fcf6efa3ff
OMAP WakeupGen is the interrupt controller extension used along with ARM GIC to wake the CPU out from low power states on external interrupts. The WakeupGen unit is responsible for generating the wakeup event from the incoming interrupts and enable bits. It is implemented in the MPU always ON power domain. During normal operation, WakeupGen delivers the external interrupts directly to the GIC. WakeupGen specification has one restriction as per Veyron version 1.6. It is SW responsibility to program interrupt enabling/disabling coherently in the GIC and in the WakeupGen enable registers. That is, a given interrupt for a given CPU is either enable at both GIC and WakeupGen, or disable at both, but no mix. That's the reason the WakeupGen is implemented as an extension of GIC. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
154 lines
3.3 KiB
C
154 lines
3.3 KiB
C
/*
|
|
* OMAP4 specific common source file.
|
|
*
|
|
* Copyright (C) 2010 Texas Instruments, Inc.
|
|
* Author:
|
|
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
|
*
|
|
*
|
|
* This program is free software,you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
#include <linux/io.h>
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <asm/hardware/gic.h>
|
|
#include <asm/hardware/cache-l2x0.h>
|
|
|
|
#include <plat/irqs.h>
|
|
|
|
#include <mach/hardware.h>
|
|
#include <mach/omap-wakeupgen.h>
|
|
|
|
#include "common.h"
|
|
#include "omap4-sar-layout.h"
|
|
|
|
#ifdef CONFIG_CACHE_L2X0
|
|
static void __iomem *l2cache_base;
|
|
#endif
|
|
|
|
static void __iomem *sar_ram_base;
|
|
|
|
void __init gic_init_irq(void)
|
|
{
|
|
void __iomem *omap_irq_base;
|
|
void __iomem *gic_dist_base_addr;
|
|
|
|
/* Static mapping, never released */
|
|
gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
|
|
BUG_ON(!gic_dist_base_addr);
|
|
|
|
/* Static mapping, never released */
|
|
omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
|
|
BUG_ON(!omap_irq_base);
|
|
|
|
omap_wakeupgen_init();
|
|
|
|
gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
|
|
}
|
|
|
|
#ifdef CONFIG_CACHE_L2X0
|
|
|
|
void __iomem *omap4_get_l2cache_base(void)
|
|
{
|
|
return l2cache_base;
|
|
}
|
|
|
|
static void omap4_l2x0_disable(void)
|
|
{
|
|
/* Disable PL310 L2 Cache controller */
|
|
omap_smc1(0x102, 0x0);
|
|
}
|
|
|
|
static void omap4_l2x0_set_debug(unsigned long val)
|
|
{
|
|
/* Program PL310 L2 Cache controller debug register */
|
|
omap_smc1(0x100, val);
|
|
}
|
|
|
|
static int __init omap_l2_cache_init(void)
|
|
{
|
|
u32 aux_ctrl = 0;
|
|
|
|
/*
|
|
* To avoid code running on other OMAPs in
|
|
* multi-omap builds
|
|
*/
|
|
if (!cpu_is_omap44xx())
|
|
return -ENODEV;
|
|
|
|
/* Static mapping, never released */
|
|
l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
|
|
if (WARN_ON(!l2cache_base))
|
|
return -ENOMEM;
|
|
|
|
/*
|
|
* 16-way associativity, parity disabled
|
|
* Way size - 32KB (es1.0)
|
|
* Way size - 64KB (es2.0 +)
|
|
*/
|
|
aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
|
|
(0x1 << 25) |
|
|
(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
|
|
(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
|
|
|
|
if (omap_rev() == OMAP4430_REV_ES1_0) {
|
|
aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
|
|
} else {
|
|
aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
|
|
(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
|
|
(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
|
|
(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
|
|
(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
|
|
}
|
|
if (omap_rev() != OMAP4430_REV_ES1_0)
|
|
omap_smc1(0x109, aux_ctrl);
|
|
|
|
/* Enable PL310 L2 Cache controller */
|
|
omap_smc1(0x102, 0x1);
|
|
|
|
l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
|
|
|
|
/*
|
|
* Override default outer_cache.disable with a OMAP4
|
|
* specific one
|
|
*/
|
|
outer_cache.disable = omap4_l2x0_disable;
|
|
outer_cache.set_debug = omap4_l2x0_set_debug;
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(omap_l2_cache_init);
|
|
#endif
|
|
|
|
void __iomem *omap4_get_sar_ram_base(void)
|
|
{
|
|
return sar_ram_base;
|
|
}
|
|
|
|
/*
|
|
* SAR RAM used to save and restore the HW
|
|
* context in low power modes
|
|
*/
|
|
static int __init omap4_sar_ram_init(void)
|
|
{
|
|
/*
|
|
* To avoid code running on other OMAPs in
|
|
* multi-omap builds
|
|
*/
|
|
if (!cpu_is_omap44xx())
|
|
return -ENOMEM;
|
|
|
|
/* Static mapping, never released */
|
|
sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
|
|
if (WARN_ON(!sar_ram_base))
|
|
return -ENOMEM;
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(omap4_sar_ram_init);
|