d8b532578f
The s3c24xx cpufreq driver needs to change the mpll speed and was doing this by writing raw values from a translation table into the MPLLCON register. Change this to use a regular clk_set_rate call when using the common clock framework and only write the raw value in the samsung_clock case. The s3c cpufreq driver does already aquire the mpll, so simply add a reference to struct s3c_cpufreq_config to let set_fvco access it. While struct clk is opaque the differenciation between samsung clock and common clock is kept, as the samsung-clock mpll clk does not implement a real set_rate. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
/*
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* Copyright (c) 2009 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/cpufreq.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu-freq-core.h>
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#include "regs-mem.h"
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/**
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* s3c2410_cpufreq_setrefresh - set SDRAM refresh value
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* @cfg: The frequency configuration
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*
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* Set the SDRAM refresh value appropriately for the configured
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* frequency.
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*/
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void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
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{
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struct s3c_cpufreq_board *board = cfg->board;
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unsigned long refresh;
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unsigned long refval;
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/* Reduce both the refresh time (in ns) and the frequency (in MHz)
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* down to ensure that we do not overflow 32 bit numbers.
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*
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* This should work for HCLK up to 133MHz and refresh period up
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* to 30usec.
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*/
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refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
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refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
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refresh = (1 << 11) + 1 - refresh;
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s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
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refval = __raw_readl(S3C2410_REFRESH);
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refval &= ~((1 << 12) - 1);
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refval |= refresh;
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__raw_writel(refval, S3C2410_REFRESH);
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}
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/**
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* s3c2410_set_fvco - set the PLL value
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* @cfg: The frequency configuration
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*/
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void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
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{
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#ifdef CONFIG_SAMSUNG_CLOCK
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__raw_writel(cfg->pll.driver_data, S3C2410_MPLLCON);
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#endif
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#ifdef CONFIG_COMMON_CLK
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if (!IS_ERR(cfg->mpll))
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clk_set_rate(cfg->mpll, cfg->pll.frequency);
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#endif
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}
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