ced3ec8aa7
Prefix messages from IDE PCI host drivers by driver name instead of marketed
chipset name (it is still possible to exactly identify the particular chipset
basing on driver messages).
As a bonus this provides nice code savings for some drivers:
text data bss dec hex filename
3826 112 8 3946 f6a drivers/ide/pci/amd74xx.o.before
2786 112 8 2906 b5a drivers/ide/pci/amd74xx.o.after
764 108 0 872 368 drivers/ide/pci/cs5520.o.before
680 108 0 788 314 drivers/ide/pci/cs5520.o.after
1680 112 4 1796 704 drivers/ide/pci/generic.o.before
1155 112 4 1271 4f7 drivers/ide/pci/generic.o.after
7128 792 0 7920 1ef0 drivers/ide/pci/hpt366.o.before
6984 792 0 7776 1e60 drivers/ide/pci/hpt366.o.after
2800 148 0 2948 b84 drivers/ide/pci/pdc202xx_new.o.before
2523 148 0 2671 a6f drivers/ide/pci/pdc202xx_new.o.after
2831 148 0 2979 ba3 drivers/ide/pci/pdc202xx_old.o.before
2683 148 0 2831 b0f drivers/ide/pci/pdc202xx_old.o.after
3776 112 4 3892 f34 drivers/ide/pci/piix.o.before
2804 112 4 2920 b68 drivers/ide/pci/piix.o.after
4693 116 0 4809 12c9 drivers/ide/pci/siimage.o.before
4600 116 0 4716 126c drivers/ide/pci/siimage.o.after
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
468 lines
13 KiB
C
468 lines
13 KiB
C
/*
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* Copyright (C) 1998-2000 Michel Aubry
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* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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* Portions copyright (c) 2001 Sun Microsystems
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*
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*
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* RCC/ServerWorks IDE driver for Linux
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*
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* OSB4: `Open South Bridge' IDE Interface (fn 1)
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* supports UDMA mode 2 (33 MB/s)
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*
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* CSB5: `Champion South Bridge' IDE Interface (fn 1)
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* all revisions support UDMA mode 4 (66 MB/s)
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* revision A2.0 and up support UDMA mode 5 (100 MB/s)
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*
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* *** The CSB5 does not provide ANY register ***
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* *** to detect 80-conductor cable presence. ***
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*
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* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
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*
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* HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
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* controller same as the CSB6. Single channel ATA100 only.
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*
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* Documentation:
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* Available under NDA only. Errata info very hard to get.
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*
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#define DRV_NAME "serverworks"
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#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
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#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
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/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
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* can overrun their FIFOs when used with the CSB5 */
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static const char *svwks_bad_ata100[] = {
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"ST320011A",
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"ST340016A",
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"ST360021A",
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"ST380021A",
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NULL
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};
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static struct pci_dev *isa_dev;
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static int check_in_drive_lists (ide_drive_t *drive, const char **list)
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{
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while (*list)
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if (!strcmp(*list++, drive->id->model))
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return 1;
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return 0;
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}
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static u8 svwks_udma_filter(ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u8 mask = 0;
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if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
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return 0x1f;
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if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
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u32 reg = 0;
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if (isa_dev)
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pci_read_config_dword(isa_dev, 0x64, ®);
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/*
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* Don't enable UDMA on disk devices for the moment
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*/
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if(drive->media == ide_disk)
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return 0;
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/* Check the OSB4 DMA33 enable bit */
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return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
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} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
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return 0x07;
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} else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
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u8 btr = 0, mode;
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pci_read_config_byte(dev, 0x5A, &btr);
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mode = btr & 0x3;
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/* If someone decides to do UDMA133 on CSB5 the same
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issue will bite so be inclusive */
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if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
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mode = 2;
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switch(mode) {
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case 3: mask = 0x3f; break;
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case 2: mask = 0x1f; break;
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case 1: mask = 0x07; break;
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default: mask = 0x00; break;
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}
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}
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if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
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(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
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(!(PCI_FUNC(dev->devfn) & 1)))
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mask = 0x1f;
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return mask;
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}
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static u8 svwks_csb_check (struct pci_dev *dev)
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{
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switch (dev->device) {
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case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
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case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
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case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
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case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
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return 1;
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default:
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break;
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}
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return 0;
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}
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static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
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static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
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if (svwks_csb_check(dev)) {
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u16 csb_pio = 0;
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pci_read_config_word(dev, 0x4a, &csb_pio);
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csb_pio &= ~(0x0f << (4 * drive->dn));
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csb_pio |= (pio << (4 * drive->dn));
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pci_write_config_word(dev, 0x4a, csb_pio);
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}
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}
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static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
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static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
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static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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u8 unit = (drive->select.b.unit & 0x01);
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u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
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pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
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pci_read_config_byte(dev, 0x54, &ultra_enable);
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ultra_timing &= ~(0x0F << (4*unit));
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ultra_enable &= ~(0x01 << drive->dn);
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if (speed >= XFER_UDMA_0) {
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dma_timing |= dma_modes[2];
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ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
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ultra_enable |= (0x01 << drive->dn);
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} else if (speed >= XFER_MW_DMA_0)
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dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
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pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
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pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
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pci_write_config_byte(dev, 0x54, ultra_enable);
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}
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static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
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{
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unsigned int reg;
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u8 btr;
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/* force Master Latency Timer value to 64 PCICLKs */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
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/* OSB4 : South Bridge and IDE */
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if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
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isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
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PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
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if (isa_dev) {
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pci_read_config_dword(isa_dev, 0x64, ®);
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reg &= ~0x00002000; /* disable 600ns interrupt mask */
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if(!(reg & 0x00004000))
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printk(KERN_DEBUG "%s %s: UDMA not BIOS "
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"enabled.\n", name, pci_name(dev));
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reg |= 0x00004000; /* enable UDMA/33 support */
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pci_write_config_dword(isa_dev, 0x64, reg);
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}
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}
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/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
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else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
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(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
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(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
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/* Third Channel Test */
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if (!(PCI_FUNC(dev->devfn) & 1)) {
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struct pci_dev * findev = NULL;
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u32 reg4c = 0;
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findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
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PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
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if (findev) {
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pci_read_config_dword(findev, 0x4C, ®4c);
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reg4c &= ~0x000007FF;
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reg4c |= 0x00000040;
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reg4c |= 0x00000020;
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pci_write_config_dword(findev, 0x4C, reg4c);
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pci_dev_put(findev);
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}
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outb_p(0x06, 0x0c00);
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dev->irq = inb_p(0x0c01);
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} else {
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struct pci_dev * findev = NULL;
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u8 reg41 = 0;
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findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
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PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
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if (findev) {
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pci_read_config_byte(findev, 0x41, ®41);
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reg41 &= ~0x40;
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pci_write_config_byte(findev, 0x41, reg41);
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pci_dev_put(findev);
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}
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/*
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* This is a device pin issue on CSB6.
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* Since there will be a future raid mode,
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* early versions of the chipset require the
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* interrupt pin to be set, and it is a compatibility
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* mode issue.
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*/
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if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
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dev->irq = 0;
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}
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// pci_read_config_dword(dev, 0x40, &pioreg)
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// pci_write_config_dword(dev, 0x40, 0x99999999);
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// pci_read_config_dword(dev, 0x44, &dmareg);
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// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
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/* setup the UDMA Control register
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*
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* 1. clear bit 6 to enable DMA
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* 2. enable DMA modes with bits 0-1
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* 00 : legacy
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* 01 : udma2
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* 10 : udma2/udma4
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* 11 : udma2/udma4/udma5
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*/
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pci_read_config_byte(dev, 0x5A, &btr);
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btr &= ~0x40;
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if (!(PCI_FUNC(dev->devfn) & 1))
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btr |= 0x2;
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else
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btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
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pci_write_config_byte(dev, 0x5A, btr);
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}
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/* Setup HT1000 SouthBridge Controller - Single Channel Only */
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else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
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pci_read_config_byte(dev, 0x5A, &btr);
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btr &= ~0x40;
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btr |= 0x3;
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pci_write_config_byte(dev, 0x5A, btr);
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}
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return dev->irq;
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}
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static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif)
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{
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return ATA_CBL_PATA80;
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}
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/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
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* of the subsystem device ID indicate presence of an 80-pin cable.
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* Bit 15 clear = secondary IDE channel does not have 80-pin cable.
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* Bit 15 set = secondary IDE channel has 80-pin cable.
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* Bit 14 clear = primary IDE channel does not have 80-pin cable.
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* Bit 14 set = primary IDE channel has 80-pin cable.
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*/
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static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
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dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
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(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
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dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
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return ((1 << (hwif->channel + 14)) &
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dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
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return ATA_CBL_PATA40;
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}
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/* Sun Cobalt Alpine hardware avoids the 80-pin cable
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* detect issue by attaching the drives directly to the board.
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* This check follows the Dell precedent (how scary is that?!)
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*
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* WARNING: this only works on Alpine hardware!
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*/
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static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
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dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
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dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
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return ((1 << (hwif->channel + 14)) &
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dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
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return ATA_CBL_PATA40;
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}
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static u8 __devinit svwks_cable_detect(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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/* Server Works */
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if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
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return ata66_svwks_svwks (hwif);
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/* Dell PowerEdge */
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if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
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return ata66_svwks_dell (hwif);
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/* Cobalt Alpine */
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if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
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return ata66_svwks_cobalt (hwif);
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/* Per Specified Design by OEM, and ASIC Architect */
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if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
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(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
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return ATA_CBL_PATA80;
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return ATA_CBL_PATA40;
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}
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static const struct ide_port_ops osb4_port_ops = {
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.set_pio_mode = svwks_set_pio_mode,
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.set_dma_mode = svwks_set_dma_mode,
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.udma_filter = svwks_udma_filter,
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};
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static const struct ide_port_ops svwks_port_ops = {
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.set_pio_mode = svwks_set_pio_mode,
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.set_dma_mode = svwks_set_dma_mode,
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.udma_filter = svwks_udma_filter,
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.cable_detect = svwks_cable_detect,
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};
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#define IDE_HFLAGS_SVWKS IDE_HFLAG_LEGACY_IRQS
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static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
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{ /* 0: OSB4 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_svwks,
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.port_ops = &osb4_port_ops,
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.host_flags = IDE_HFLAGS_SVWKS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = 0x00, /* UDMA is problematic on OSB4 */
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},
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{ /* 1: CSB5 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_svwks,
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.port_ops = &svwks_port_ops,
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.host_flags = IDE_HFLAGS_SVWKS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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},
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{ /* 2: CSB6 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_svwks,
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.port_ops = &svwks_port_ops,
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.host_flags = IDE_HFLAGS_SVWKS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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},
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{ /* 3: CSB6-2 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_svwks,
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.port_ops = &svwks_port_ops,
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.host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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},
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{ /* 4: HT1000 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_svwks,
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.port_ops = &svwks_port_ops,
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.host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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}
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};
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/**
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* svwks_init_one - called when a OSB/CSB is found
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* @dev: the svwks device
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* @id: the matching pci id
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*
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* Called when the PCI registration layer (or the IDE initialization)
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* finds a device matching our IDE device tables.
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*/
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static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct ide_port_info d;
|
|
u8 idx = id->driver_data;
|
|
|
|
d = serverworks_chipsets[idx];
|
|
|
|
if (idx == 1)
|
|
d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
|
|
else if (idx == 2 || idx == 3) {
|
|
if ((PCI_FUNC(dev->devfn) & 1) == 0) {
|
|
if (pci_resource_start(dev, 0) != 0x01f1)
|
|
d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
|
|
d.host_flags |= IDE_HFLAG_SINGLE;
|
|
} else
|
|
d.host_flags &= ~IDE_HFLAG_SINGLE;
|
|
}
|
|
|
|
return ide_pci_init_one(dev, &d, NULL);
|
|
}
|
|
|
|
static const struct pci_device_id svwks_pci_tbl[] = {
|
|
{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 },
|
|
{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 },
|
|
{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 },
|
|
{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 },
|
|
{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
|
|
{ 0, },
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
|
|
|
|
static struct pci_driver driver = {
|
|
.name = "Serverworks_IDE",
|
|
.id_table = svwks_pci_tbl,
|
|
.probe = svwks_init_one,
|
|
.remove = ide_pci_remove,
|
|
};
|
|
|
|
static int __init svwks_ide_init(void)
|
|
{
|
|
return ide_pci_register_driver(&driver);
|
|
}
|
|
|
|
static void __exit svwks_ide_exit(void)
|
|
{
|
|
pci_unregister_driver(&driver);
|
|
}
|
|
|
|
module_init(svwks_ide_init);
|
|
module_exit(svwks_ide_exit);
|
|
|
|
MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
|
|
MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
|
|
MODULE_LICENSE("GPL");
|