bdea6c657e
On KZM-A9-GT board (SMP), when CONFIG_THUMB2_KERNEL=y it fails to compile AS arch/arm/mach-shmobile/headsmp-scu.o /proj/koba/kernel/arm-soc/arch/arm/mach-shmobile/headsmp-scu.S: Assembler messages: /proj/koba/kernel/arm-soc/arch/arm/mach-shmobile/headsmp-scu.S:41: Error: shift must be constant -- `bic r2,r2,r3,lsl r1' make[2]: *** [arch/arm/mach-shmobile/headsmp-scu.o] Error 1 make[1]: *** [arch/arm/mach-shmobile] Error 2 make: *** [sub-make] Error 2 Instruction `bic r2,r2,r3,lsl r1' is not supported in thumb mode. This patch split it into 2 instructions. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
52 lines
1.5 KiB
ArmAsm
52 lines
1.5 KiB
ArmAsm
/*
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* Shared SCU setup for mach-shmobile
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*
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* Copyright (C) 2012 Bastian Hecht
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/memory.h>
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__CPUINIT
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/*
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* Boot code for secondary CPUs.
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*
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* First we turn on L1 cache coherency for our CPU. Then we jump to
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* shmobile_invalidate_start that invalidates the cache and hands over control
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* to the common ARM startup code.
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*/
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ENTRY(shmobile_boot_scu)
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@ r0 = SCU base address
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mrc p15, 0, r1, c0, c0, 5 @ read MIPDR
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and r1, r1, #3 @ mask out cpu ID
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lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
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ldr r2, [r0, #8] @ SCU Power Status Register
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mov r3, #3
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lsl r3, r3, r1
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bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
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str r2, [r0, #8] @ write back
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b shmobile_invalidate_start
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ENDPROC(shmobile_boot_scu)
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.text
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.globl shmobile_scu_base
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shmobile_scu_base:
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.space 4
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