Lucas Stach 470ee7ab77 clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 ... commit 797097301860c64b63346d068ba4fe4992bd5021 upstream. The post divider value in the frequency table is wrong as it would lead to the PLL producing an output rate of 960 MHz instead of the desired 480 MHz. This wasn't a problem as nothing used the table to actually initialize the PLL rate, but the bootloader configuration was used unaltered. If the bootloader does not set up the PLL it will fail to come when used under Linux. To fix this don't rely on the bootloader, but set the correct rate in the clock driver. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Thierry Reding <treding@nvidia.com> [jonathanh@nvidia.com: Back-ported to stable v4.4.y] Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2018-07-25 10:18:32 +02:00
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at91
bcm	clk: bcm2835: De-assert/assert PLL reset signal when appropriate	2018-04-24 09:32:08 +02:00
berlin
h8300
hisilicon
imx	clk: imx6: refine hdmi_isfr's parent to make HDMI work on i.MX6 SoCs w/o VPU	2017-12-20 10:04:59 +01:00
ingenic
keystone
mediatek	clk: mediatek: add the option for determining PLL source clock	2017-12-20 10:04:59 +01:00
meson
mmp
mvebu	clk: mvebu: armada-38x: add support for missing clocks	2018-04-24 09:32:08 +02:00
mxs
nxp
pistachio
pxa
qcom	clk: qcom: msm8916: fix mnd_width for codec_digcodec	2018-03-22 09:23:28 +01:00
rockchip	clk: rockchip: Prevent calculating mmc phase if clock rate is zero	2018-05-30 07:49:14 +02:00
samsung	clk: samsung: exynos3250: Fix PLL rates	2018-05-30 07:49:16 +02:00
shmobile
sirf
socfpga
spear
st
sunxi
tegra	clk: tegra: Fix PLL_U post divider and initial rate on Tegra30	2018-07-25 10:18:32 +02:00
ti
ux500
versatile
x86
zte
zynq
clk-asm9260.c
clk-axi-clkgen.c
clk-axm5516.c
clk-cdce706.c
clk-cdce925.c
clk-clps711x.c
clk-composite.c
clk-conf.c	clk: Fix __set_clk_rates error print-string	2018-04-13 19:50:16 +02:00
clk-devres.c
clk-divider.c
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-gate.c
clk-gpio.c
clk-highbank.c
clk-ls1x.c
clk-max-gen.c
clk-max-gen.h
clk-max77686.c
clk-max77802.c
clk-mb86s7x.c
clk-moxart.c
clk-multiplier.c
clk-mux.c
clk-nomadik.c
clk-nspire.c
clk-palmas.c
clk-pwm.c
clk-qoriq.c
clk-rk808.c
clk-s2mps11.c
clk-scpi.c	clk: scpi: fix return type of __scpi_dvfs_round_rate	2018-04-13 19:50:16 +02:00
clk-si514.c
clk-si570.c
clk-si5351.c	clk: si5351: Rename internal plls to avoid name collisions	2018-03-24 10:58:48 +01:00
clk-si5351.h
clk-stm32f4.c
clk-twl6040.c
clk-u300.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c	clk: Don't show the incorrect clock phase	2018-05-30 07:49:11 +02:00
clk.h
clkdev.c
Kconfig
Makefile