7d7e1eba7e
As the interrupts should only be defined in the platform_data, and eventually coming from device tree, there's no need to define them in header files. Let's remove the hardcoded references to irqs.h and fix up the includes so we don't rely on headers included in irqs.h. Note that we're defining OMAP_INTC_START as 0 to the interrupts. This will be needed when we enable SPARSE_IRQ. For some drivers we need to add #include <plat/cpu.h> for now until these drivers are fixed to remove cpu_is_omapxxxx() usage. While at it, sort som of the includes the standard way, and add the trailing commas where they are missing in the related data structures. Note that for drivers/staging/tidspbridge we just define things locally. Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
234 lines
5.6 KiB
C
234 lines
5.6 KiB
C
/*
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* linux/arch/arm/mach-omap2/mcbsp.c
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*
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* Copyright (C) 2008 Instituto Nokia de Tecnologia
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* Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Multichannel mode not supported.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <plat/dma.h>
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#include <plat/cpu.h>
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#include <plat/mcbsp.h>
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#include <plat/omap_device.h>
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#include <linux/pm_runtime.h>
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#include "control.h"
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/*
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* FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
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* Sidetone needs non-gated ICLK and sidetone autoidle is broken.
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*/
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-34xx.h"
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/* McBSP1 internal signal muxing function for OMAP2/3 */
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static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
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const char *src)
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{
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u32 v;
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v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
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if (!strcmp(signal, "clkr")) {
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if (!strcmp(src, "clkr"))
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v &= ~OMAP2_MCBSP1_CLKR_MASK;
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else if (!strcmp(src, "clkx"))
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v |= OMAP2_MCBSP1_CLKR_MASK;
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else
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return -EINVAL;
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} else if (!strcmp(signal, "fsr")) {
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if (!strcmp(src, "fsr"))
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v &= ~OMAP2_MCBSP1_FSR_MASK;
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else if (!strcmp(src, "fsx"))
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v |= OMAP2_MCBSP1_FSR_MASK;
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else
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return -EINVAL;
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} else {
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return -EINVAL;
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}
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omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
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return 0;
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}
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/* McBSP4 internal signal muxing function for OMAP4 */
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#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31)
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#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30)
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static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
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const char *src)
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{
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u32 v;
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/*
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* In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
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* mux) is used */
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v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
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if (!strcmp(signal, "clkr")) {
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if (!strcmp(src, "clkr"))
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v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
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else if (!strcmp(src, "clkx"))
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v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
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else
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return -EINVAL;
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} else if (!strcmp(signal, "fsr")) {
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if (!strcmp(src, "fsr"))
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v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
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else if (!strcmp(src, "fsx"))
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v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
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else
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return -EINVAL;
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} else {
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return -EINVAL;
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}
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omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
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return 0;
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}
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/* McBSP CLKS source switching function */
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static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
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const char *src)
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{
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struct clk *fck_src;
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char *fck_src_name;
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int r;
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if (!strcmp(src, "clks_ext"))
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fck_src_name = "pad_fck";
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else if (!strcmp(src, "clks_fclk"))
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fck_src_name = "prcm_fck";
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else
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return -EINVAL;
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fck_src = clk_get(dev, fck_src_name);
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if (IS_ERR_OR_NULL(fck_src)) {
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pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
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fck_src_name);
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return -EINVAL;
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}
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pm_runtime_put_sync(dev);
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r = clk_set_parent(clk, fck_src);
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if (IS_ERR_VALUE(r)) {
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pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
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"clks", fck_src_name);
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clk_put(fck_src);
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return -EINVAL;
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}
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pm_runtime_get_sync(dev);
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clk_put(fck_src);
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return 0;
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}
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static int omap3_enable_st_clock(unsigned int id, bool enable)
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{
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unsigned int w;
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/*
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* Sidetone uses McBSP ICLK - which must not idle when sidetones
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* are enabled or sidetones start sounding ugly.
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*/
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w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
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if (enable)
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w &= ~(1 << (id - 2));
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else
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w |= 1 << (id - 2);
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omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
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return 0;
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}
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static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
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{
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int id, count = 1;
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char *name = "omap-mcbsp";
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struct omap_hwmod *oh_device[2];
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struct omap_mcbsp_platform_data *pdata = NULL;
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struct platform_device *pdev;
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sscanf(oh->name, "mcbsp%d", &id);
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pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
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if (!pdata) {
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pr_err("%s: No memory for mcbsp\n", __func__);
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return -ENOMEM;
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}
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pdata->reg_step = 4;
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if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
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pdata->reg_size = 2;
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} else {
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pdata->reg_size = 4;
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pdata->has_ccr = true;
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}
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pdata->set_clk_src = omap2_mcbsp_set_clk_src;
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/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
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if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
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pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
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/* On OMAP4 the McBSP4 port has 6 pin configuration */
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if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
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pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
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if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
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if (id == 2)
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/* The FIFO has 1024 + 256 locations */
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pdata->buffer_size = 0x500;
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else
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/* The FIFO has 128 locations */
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pdata->buffer_size = 0x80;
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} else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
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/* The FIFO has 128 locations for all instances */
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pdata->buffer_size = 0x80;
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}
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if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
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pdata->has_wakeup = true;
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oh_device[0] = oh;
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if (oh->dev_attr) {
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oh_device[1] = omap_hwmod_lookup((
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(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
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pdata->enable_st_clock = omap3_enable_st_clock;
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count++;
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}
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pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
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sizeof(*pdata), NULL, 0, false);
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kfree(pdata);
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if (IS_ERR(pdev)) {
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pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
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name, oh->name);
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return PTR_ERR(pdev);
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}
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return 0;
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}
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static int __init omap2_mcbsp_init(void)
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{
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omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
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return 0;
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}
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arch_initcall(omap2_mcbsp_init);
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