1f72e4045d
This patch removes legacy UART initialization code that was used to set up UART platform devices when booting with ATAGS, which is not supported on Exynos any more. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
601 lines
15 KiB
C
601 lines
15 KiB
C
/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Common Codes for EXYNOS
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/gpio.h>
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#include <clocksource/samsung_pwm.h>
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#include <linux/sched.h>
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#include <linux/serial_core.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <linux/of_irq.h>
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#include <linux/export.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/clocksource.h>
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#include <linux/clk-provider.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/chained_irq.h>
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#include <asm/proc-fns.h>
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#include <asm/exception.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/cacheflush.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-pmu.h>
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#include <mach/regs-gpio.h>
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#include <mach/irqs.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/pm.h>
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#include <plat/sdhci.h>
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#include <plat/gpio-cfg.h>
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#include <plat/adc-core.h>
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#include <plat/fb-core.h>
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#include <plat/fimc-core.h>
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#include <plat/iic-core.h>
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#include <plat/tv-core.h>
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#include <plat/spi-core.h>
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#include <plat/regs-serial.h>
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#include "common.h"
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#define L2_AUX_VAL 0x7C470001
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#define L2_AUX_MASK 0xC200ffff
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static const char name_exynos4210[] = "EXYNOS4210";
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static const char name_exynos4212[] = "EXYNOS4212";
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static const char name_exynos4412[] = "EXYNOS4412";
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static const char name_exynos5250[] = "EXYNOS5250";
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static const char name_exynos5440[] = "EXYNOS5440";
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static void exynos4_map_io(void);
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static void exynos5_map_io(void);
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static void exynos5440_map_io(void);
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static int exynos_init(void);
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unsigned long xxti_f = 0, xusbxti_f = 0;
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = EXYNOS4210_CPU_ID,
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.idmask = EXYNOS4_CPU_MASK,
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.map_io = exynos4_map_io,
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.init = exynos_init,
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.name = name_exynos4210,
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}, {
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.idcode = EXYNOS4212_CPU_ID,
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.idmask = EXYNOS4_CPU_MASK,
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.map_io = exynos4_map_io,
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.init = exynos_init,
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.name = name_exynos4212,
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}, {
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.idcode = EXYNOS4412_CPU_ID,
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.idmask = EXYNOS4_CPU_MASK,
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.map_io = exynos4_map_io,
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.init = exynos_init,
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.name = name_exynos4412,
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}, {
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.idcode = EXYNOS5250_SOC_ID,
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.idmask = EXYNOS5_SOC_MASK,
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.map_io = exynos5_map_io,
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.init = exynos_init,
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.name = name_exynos5250,
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}, {
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.idcode = EXYNOS5440_SOC_ID,
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.idmask = EXYNOS5_SOC_MASK,
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.map_io = exynos5440_map_io,
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.init = exynos_init,
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.name = name_exynos5440,
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},
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};
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/* Initial IO mappings */
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static struct map_desc exynos_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_CHIPID,
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.pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_TIMER,
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.pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_WATCHDOG,
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.pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SYSTIMER,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_PMU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
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.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GIC_CPU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GIC_DIST,
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.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(EXYNOS4_PA_UART),
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.length = SZ_512K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_CMU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
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.length = SZ_128K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
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.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
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.length = SZ_8K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_L2CC,
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.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_DMC0,
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.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_DMC1,
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.pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_USB_HSPHY,
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.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos4_iodesc0[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_SYSRAM,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos4_iodesc1[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_SYSRAM,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos4210_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
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.pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos4x12_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
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.pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos5250_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
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.pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos5_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_TIMER,
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.pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_WATCHDOG,
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.pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SYSRAM,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_CMU,
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.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
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.length = 144 * SZ_1K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_PMU,
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.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(EXYNOS5_PA_UART),
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.length = SZ_512K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc exynos5440_iodesc0[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
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.length = SZ_512K,
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.type = MT_DEVICE,
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},
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};
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static struct samsung_pwm_variant exynos4_pwm_variant = {
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.bits = 32,
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.div_base = 0,
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.has_tint_cstat = true,
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.tclk_mask = 0,
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};
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void exynos4_restart(char mode, const char *cmd)
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{
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__raw_writel(0x1, S5P_SWRESET);
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}
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void exynos5_restart(char mode, const char *cmd)
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{
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struct device_node *np;
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u32 val;
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void __iomem *addr;
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if (of_machine_is_compatible("samsung,exynos5250")) {
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val = 0x1;
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addr = EXYNOS_SWRESET;
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} else if (of_machine_is_compatible("samsung,exynos5440")) {
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u32 status;
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
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addr = of_iomap(np, 0) + 0xbc;
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status = __raw_readl(addr);
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addr = of_iomap(np, 0) + 0xcc;
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val = __raw_readl(addr);
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val = (val & 0xffff0000) | (status & 0xffff);
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} else {
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pr_err("%s: cannot support non-DT\n", __func__);
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return;
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}
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__raw_writel(val, addr);
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}
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void __init exynos_init_late(void)
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{
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if (of_machine_is_compatible("samsung,exynos5440"))
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/* to be supported later */
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return;
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exynos_pm_late_initcall();
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}
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int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
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int depth, void *data)
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{
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struct map_desc iodesc;
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__be32 *reg;
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unsigned long len;
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if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
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!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
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return 0;
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reg = of_get_flat_dt_prop(node, "reg", &len);
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if (reg == NULL || len != (sizeof(unsigned long) * 2))
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return 0;
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iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
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iodesc.length = be32_to_cpu(reg[1]) - 1;
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iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
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iodesc.type = MT_DEVICE;
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iotable_init(&iodesc, 1);
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return 1;
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}
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/*
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* exynos_map_io
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*
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* register the standard cpu IO areas
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*/
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void __init exynos_init_io(struct map_desc *mach_desc, int size)
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{
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debug_ll_io_init();
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if (initial_boot_params)
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of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
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else
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iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
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if (mach_desc)
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iotable_init(mach_desc, size);
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/* detect cpu id and rev. */
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s5p_init_cpu(S5P_VA_CHIPID);
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s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
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}
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static void __init exynos4_map_io(void)
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{
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iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
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if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
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iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
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else
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iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
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if (soc_is_exynos4210())
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iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
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if (soc_is_exynos4212() || soc_is_exynos4412())
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iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
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/* initialize device information early */
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exynos4_default_sdhci0();
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exynos4_default_sdhci1();
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exynos4_default_sdhci2();
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exynos4_default_sdhci3();
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s3c_adc_setname("samsung-adc-v3");
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s3c_fimc_setname(0, "exynos4-fimc");
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s3c_fimc_setname(1, "exynos4-fimc");
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s3c_fimc_setname(2, "exynos4-fimc");
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s3c_fimc_setname(3, "exynos4-fimc");
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s3c_sdhci_setname(0, "exynos4-sdhci");
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s3c_sdhci_setname(1, "exynos4-sdhci");
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s3c_sdhci_setname(2, "exynos4-sdhci");
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s3c_sdhci_setname(3, "exynos4-sdhci");
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/* The I2C bus controllers are directly compatible with s3c2440 */
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s3c_i2c0_setname("s3c2440-i2c");
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s3c_i2c1_setname("s3c2440-i2c");
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s3c_i2c2_setname("s3c2440-i2c");
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s5p_fb_setname(0, "exynos4-fb");
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s5p_hdmi_setname("exynos4-hdmi");
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s3c64xx_spi_setname("exynos4210-spi");
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}
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static void __init exynos5_map_io(void)
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{
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iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
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if (soc_is_exynos5250())
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iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
|
|
}
|
|
|
|
static void __init exynos5440_map_io(void)
|
|
{
|
|
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
|
|
}
|
|
|
|
void __init exynos_set_timer_source(u8 channels)
|
|
{
|
|
exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
|
|
exynos4_pwm_variant.output_mask &= ~channels;
|
|
}
|
|
|
|
void __init exynos_init_time(void)
|
|
{
|
|
unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
|
|
EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC,
|
|
EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
|
|
EXYNOS4_IRQ_TIMER4_VIC,
|
|
};
|
|
|
|
if (of_have_populated_dt()) {
|
|
of_clk_init(NULL);
|
|
clocksource_of_init();
|
|
} else {
|
|
/* todo: remove after migrating legacy E4 platforms to dt */
|
|
#ifdef CONFIG_ARCH_EXYNOS4
|
|
exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
|
|
exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
|
|
#endif
|
|
#ifdef CONFIG_CLKSRC_SAMSUNG_PWM
|
|
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
|
|
samsung_pwm_clocksource_init(S3C_VA_TIMER,
|
|
timer_irqs, &exynos4_pwm_variant);
|
|
else
|
|
#endif
|
|
mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
|
|
EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
|
|
}
|
|
}
|
|
|
|
static unsigned int max_combiner_nr(void)
|
|
{
|
|
if (soc_is_exynos5250())
|
|
return EXYNOS5_MAX_COMBINER_NR;
|
|
else if (soc_is_exynos4412())
|
|
return EXYNOS4412_MAX_COMBINER_NR;
|
|
else if (soc_is_exynos4212())
|
|
return EXYNOS4212_MAX_COMBINER_NR;
|
|
else
|
|
return EXYNOS4210_MAX_COMBINER_NR;
|
|
}
|
|
|
|
|
|
void __init exynos4_init_irq(void)
|
|
{
|
|
unsigned int gic_bank_offset;
|
|
|
|
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
|
|
|
|
if (!of_have_populated_dt())
|
|
gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
|
|
else
|
|
irqchip_init();
|
|
|
|
if (!of_have_populated_dt())
|
|
combiner_init(S5P_VA_COMBINER_BASE, NULL,
|
|
max_combiner_nr(), COMBINER_IRQ(0, 0));
|
|
|
|
gic_arch_extn.irq_set_wake = s3c_irq_wake;
|
|
}
|
|
|
|
void __init exynos5_init_irq(void)
|
|
{
|
|
irqchip_init();
|
|
gic_arch_extn.irq_set_wake = s3c_irq_wake;
|
|
}
|
|
|
|
struct bus_type exynos_subsys = {
|
|
.name = "exynos-core",
|
|
.dev_name = "exynos-core",
|
|
};
|
|
|
|
static struct device exynos4_dev = {
|
|
.bus = &exynos_subsys,
|
|
};
|
|
|
|
static int __init exynos_core_init(void)
|
|
{
|
|
return subsys_system_register(&exynos_subsys, NULL);
|
|
}
|
|
core_initcall(exynos_core_init);
|
|
|
|
#ifdef CONFIG_CACHE_L2X0
|
|
static int __init exynos4_l2x0_cache_init(void)
|
|
{
|
|
int ret;
|
|
|
|
if (soc_is_exynos5250() || soc_is_exynos5440())
|
|
return 0;
|
|
|
|
ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
|
|
if (!ret) {
|
|
l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
|
|
clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
|
|
return 0;
|
|
}
|
|
|
|
if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
|
|
l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
|
|
/* TAG, Data Latency Control: 2 cycles */
|
|
l2x0_saved_regs.tag_latency = 0x110;
|
|
|
|
if (soc_is_exynos4212() || soc_is_exynos4412())
|
|
l2x0_saved_regs.data_latency = 0x120;
|
|
else
|
|
l2x0_saved_regs.data_latency = 0x110;
|
|
|
|
l2x0_saved_regs.prefetch_ctrl = 0x30000007;
|
|
l2x0_saved_regs.pwr_ctrl =
|
|
(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
|
|
|
|
l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
|
|
|
|
__raw_writel(l2x0_saved_regs.tag_latency,
|
|
S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
|
|
__raw_writel(l2x0_saved_regs.data_latency,
|
|
S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
|
|
|
|
/* L2X0 Prefetch Control */
|
|
__raw_writel(l2x0_saved_regs.prefetch_ctrl,
|
|
S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
|
|
|
|
/* L2X0 Power Control */
|
|
__raw_writel(l2x0_saved_regs.pwr_ctrl,
|
|
S5P_VA_L2CC + L2X0_POWER_CTRL);
|
|
|
|
clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
|
|
clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
|
|
}
|
|
|
|
l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
|
|
return 0;
|
|
}
|
|
early_initcall(exynos4_l2x0_cache_init);
|
|
#endif
|
|
|
|
static int __init exynos_init(void)
|
|
{
|
|
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
|
|
|
|
return device_register(&exynos4_dev);
|
|
}
|