02b4e2756e
All ARMv5 and older CPUs invalidate their caches in the early assembly setup function, prior to enabling the MMU. This is because the L1 cache should not contain any data relevant to the execution of the kernel at this point; all data should have been flushed out to memory. This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, these typically do not search their caches when caching is disabled (as it needs to be when the MMU is disabled) so this change should be safe. ARMv7 allows there to be CPUs which search their caches while caching is disabled, and it's permitted that the cache is uninitialised at boot; for these, the architecture reference manual requires that an implementation specific code sequence is used immediately after reset to ensure that the cache is placed into a sane state. Such functionality is definitely outside the remit of the Linux kernel, and must be done by the SoC's firmware before _any_ CPU gets to the Linux kernel. Changing the data cache clean+invalidate to a mere invalidate allows us to get rid of a lot of platform specific hacks around this issue for their secondary CPU bringup paths - some of which were buggy. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
106 lines
2.8 KiB
C
106 lines
2.8 KiB
C
/*
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* Copyright 2010-2011 Calxeda, Inc.
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* Copyright 2012 Pavel Machek <pavel@denx.de>
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* Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
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* Copyright (C) 2012 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#include "core.h"
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static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
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if (socfpga_cpu1start_addr) {
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/* This will put CPU #1 into reset. */
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writel(RSTMGR_MPUMODRST_CPU1,
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rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
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memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
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writel(virt_to_phys(secondary_startup),
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sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
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flush_cache_all();
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smp_wmb();
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outer_clean_range(0, trampoline_size);
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/* This will release CPU #1 out of reset. */
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writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
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}
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return 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init socfpga_smp_init_cpus(void)
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{
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unsigned int i, ncores;
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ncores = scu_get_core_count(socfpga_scu_base_addr);
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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/* sanity check */
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if (ncores > num_possible_cpus()) {
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pr_warn("socfpga: no. of cores (%d) greater than configured"
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"maximum of %d - clipping\n", ncores, num_possible_cpus());
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ncores = num_possible_cpus();
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(socfpga_scu_base_addr);
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}
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/*
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* platform-specific code to shutdown a CPU
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*
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* Called with IRQs disabled
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*/
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static void socfpga_cpu_die(unsigned int cpu)
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{
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/* Do WFI. If we wake up early, go back into WFI */
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while (1)
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cpu_do_idle();
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}
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struct smp_operations socfpga_smp_ops __initdata = {
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.smp_init_cpus = socfpga_smp_init_cpus,
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.smp_prepare_cpus = socfpga_smp_prepare_cpus,
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.smp_boot_secondary = socfpga_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = socfpga_cpu_die,
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#endif
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};
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