The main update this time around is the addition of a standard DT
binding for specifying the endianness of devices. This allows drivers
to support any endianness of device register map without any code,
useful for configurable IP blocks.
There's also a few bug fixes that I didn't get round to sending, none of
them terribly severe or new, and a reduction in size for struct regmap.
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Merge tag 'regmap-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap
Pull regmap updates from Mark Brown:
"The main update this time around is the addition of a standard DT
binding for specifying the endianness of devices. This allows drivers
to support any endianness of device register map without any code,
useful for configurable IP blocks.
There's also a few bug fixes that I didn't get round to sending, none
of them terribly severe or new, and a reduction in size for struct
regmap"
* tag 'regmap-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap:
regmap: Fix debugfs-file 'registers' mode
regmap: fix possible ZERO_SIZE_PTR pointer dereferencing error.
regmap: debugfs: fix possbile NULL pointer dereference
regmap: fix NULL pointer dereference in _regmap_write/read
regmap: fix NULL pointer dereference in regmap_get_val_endian
regmap: cache: Do not fail silently from regcache_sync calls
regmap: change struct regmap's internal locks as union
regmap: Split regmap_get_endian() in two functions
regmap: of_regmap_get_endian() cleanup
regmap: Fix DT endianess parsing logic
regmap: Add explicit dependencies to catch "select" misuse
regmap: Restore L: linux-kernel@vger.kernel.org entry
regmap: Add the DT binding documentation for endianness
regmap: add DT endianness binding support.
development series:
- New drivers for the Freescale i.MX21, Qualcomm APQ8084
pin controllers.
- Incremental new features on the Rockchip, atlas 6,
OMAP, AM437x, APQ8064, prima2, AT91, Tegra, i.MX, Berlin
and Nomadik.
- Push Freescale drivers down into their own subdirectory.
- Assorted sprays of syntax and semantic fixes.
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Merge tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij:
"This is the bulk of pin control changes for the v3.18 development
series:
- New drivers for the Freescale i.MX21, Qualcomm APQ8084 pin
controllers.
- Incremental new features on the Rockchip, atlas 6, OMAP, AM437x,
APQ8064, prima2, AT91, Tegra, i.MX, Berlin and Nomadik.
- Push Freescale drivers down into their own subdirectory.
- Assorted sprays of syntax and semantic fixes"
* tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits)
pinctrl: specify bindings for pins and groups
pinctrl: nomadik: improve GPIO debug prints
pinctrl: abx500: refactor DT parser to take two paths
pinctrl: abx500: use helpers for map allocation/free
pinctrl: alter device tree bindings for functions
pinctrl: nomadik: refactor DT parser to take two paths
pinctrl: nomadik: use utils map free function
pinctrl: nomadik: use util function to reserve maps
pinctrl: qcom: use restart_notifier mechanism for ps_hold
pinctrl: sh-pfc: sh73a0: Remove unnecessary SoC data allocation
pinctrl: berlin: fix the dt_free_map function
pinctrl: at91: disable PD or PU before enabling PU or PD
pinctrl: st: remove gpiochip in failure cases
pinctrl: at91: Fix error handling while doing gpiochio_irqchip_add
pinctrl: at91: Fix failure path in at91_gpio_probe path
pinctrl: lantiq: Release gpiochip resources in fail case
pinctrl: imx: detect uninitialized pins
pinctrl: tegra: Add MIPI pad control
pinctrl: at91: Switch to using managed clk_get
pinctrl: adi2: Remove duplicate gpiochip_remove_pin_ranges
...
* pm-cpufreq:
cpufreq: cpufreq-dt: fix potential double put of cpu OF node
cpufreq: cpu0: rename driver and internals to 'cpufreq_dt'
cpufreq: ppc-corenet: remove duplicate update of cpu_data
cpufreq: Replace strnicmp with strncasecmp
cpufreq: powernv: Set the cpus to nominal frequency during reboot/kexec
cpufreq: powernv: Set the pstate of the last hotplugged out cpu in policy->cpus to minimum
cpufreq: Allow stop CPU callback to be used by all cpufreq drivers
cpufreq: cpu0: Make allocate_resources() work for any CPU
cpufreq: cpu0: try regulators with name "cpu-supply"
cpufreq: cpu0: Move per-cluster initialization code to ->init()
cpufreq: cpu0: use dev_{err|warn|dbg} instead of pr_{err|warn|debug}
cpufreq: cpu0: print relevant error when we defer probe
cpufreq: cpu0: don't validate clock on clk_put()
cpufreq: cpu0: Update Module Author
cpufreq: Add support for per-policy driver data
* pm-cpuidle:
drivers: cpuidle: initialize big.LITTLE driver through DT
drivers: cpuidle: CPU idle ARM64 driver
drivers: cpuidle: implement DT based idle states infrastructure
cpuidle: big.LITTLE: add Exynos5800 compatible string
cpuidle: Replace strnicmp with strncasecmp
arm64: add PSCI CPU_SUSPEND based cpu_suspend support
arm64: kernel: introduce cpu_init_idle CPU operation
arm64: kernel: refactor the CPU suspend API for retention states
Documentation: arm: define DT idle states bindings
This patch removes the non-ascii characters in
Documentation/devicetree/of_selftest.txt
Signed-off-by: Gaurav Minocha <gaurav.minocha.os@gmail.com>
[grant.likely: Fix: s/of_fdt_unflatten_device_tree()/of_fdt_unflatten_tree()/]
Signed-off-by: Grant Likely <grant.likely@linaro.org>
John W. Linville says:
====================
pull request: wireless-next 2014-10-03
Please pull tihs batch of updates intended for the 3.18 stream!
For the iwlwifi bits, Emmanuel says:
"I have here a few things that depend on the latest mac80211's changes:
RRM, TPC, Quiet Period etc... Eyal keeps improving our rate control
and we have a new device ID. This last patch should probably have
gone to wireless.git, but at that stage, I preferred to send it to
-next and CC stable."
For (most of) the Atheros bits, Kalle says:
"The only new feature is testmode support from me. Ben added a new method
to crash the firmware with an assert for debug purposes. As usual, we
have lots of smaller fixes from Michal. Matteo fixed a Kconfig
dependency with debugfs. I fixed some warnings recently added to
checkpatch."
For the NFC bits, Samuel says:
"We've had major updates for TI and ST Microelectronics drivers, and a
few NCI related changes.
For TI's trf7970a driver:
- Target mode support for trf7970a
- Suspend/resume support for trf7970a
- DT properties additions to handle different quirks
- A bunch of fixes for smartphone IOP related issues
For ST Microelectronics' ST21NFCA and ST21NFCB drivers:
- ISO15693 support for st21nfcb
- checkpatch and sparse related warning fixes
- Code cleanups and a few minor fixes
Finally, Marvell added ISO15693 support to the NCI stack, together with a
couple of NCI fixes."
For the Bluetooth bits, Johan says:
"This 3.18 pull request replaces the one I did on Monday ("bluetooth-next
2014-09-22", which hasn't been pulled yet). The additions since the last
request are:
- SCO connection fix for devices not supporting eSCO
- Cleanups regarding the SCO establishment logic
- Remove unnecessary return value from logging functions
- Header compression fix for 6lowpan
- Cleanups to the ieee802154/mrf24j40 driver
Here's a copy from previous request that this one replaces:
'
Here are some more patches for 3.18. They include various fixes to the
btusb HCI driver, a fix for LE SMP, as well as adding Jukka to the
MAINTAINERS file for generic 6LoWPAN (as requested by Alexander Aring).
I've held on to this pull request a bit since we were waiting for a SCO
related fix to get sorted out first. However, since the merge window is
getting closer I decided not to wait for it. If we do get the fix sorted
out there'll probably be a second small pull request later this week.
'"
And,
"Unless 3.17 gets delayed this will probably be our last -next pull request for
3.18. We've got:
- New Marvell hardware supportr
- Multicast support for 6lowpan
- Several of 6lowpan fixes & cleanups
- Fix for a (false-positive) lockdep warning in L2CAP
- Minor btusb cleanup"
On top of all that comes the usual sort of updates to ath5k, ath9k,
ath10k, brcmfmac, mwifiex, and wil6210. This time around there are
also a number of rtlwifi updates to enable some new hardware and
to reconcile the in-kernel drivers with some newer releases of the
Realtek vendor drivers. Also of note is some device tree work for
the bcma bus.
Please let me know if there are problems!
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Introduce support for dynamic device tree resolution.
Using it, it is possible to prepare a device tree that's
been loaded on runtime to be modified and inserted at the kernel
live tree.
Export of of_resolve and bug fix of double free by
Guenter Roeck <groeck@juniper.net>
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
[grant.likely: Don't need to select CONFIG_OF_DYNAMIC and CONFIG_OF_DEVICE]
[grant.likely: Don't need to depend on OF or !SPARC]
[grant.likely: Factor out duplicate code blocks into single function]
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Since commit b21cc2f5fdfe224 ("ASoC: esai: Add VF610+ compatibles support.")
the fsl_esai driver also accepts the "fsl,vf610-esai" compatible string.
Update the documentation accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Freescale updates from Scott (27 commits):
"Highlights include DMA32 zone support (SATA, USB, etc now works on 64-bit
FSL kernels), MSI changes, 8xx optimizations and cleanup, t104x board
support, and PrPMC PCI enumeration."
The naming convention of this driver was always under the scanner, people
complained that it should have a more generic name than cpu0, as it manages all
CPUs that are sharing clock lines.
Also, in future it will be modified to support any number of clusters with
separate clock/voltage lines.
Lets rename it to 'cpufreq_dt' from 'cpufreq_cpu0'.
Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Add I2C bus driver for the controller found in the LSI Axxia family SoCs. The
driver implements 10-bit addressing and SMBus transfer modes via emulation
(including SMBus block data read).
Signed-off-by: Anders Berg <anders.berg@avagotech.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Add an optional mic detect gpio property. If specified in device tree
there will be a mic jack created for the given gpio. This will be
used by the Tegra-based Chromebooks.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The HSI2C module on Exynos7 differs in the transfer status
bits. Transfer status bits were moved to INT_ENABLE and
INT_STATUS registers
This patch adds support for the HSI2C module on Exynos7.
1. Implementes a "hw" field in the variant struct to distinguish
the hardware.
2. Updates the dt-new compatible in dt-binding documenation
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
When both 'cache-size' and 'cache-sets' are specified for a L2 cache
controller node, parse those properties and set up the
set size based on which type of L2 cache controller we are using.
Update the L2 cache controller Device Tree binding with the optional
'cache-size', 'cache-sets', 'cache-block-size' and 'cache-line-size'
properties. These come from the ePAPR specification.
Using the cache size, number of sets and cache line size we can
calculate desired associativity of the L2 cache. This is done
by the calculation:
set size = cache size / sets
ways = set size / line size
way size = cache size / ways = sets * line size
associativity = cache size / way size
Example output from the PB1176 DT that look like this:
L2: l2-cache {
compatible = "arm,l220-cache";
(...)
arm,override-auxreg;
cache-size = <131072>; // 128kB
cache-sets = <512>;
cache-line-size = <32>;
};
Ends up like this:
L2C OF: override cache size: 131072 bytes (128KB)
L2C OF: override line size: 32 bytes
L2C OF: override way size: 16384 bytes (16KB)
L2C OF: override associativity: 8
L2C: DT/platform modifies aux control register: 0x02020fff -> 0x02030fff
L2C-220 cache controller enabled, 8 ways, 128 kB
L2C-220: CACHE_ID 0x41000486, AUX_CTRL 0x06030fff
Which is consistent with the value earlier hardcoded for the
PB1176 platform.
This patch is an extended version based on the initial patch
by Florian Fainelli.
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Conflicts:
drivers/net/usb/r8152.c
net/netfilter/nfnetlink.c
Both r8152 and nfnetlink conflicts were simple overlapping changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
Allow Headphone and Microphone jack detect gpios to be specified in
device tree. This will allow a few systems including rk3288_max98090
to use simple-card instead of having their own board file.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch adds documentation for the devicetree bindings used by the
DT files of Cavium Thunder SoC platforms.
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Signed-off-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Pin configurations can be per-pin or per-group. Make sure that the
per-group case is covered by the bindings.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the AppliedMicro X-Gene SOC PCIe host controller driver. The X-Gene
PCIe controller supports up to 8 lanes and GEN3 speed. The X-Gene SOC
supports up to 5 PCIe ports.
[bhelgaas: folded in MAINTAINERS and bindings updates]
Tested-by: Ming Lei <ming.lei@canonical.com>
Tested-by: Dann Frazier <dann.frazier@canonical.com>
Signed-off-by: Tanmay Inamdar <tinamdar@apm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> (driver)
The Armada SoC family implementation of this SPI hardware module has
extended the configuration register to allow for a wider range of SPI
clock rates. Specifically the Serial Baud Rate Pre-selection bits in the
SPI Interface Configuration Register now also use bits 6 and 7 as well.
Modify the baud rate calculation to handle these differences for the
Armada case. Potentially a baud rate can be setup using a number of
different pre-scalar and scalar combinations. This code tries all
possible pre-scalar divisors (8 in total) to try and find the most
accurate set.
This change introduces (and documents) a new device tree compatible
device name "armada-370-spi" to support this.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add the support for voting of the regulator powering the
host controller logic.
Signed-off-by: Raviv Shvili <rshvili@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Add generic clock initialization support for UFSHCD platform
driver. The clock info is read from device tree using standard
clock bindings. A generic max-clock-frequency-hz property is
defined to save information on maximum operating clock frequency
the h/w supports.
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
UFS devices are powered by at most three external power supplies -
- VCC - The flash memory core power supply, 2.7V to 3.6V or 1.70V to 1.95V
- VCCQ - The controller and I/O power supply, 1.1V to 1.3V
- VCCQ2 - Secondary controller and/or I/O power supply, 1.65V to 1.95V
For some devices VCCQ or VCCQ2 are optional as they can be
generated using internal LDO inside the UFS device.
Add DT bindings for voltage regulators that can be controlled
from host driver.
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
This adds the binding documentation for the Marvell PXA168 Ethernet
controller, following its DT support.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
Document the device-tree binding of Marvell PXA based SoCs.
PXA clocks are mostly fixed rate and fixed ratio clocks derived from an
external oscillator, and gated by a register set (CKEN or CKEN*).
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This will allow us to define GPIO-attached devices (LEDs, buttons) in
the the device tree.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
