From 401a52694ef759630def9c8ca0ce739c290d9d66 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 17 Nov 2014 17:47:00 +0100 Subject: [PATCH 1/9] ARM: STi: DT: STiH416: Add pinctl setup for usb controllers. This patch adds the required pin config for all usb controllers on the stih416. Signed-off-by: Peter Griffin Acked-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index c2025bc37dd5..9cccf2d6aa26 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -147,6 +147,15 @@ }; }; + usb { + pinctrl_usb3: usb3 { + st,pins { + oc-detect = <&pio40 0 ALT1 IN>; + pwr-enable = <&pio40 1 ALT1 OUT>; + }; + }; + }; + sbc_i2c1 { pinctrl_sbc_i2c1_default: sbc_i2c1-default { st,pins { @@ -318,6 +327,16 @@ }; }; + usb { + pinctrl_usb0: usb0 { + st,pins { + oc-detect = <&pio9 4 ALT1 IN>; + pwr-enable = <&pio9 5 ALT1 OUT>; + }; + }; + }; + + i2c1 { pinctrl_i2c1_default: i2c1-default { st,pins { @@ -506,6 +525,21 @@ }; }; }; + + usb { + pinctrl_usb1: usb1 { + st,pins { + oc-detect = <&pio18 0 ALT1 IN>; + pwr-enable = <&pio18 1 ALT1 OUT>; + }; + }; + pinctrl_usb2: usb2 { + st,pins { + oc-detect = <&pio18 2 ALT1 IN>; + pwr-enable = <&pio18 3 ALT1 OUT>; + }; + }; + }; }; pin-controller-fvdp-fe { From 7701677e315924bde68884be643156fcefccacb9 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 17 Nov 2014 17:47:00 +0100 Subject: [PATCH 2/9] ARM: STi: DT: STiH416: Add DT node for the stih415/6 usb2 phy This usb picophy is found on stih415/6 SoC. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 1137bdfcca1c..ff2ad35a5aa2 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -316,5 +316,13 @@ status = "disabled"; }; + + usb2_phy: phy@0 { + compatible = "st,stih416-usb-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_rear>; + clocks = <&clk_sysin>; + clock-names = "osc_phy"; + }; }; }; From 18221b8259a1987a49db41e26a7d60f183ca9f92 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 17 Nov 2014 17:47:00 +0100 Subject: [PATCH 3/9] ARM: STi: DT: STiH416: Add DT nodes for the ehci and ohci usb controllers. This patch adds the DT nodes for the 4 usb ehci and ohci usb controllers on the stih416 SoC. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416.dtsi | 121 +++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index ff2ad35a5aa2..2bdda522c4f0 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -324,5 +324,126 @@ clocks = <&clk_sysin>; clock-names = "osc_phy"; }; + + ehci0: usb@fe1ffe00 { + compatible = "st,st-ehci-300x"; + reg = <0xfe1ffe00 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB0_POWERDOWN>, + <&softreset STIH416_USB0_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ohci0: usb@fe1ffc00 { + compatible = "st,st-ohci-300x"; + reg = <0xfe1ffc00 0x100>; + interrupts = ; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + status = "okay"; + resets = <&powerdown STIH416_USB0_POWERDOWN>, + <&softreset STIH416_USB0_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ehci1: usb@fe203e00 { + compatible = "st,st-ehci-300x"; + reg = <0xfe203e00 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB1_POWERDOWN>, + <&softreset STIH416_USB1_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ohci1: usb@fe203c00 { + compatible = "st,st-ohci-300x"; + reg = <0xfe203c00 0x100>; + interrupts = ; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB1_POWERDOWN>, + <&softreset STIH416_USB1_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ehci2: usb@fe303e00 { + compatible = "st,st-ehci-300x"; + reg = <0xfe303e00 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB2_POWERDOWN>, + <&softreset STIH416_USB2_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ohci2: usb@fe303c00 { + compatible = "st,st-ohci-300x"; + reg = <0xfe303c00 0x100>; + interrupts = ; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB2_POWERDOWN>, + <&softreset STIH416_USB2_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ehci3: usb@fe343e00 { + compatible = "st,st-ehci-300x"; + reg = <0xfe343e00 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB3_POWERDOWN>, + <&softreset STIH416_USB3_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ohci3: usb@fe343c00 { + compatible = "st,st-ohci-300x"; + reg = <0xfe343c00 0x100>; + interrupts = ; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB3_POWERDOWN>, + <&softreset STIH416_USB3_SOFTRESET>; + reset-names = "power", "softreset"; + }; }; }; From cc149f7ae2fa54b3d067527642146dde37977358 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 17 Nov 2014 17:47:00 +0100 Subject: [PATCH 4/9] ARM: STi: DT: STiH410: Add defines for STiH410 DT clocks Although most clock outputs are the same as stih407 SoC, stih410 also has some additional new clock outputs. Signed-off-by: Peter Griffin Acked-by: Lee Jones Signed-off-by: Maxime Coquelin --- include/dt-bindings/clock/stih410-clks.h | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/clock/stih410-clks.h diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h new file mode 100644 index 000000000000..2097a4bbe155 --- /dev/null +++ b/include/dt-bindings/clock/stih410-clks.h @@ -0,0 +1,25 @@ +/* + * This header provides constants clk index STMicroelectronics + * STiH410 SoC. + */ +#ifndef _DT_BINDINGS_CLK_STIH410 +#define _DT_BINDINGS_CLK_STIH410 + +#include "stih407-clks.h" + +/* STiH410 introduces new clock outputs compared to STiH407 */ + +/* CLOCKGEN C0 */ +#define CLK_TX_ICN_HADES 32 +#define CLK_RX_ICN_HADES 33 +#define CLK_ICN_REG_16 34 +#define CLK_PP_HADES 35 +#define CLK_CLUST_HADES 36 +#define CLK_HWPE_HADES 37 +#define CLK_FC_HADES 38 + +/* CLOCKGEN D0 */ +#define CLK_PCMR10_MASTER 4 +#define CLK_USB2_PHY 5 + +#endif From ef893c1a935950610cbae5a0e6d1d62e080413de Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 17 Nov 2014 17:48:00 +0100 Subject: [PATCH 5/9] ARM: STi: DT: STiH410: Add pinctl config for usb controllers. This patch adds the required pin configiguration for the extra usb controllers found on the stih410 device. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih410-pinctrl.dtsi | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 arch/arm/boot/dts/stih410-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/stih410-pinctrl.dtsi new file mode 100644 index 000000000000..b3e9dfc81c07 --- /dev/null +++ b/arch/arm/boot/dts/stih410-pinctrl.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Peter Griffin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "st-pincfg.h" +/ { + + soc { + pin-controller-rear { + + usb0 { + pinctrl_usb0: usb2-0 { + st,pins { + usb-oc-detect = <&pio35 0 ALT1 IN>; + usb-pwr-enable = <&pio35 1 ALT1 OUT>; + }; + }; + }; + + usb1 { + pinctrl_usb1: usb2-1 { + st,pins { + usb-oc-detect = <&pio35 2 ALT1 IN>; + usb-pwr-enable = <&pio35 3 ALT1 OUT>; + }; + }; + }; + }; + }; +}; From 2577451303cb29c82b3d4b1e4a9971f78f9e70e7 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 17 Nov 2014 17:48:00 +0100 Subject: [PATCH 6/9] ARM: STi: DT: STih407: Abstract common dt nodes into shared files. The stih410 soc which will be added in the following commit is very similar to the stih407, to enable maximum re-use of the dt files this commit abstracts the common parts into a shared dt file stihxxx-b2120 for the board, and also a shared file stih407-family.dtsi for the SoC. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-b2120.dts | 53 +---------------- .../dts/{stih407.dtsi => stih407-family.dtsi} | 1 - arch/arm/boot/dts/stihxxx-b2120.dtsi | 59 +++++++++++++++++++ 3 files changed, 62 insertions(+), 51 deletions(-) rename arch/arm/boot/dts/{stih407.dtsi => stih407-family.dtsi} (99%) create mode 100644 arch/arm/boot/dts/stihxxx-b2120.dtsi diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts index fe69f92e5f82..a3ad52b8de1c 100644 --- a/arch/arm/boot/dts/stih407-b2120.dts +++ b/arch/arm/boot/dts/stih407-b2120.dts @@ -7,7 +7,9 @@ * published by the Free Software Foundation. */ /dts-v1/; -#include "stih407.dtsi" +#include "stih407-clock.dtsi" +#include "stih407-family.dtsi" +#include "stihxxx-b2120.dtsi" / { model = "STiH407 B2120"; compatible = "st,stih407-b2120", "st,stih407"; @@ -26,53 +28,4 @@ ttyAS0 = &sbc_serial0; }; - soc { - sbc_serial0: serial@9530000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - red { - #gpio-cells = <2>; - label = "Front Panel LED"; - gpios = <&pio4 1 0>; - linux,default-trigger = "heartbeat"; - }; - green { - #gpio-cells = <2>; - gpios = <&pio1 3 0>; - default-state = "off"; - }; - }; - - i2c@9842000 { - status = "okay"; - }; - - i2c@9843000 { - status = "okay"; - }; - - i2c@9844000 { - status = "okay"; - }; - - i2c@9845000 { - status = "okay"; - }; - - i2c@9540000 { - status = "okay"; - }; - - /* SSC11 to HDMI */ - i2c@9541000 { - status = "okay"; - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - }; }; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407-family.dtsi similarity index 99% rename from arch/arm/boot/dts/stih407.dtsi rename to arch/arm/boot/dts/stih407-family.dtsi index 50637f5168d4..3e31d32133b8 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -6,7 +6,6 @@ * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. */ -#include "stih407-clock.dtsi" #include "stih407-pinctrl.dtsi" #include / { diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi new file mode 100644 index 000000000000..0074bd49797c --- /dev/null +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014 STMicroelectronics (R&D) Limited. + * Author: Giuseppe Cavallaro + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/ { + soc { + sbc_serial0: serial@9530000 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + red { + #gpio-cells = <2>; + label = "Front Panel LED"; + gpios = <&pio4 1 0>; + linux,default-trigger = "heartbeat"; + }; + green { + #gpio-cells = <2>; + gpios = <&pio1 3 0>; + default-state = "off"; + }; + }; + + i2c@9842000 { + status = "okay"; + }; + + i2c@9843000 { + status = "okay"; + }; + + i2c@9844000 { + status = "okay"; + }; + + i2c@9845000 { + status = "okay"; + }; + + i2c@9540000 { + status = "okay"; + }; + + /* SSC11 to HDMI */ + i2c@9541000 { + status = "okay"; + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + }; + }; +}; From b16b77a5c1fdfbb135352b5cb6a5c77af2605535 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 17 Nov 2014 17:48:00 +0100 Subject: [PATCH 7/9] ARM: STi: DT: STiH410: Add STiH410 SoC and b2120 board support. The STiH410 is an advanced multi-HD AVC processor with 3D graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU part of the stih407 family. It has wide connectivity including USB 3.0, PCI-e, SATA and gigabit ethernet. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stih410-b2120.dts | 29 +++ arch/arm/boot/dts/stih410-clock.dtsi | 338 +++++++++++++++++++++++++++ arch/arm/boot/dts/stih410.dtsi | 14 ++ 4 files changed, 382 insertions(+) create mode 100644 arch/arm/boot/dts/stih410-b2120.dts create mode 100644 arch/arm/boot/dts/stih410-clock.dtsi create mode 100644 arch/arm/boot/dts/stih410.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 38c89cafa1ab..04cf4a4472d8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -409,6 +409,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ spear320-hmi.dtb dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ + stih410-b2120.dtb \ stih415-b2000.dtb \ stih415-b2020.dtb \ stih416-b2000.dtb \ diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts new file mode 100644 index 000000000000..972c17ad8313 --- /dev/null +++ b/arch/arm/boot/dts/stih410-b2120.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 STMicroelectronics (R&D) Limited. + * Author: Peter Griffin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; +#include "stih410.dtsi" +#include "stihxxx-b2120.dtsi" +/ { + model = "STiH410 B2120"; + compatible = "st,stih410-b2120", "st,stih410"; + + chosen { + bootargs = "console=ttyAS0,115200"; + linux,stdout-path = &sbc_serial0; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + aliases { + ttyAS0 = &sbc_serial0; + }; +}; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi new file mode 100644 index 000000000000..6b5803a30096 --- /dev/null +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -0,0 +1,338 @@ +/* + * Copyright (C) 2014 STMicroelectronics R&D Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +/ { + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + compatible = "st,stih410-clk", "simple-bus"; + + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + clock-output-names = "CLK_SYSIN"; + }; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* + * A9 PLL. + */ + clockgen-a9@92b0000 { + compatible = "st,clkgen-c32"; + reg = <0x92b0000 0xffff>; + + clockgen_a9_pll: clockgen-a9-pll { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clockgen-a9-pll-odf"; + }; + }; + + /* + * ARM CPU related clocks. + */ + clk_m_a9: clk-m-a9@92b0000 { + #clock-cells = <0>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + reg = <0x92b0000 0x10000>; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + }; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; + + /* + * Bootloader initialized system infrastructure clock for + * serial devices. + */ + clk_ext2f_a9: clockgen-c0@13 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + clock-output-names = "clk-s-icn-reg-0"; + }; + + clockgen-a@090ff000 { + compatible = "st,clkgen-c32"; + reg = <0x90ff000 0x1000>; + + clk_s_a0_pll: clk-s-a0-pll { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a0-pll-ofd-0"; + }; + + clk_s_a0_flexgen: clk-s-a0-flexgen { + compatible = "st,flexgen"; + + #clock-cells = <1>; + + clocks = <&clk_s_a0_pll 0>, + <&clk_sysin>; + + clock-output-names = "clk-ic-lmi0", + "clk-ic-lmi1"; + }; + }; + + clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-C", "st,quadfs"; + reg = <0x9103000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-fs0-ch0", + "clk-s-c0-fs0-ch1", + "clk-s-c0-fs0-ch2", + "clk-s-c0-fs0-ch3"; + }; + + clk_s_c0: clockgen-c@09103000 { + compatible = "st,clkgen-c32"; + reg = <0x9103000 0x1000>; + + clk_s_c0_pll0: clk-s-c0-pll0 { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-pll0-odf-0"; + }; + + clk_s_c0_pll1: clk-s-c0-pll1 { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-pll1-odf-0"; + }; + + clk_s_c0_flexgen: clk-s-c0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_c0_pll0 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_quadfs 0>, + <&clk_s_c0_quadfs 1>, + <&clk_s_c0_quadfs 2>, + <&clk_s_c0_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-icn-gpu", + "clk-fdma", + "clk-nand", + "clk-hva", + "clk-proc-stfe", + "clk-proc-tp", + "clk-rx-icn-dmu", + "clk-rx-icn-hva", + "clk-icn-cpu", + "clk-tx-icn-dmu", + "clk-mmc-0", + "clk-mmc-1", + "clk-jpegdec", + "clk-ext2fa9", + "clk-ic-bdisp-0", + "clk-ic-bdisp-1", + "clk-pp-dmu", + "clk-vid-dmu", + "clk-dss-lpc", + "clk-st231-aud-0", + "clk-st231-gp-1", + "clk-st231-dmu", + "clk-icn-lmi", + "clk-tx-icn-disp-1", + "clk-icn-sbc", + "clk-stfe-frc2", + "clk-eth-phy", + "clk-eth-ref-phyclk", + "clk-flash-promip", + "clk-main-disp", + "clk-aux-disp", + "clk-compo-dvp", + "clk-tx-icn-hades", + "clk-rx-icn-hades", + "clk-icn-reg-16", + "clk-pp-hades", + "clk-clust-hades", + "clk-hwpe-hades", + "clk-fc-hades"; + }; + }; + + clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9104000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d0-fs0-ch0", + "clk-s-d0-fs0-ch1", + "clk-s-d0-fs0-ch2", + "clk-s-d0-fs0-ch3"; + }; + + clockgen-d0@09104000 { + compatible = "st,clkgen-c32"; + reg = <0x9104000 0x1000>; + + clk_s_d0_flexgen: clk-s-d0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d0_quadfs 0>, + <&clk_s_d0_quadfs 1>, + <&clk_s_d0_quadfs 2>, + <&clk_s_d0_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-pcm-0", + "clk-pcm-1", + "clk-pcm-2", + "clk-spdiff", + "clk-pcmr10-master", + "clk-usb2-phy"; + }; + }; + + clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9106000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d2-fs0-ch0", + "clk-s-d2-fs0-ch1", + "clk-s-d2-fs0-ch2", + "clk-s-d2-fs0-ch3"; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clockgen-d2@x9106000 { + compatible = "st,clkgen-c32"; + reg = <0x9106000 0x1000>; + + clk_s_d2_flexgen: clk-s-d2-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 2>, + <&clk_s_d2_quadfs 3>, + <&clk_sysin>, + <&clk_sysin>, + <&clk_tmdsout_hdmi>; + + clock-output-names = "clk-pix-main-disp", + "clk-pix-pip", + "clk-pix-gdp1", + "clk-pix-gdp2", + "clk-pix-gdp3", + "clk-pix-gdp4", + "clk-pix-aux-disp", + "clk-denc", + "clk-pix-hddac", + "clk-hddac", + "clk-sddac", + "clk-pix-dvo", + "clk-dvo", + "clk-pix-hdmi", + "clk-tmds-hdmi", + "clk-ref-hdmiphy"; + }; + }; + + clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9107000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d3-fs0-ch0", + "clk-s-d3-fs0-ch1", + "clk-s-d3-fs0-ch2", + "clk-s-d3-fs0-ch3"; + }; + + clockgen-d3@9107000 { + compatible = "st,clkgen-c32"; + reg = <0x9107000 0x1000>; + + clk_s_d3_flexgen: clk-s-d3-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d3_quadfs 0>, + <&clk_s_d3_quadfs 1>, + <&clk_s_d3_quadfs 2>, + <&clk_s_d3_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-stfe-frc1", + "clk-tsout-0", + "clk-tsout-1", + "clk-mchi", + "clk-vsens-compo", + "clk-frc1-remote", + "clk-lpc-0", + "clk-lpc-1"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi new file mode 100644 index 000000000000..c05627eb717d --- /dev/null +++ b/arch/arm/boot/dts/stih410.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Peter Griffin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "stih410-clock.dtsi" +#include "stih407-family.dtsi" +#include "stih410-pinctrl.dtsi" +/ { + +}; From f6b1e68a29ca5471d0f89dce019040e5b021470f Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 17 Nov 2014 17:48:00 +0100 Subject: [PATCH 8/9] ARM: STi: DT: STih407: STih410: Add clk_ignore_unused to kernel bootargs At the moment we don't take a reference on some core interconnect clocks which means when CCF turns off unused clocks the SoC will hang. As a temp soltuion we will boot with clk_ignore_unused parameter for all b2120 boards. Signed-off-by: Peter Griffin Acked-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-b2120.dts | 2 +- arch/arm/boot/dts/stih410-b2120.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts index a3ad52b8de1c..261d5e2c48d2 100644 --- a/arch/arm/boot/dts/stih407-b2120.dts +++ b/arch/arm/boot/dts/stih407-b2120.dts @@ -15,7 +15,7 @@ compatible = "st,stih407-b2120", "st,stih407"; chosen { - bootargs = "console=ttyAS0,115200"; + bootargs = "console=ttyAS0,115200 clk_ignore_unused"; linux,stdout-path = &sbc_serial0; }; diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts index 972c17ad8313..2f61a9960dee 100644 --- a/arch/arm/boot/dts/stih410-b2120.dts +++ b/arch/arm/boot/dts/stih410-b2120.dts @@ -14,7 +14,7 @@ compatible = "st,stih410-b2120", "st,stih410"; chosen { - bootargs = "console=ttyAS0,115200"; + bootargs = "console=ttyAS0,115200 clk_ignore_unused"; linux,stdout-path = &sbc_serial0; }; From 3ece2c2be34f2fe6254b49dffa5815e2fc7f1b71 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 17 Nov 2014 17:48:00 +0100 Subject: [PATCH 9/9] ARM: STi: DT: STiH416: Change miphy356 node name to phy@fe382000 Following Arnds review comments, update the miphy365 to follow the common convention of naming the phy node names as phy@addr. Signed-off-by: Peter Griffin Suggested-by: Arnd Bergmann Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416-b2020.dts | 2 +- arch/arm/boot/dts/stih416-b2020e.dts | 2 +- arch/arm/boot/dts/stih416.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts index 5d1543babf56..200a81844765 100644 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ b/arch/arm/boot/dts/stih416-b2020.dts @@ -20,7 +20,7 @@ non-removable; }; - miphy365x_phy: miphy365x@fe382000 { + miphy365x_phy: phy@fe382000 { phy_port0: port@fe382000 { st,sata-gen = <3>; }; diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts index 956fab8b8ffe..961799e1dc51 100644 --- a/arch/arm/boot/dts/stih416-b2020e.dts +++ b/arch/arm/boot/dts/stih416-b2020e.dts @@ -38,7 +38,7 @@ non-removable; }; - miphy365x_phy: miphy365x@fe382000 { + miphy365x_phy: phy@fe382000 { phy_port0: port@fe382000 { st,sata-gen = <3>; }; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 2bdda522c4f0..fad9073ddeed 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -281,7 +281,7 @@ clocks = <&clk_s_a1_ls 8>; }; - miphy365x_phy: miphy365x@fe382000 { + miphy365x_phy: phy@fe382000 { compatible = "st,miphy365x-phy"; st,syscfg = <&syscfg_rear>; #address-cells = <1>;