a7y18lte-ubports/android_kernel_samsung_universal7885
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gpio/crystalcove: Add additional GPIO for Panel control

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Export PANEL_EN/DISABLE (offset 0x52) as additional GPIO. Needed
by display driver to enable the DSI panel on BYT platform where
the Panel EN/Disable control is routed thorugh CRC PMIC

CC: Samuel Ortiz <sameo@linux.intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Shobhit Kumar 2015-03-12 22:01:26 +05:30 committed by Linus Walleij
parent a4dd4ddd4b
commit e189ca56d9
1 changed files with 6 additions and 1 deletions

7
drivers/gpio/gpio-crystalcove.c
View File

@ -24,7 +24,7 @@
#include <linux/mfd/intel_soc_pmic.h> #include <linux/mfd/intel_soc_pmic.h>
#define CRYSTALCOVE_GPIO_NUM 16 #define CRYSTALCOVE_GPIO_NUM 16
#define CRYSTALCOVE_VGPIO_NUM 94 #define CRYSTALCOVE_VGPIO_NUM 95
#define UPDATE_IRQ_TYPE BIT(0) #define UPDATE_IRQ_TYPE BIT(0)
#define UPDATE_IRQ_MASK BIT(1) #define UPDATE_IRQ_MASK BIT(1)
@ -39,6 +39,7 @@
#define GPIO0P0CTLI 0x33 #define GPIO0P0CTLI 0x33
#define GPIO1P0CTLO 0x3b #define GPIO1P0CTLO 0x3b
#define GPIO1P0CTLI 0x43 #define GPIO1P0CTLI 0x43
#define GPIOPANELCTL 0x52
#define CTLI_INTCNT_DIS (0) #define CTLI_INTCNT_DIS (0)
#define CTLI_INTCNT_NE (1 << 1) #define CTLI_INTCNT_NE (1 << 1)
@ -93,6 +94,10 @@ static inline int to_reg(int gpio, enum ctrl_register reg_type)
{ {
int reg; int reg;
if (gpio == 94) {
return GPIOPANELCTL;
}
if (reg_type == CTRL_IN) { if (reg_type == CTRL_IN) {
if (gpio < 8) if (gpio < 8)
reg = GPIO0P0CTLI; reg = GPIO0P0CTLI;