sh: intc - remove redundant irq code for sh03, snapgear and titan
This patch removes redundant board specific interrupt code for boards using sh775x processors and 4 IRQ lines in "Individual Interrupt Mode" aka IRLM. Three boards are affected: sh03, snapgear and titan. The right way to do this is to use cpu specific code provided by intc. A nice side effect is that sh03 now compiles, board not BROKEN any more. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -308,7 +308,7 @@ config SH_MPC1211
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config SH_SH03
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config SH_SH03
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bool "Interface CTP/PCI-SH03"
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bool "Interface CTP/PCI-SH03"
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depends on CPU_SUBTYPE_SH7751 && BROKEN
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depends on CPU_SUBTYPE_SH7751
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select CPU_HAS_IPR_IRQ
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select CPU_HAS_IPR_IRQ
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select SYS_SUPPORTS_PCI
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select SYS_SUPPORTS_PCI
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help
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help
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@ -15,33 +15,9 @@
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#include <asm/sh03/sh03.h>
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#include <asm/sh03/sh03.h>
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#include <asm/addrspace.h>
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#include <asm/addrspace.h>
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static struct ipr_data ipr_irq_table[] = {
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{ IRL0_IRQ, 0, IRL0_IPR_POS, IRL0_PRIORITY },
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{ IRL1_IRQ, 0, IRL1_IPR_POS, IRL1_PRIORITY },
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{ IRL2_IRQ, 0, IRL2_IPR_POS, IRL2_PRIORITY },
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{ IRL3_IRQ, 0, IRL3_IPR_POS, IRL3_PRIORITY },
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};
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static unsigned long ipr_offsets[] = {
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INTC_IPRD,
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};
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static struct ipr_desc ipr_irq_desc = {
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.ipr_offsets = ipr_offsets,
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.nr_offsets = ARRAY_SIZE(ipr_offsets),
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.ipr_data = ipr_irq_table,
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.nr_irqs = ARRAY_SIZE(ipr_irq_table),
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.chip = {
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.name = "IPR-sh03",
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},
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};
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static void __init init_sh03_IRQ(void)
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static void __init init_sh03_IRQ(void)
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{
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{
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ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
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plat_irq_setup_pins(IRQ_MODE_IRQ);
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register_ipr_controller(&ipr_irq_desc);
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}
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}
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extern void *cf_io_base;
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extern void *cf_io_base;
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@ -68,37 +68,11 @@ module_init(eraseconfig_init);
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* IRL3 = crypto
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* IRL3 = crypto
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*/
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*/
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static struct ipr_data ipr_irq_table[] = {
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{ IRL0_IRQ, 0, IRL0_IPR_POS, IRL0_PRIORITY },
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{ IRL1_IRQ, 0, IRL1_IPR_POS, IRL1_PRIORITY },
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{ IRL2_IRQ, 0, IRL2_IPR_POS, IRL2_PRIORITY },
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{ IRL3_IRQ, 0, IRL3_IPR_POS, IRL3_PRIORITY },
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};
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static unsigned long ipr_offsets[] = {
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INTC_IPRD,
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};
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static struct ipr_desc ipr_irq_desc = {
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.ipr_offsets = ipr_offsets,
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.nr_offsets = ARRAY_SIZE(ipr_offsets),
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.ipr_data = ipr_irq_table,
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.nr_irqs = ARRAY_SIZE(ipr_irq_table),
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.chip = {
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.name = "IPR-snapgear",
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},
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};
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static void __init init_snapgear_IRQ(void)
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static void __init init_snapgear_IRQ(void)
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{
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{
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/* enable individual interrupt mode for externals */
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ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
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printk("Setup SnapGear IRQ/IPR ...\n");
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printk("Setup SnapGear IRQ/IPR ...\n");
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/* enable individual interrupt mode for externals */
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register_ipr_controller(&ipr_irq_desc);
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plat_irq_setup_pins(IRQ_MODE_IRQ);
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}
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}
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/*
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/*
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@ -12,38 +12,10 @@
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#include <asm/titan.h>
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#include <asm/titan.h>
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#include <asm/io.h>
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#include <asm/io.h>
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static struct ipr_data ipr_irq_table[] = {
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/* IRQ, IPR idx, shift, prio */
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{ TITAN_IRQ_WAN, 3, 12, 8 }, /* eth0 (WAN) */
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{ TITAN_IRQ_LAN, 3, 8, 8 }, /* eth1 (LAN) */
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{ TITAN_IRQ_MPCIA, 3, 4, 8 }, /* mPCI A (top) */
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{ TITAN_IRQ_USB, 3, 0, 8 }, /* mPCI B (bottom), USB */
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};
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static unsigned long ipr_offsets[] = { /* stolen from setup-sh7750.c */
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0xffd00004UL, /* 0: IPRA */
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0xffd00008UL, /* 1: IPRB */
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0xffd0000cUL, /* 2: IPRC */
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0xffd00010UL, /* 3: IPRD */
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};
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static struct ipr_desc ipr_irq_desc = {
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.ipr_offsets = ipr_offsets,
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.nr_offsets = ARRAY_SIZE(ipr_offsets),
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.ipr_data = ipr_irq_table,
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.nr_irqs = ARRAY_SIZE(ipr_irq_table),
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.chip = {
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.name = "IPR-titan",
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},
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};
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static void __init init_titan_irq(void)
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static void __init init_titan_irq(void)
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{
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{
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/* enable individual interrupt mode for externals */
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/* enable individual interrupt mode for externals */
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ipr_irq_enable_irlm();
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plat_irq_setup_pins(IRQ_MODE_IRQ);
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/* register ipr irqs */
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register_ipr_controller(&ipr_irq_desc);
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}
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}
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static struct sh_machine_vector mv_titan __initmv = {
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static struct sh_machine_vector mv_titan __initmv = {
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@ -282,13 +282,19 @@ void __init plat_irq_setup(void)
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#define INTC_ICR 0xffd00000UL
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#define INTC_ICR 0xffd00000UL
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#define INTC_ICR_IRLM (1<<7)
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#define INTC_ICR_IRLM (1<<7)
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/* enable individual interrupt mode for external interupts */
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void __init plat_irq_setup_pins(int mode)
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void __init ipr_irq_enable_irlm(void)
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{
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{
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#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
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#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
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BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
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BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
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return;
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#endif
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#endif
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register_intc_controller(&intc_desc_irlm);
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switch (mode) {
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case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
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ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
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ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
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register_intc_controller(&intc_desc_irlm);
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break;
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default:
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BUG();
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}
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}
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}
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@ -41,11 +41,6 @@ struct ipr_desc {
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void register_ipr_controller(struct ipr_desc *);
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void register_ipr_controller(struct ipr_desc *);
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/*
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* Enable individual interrupt mode for external IPR IRQs.
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*/
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void __init ipr_irq_enable_irlm(void);
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typedef unsigned char intc_enum;
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typedef unsigned char intc_enum;
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struct intc_vect {
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struct intc_vect {
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@ -11,22 +11,13 @@
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#include <linux/time.h>
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#include <linux/time.h>
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#define INTC_IPRD 0xffd00010UL
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#define IRL0_IRQ 2
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#define IRL0_IRQ 2
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#define IRL0_IPR_POS 3
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#define IRL0_PRIORITY 13
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#define IRL0_PRIORITY 13
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#define IRL1_IRQ 5
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#define IRL1_IRQ 5
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#define IRL1_IPR_POS 2
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#define IRL1_PRIORITY 10
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#define IRL1_PRIORITY 10
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#define IRL2_IRQ 8
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#define IRL2_IRQ 8
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#define IRL2_IPR_POS 1
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#define IRL2_PRIORITY 7
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#define IRL2_PRIORITY 7
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#define IRL3_IRQ 11
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#define IRL3_IRQ 11
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#define IRL3_IPR_POS 0
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#define IRL3_PRIORITY 4
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#define IRL3_PRIORITY 4
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void heartbeat_sh03(void);
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void heartbeat_sh03(void);
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@ -20,19 +20,15 @@
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*/
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*/
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#define IRL0_IRQ 2
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#define IRL0_IRQ 2
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#define IRL0_IPR_POS 3
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#define IRL0_PRIORITY 13
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#define IRL0_PRIORITY 13
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#define IRL1_IRQ 5
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#define IRL1_IRQ 5
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#define IRL1_IPR_POS 2
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#define IRL1_PRIORITY 10
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#define IRL1_PRIORITY 10
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#define IRL2_IRQ 8
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#define IRL2_IRQ 8
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#define IRL2_IPR_POS 1
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#define IRL2_PRIORITY 7
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#define IRL2_PRIORITY 7
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#define IRL3_IRQ 11
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#define IRL3_IRQ 11
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#define IRL3_IPR_POS 0
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#define IRL3_PRIORITY 4
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#define IRL3_PRIORITY 4
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#endif
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#endif
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