Merge branch 'parisc-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parisc fixes from Helge Deller: "This contains a kernel segfault fix when reading /proc/kpageflags or /proc/kpagecount, two fixes for the serial port and PCI graphic card support on C8000 workstations and a fix to use unshadowed registers for flushing D- and I-caches." * 'parisc-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: Use unshadowed index register for flush instructions in flush_dcache_page_asm and flush_icache_page_asm parisc: provide pci_mmap_page_range() for parisc parisc: fix serial ports on C8000 workstation parisc: fix kernel BUG at arch/parisc/include/asm/mmzone.h:50 (part 2)
This commit is contained in:
commit
aa4927b9ed
@ -27,7 +27,7 @@ extern struct node_map_data node_data[];
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#define PFNNID_SHIFT (30 - PAGE_SHIFT)
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#define PFNNID_SHIFT (30 - PAGE_SHIFT)
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#define PFNNID_MAP_MAX 512 /* support 512GB */
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#define PFNNID_MAP_MAX 512 /* support 512GB */
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extern unsigned char pfnnid_map[PFNNID_MAP_MAX];
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extern signed char pfnnid_map[PFNNID_MAP_MAX];
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#ifndef CONFIG_64BIT
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#ifndef CONFIG_64BIT
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#define pfn_is_io(pfn) ((pfn & (0xf0000000UL >> PAGE_SHIFT)) == (0xf0000000UL >> PAGE_SHIFT))
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#define pfn_is_io(pfn) ((pfn & (0xf0000000UL >> PAGE_SHIFT)) == (0xf0000000UL >> PAGE_SHIFT))
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@ -46,7 +46,7 @@ static inline int pfn_to_nid(unsigned long pfn)
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i = pfn >> PFNNID_SHIFT;
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i = pfn >> PFNNID_SHIFT;
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BUG_ON(i >= ARRAY_SIZE(pfnnid_map));
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BUG_ON(i >= ARRAY_SIZE(pfnnid_map));
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return (int)pfnnid_map[i];
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return pfnnid_map[i];
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}
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}
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static inline int pfn_valid(int pfn)
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static inline int pfn_valid(int pfn)
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@ -225,4 +225,9 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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return channel ? 15 : 14;
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return channel ? 15 : 14;
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}
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}
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#define HAVE_PCI_MMAP
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extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine);
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#endif /* __ASM_PARISC_PCI_H */
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#endif /* __ASM_PARISC_PCI_H */
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@ -1205,6 +1205,7 @@ static struct hp_hardware hp_hardware_list[] = {
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{HPHW_FIO, 0x004, 0x00320, 0x0, "Metheus Frame Buffer"},
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{HPHW_FIO, 0x004, 0x00320, 0x0, "Metheus Frame Buffer"},
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{HPHW_FIO, 0x004, 0x00340, 0x0, "BARCO CX4500 VME Grphx Cnsl"},
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{HPHW_FIO, 0x004, 0x00340, 0x0, "BARCO CX4500 VME Grphx Cnsl"},
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{HPHW_FIO, 0x004, 0x00360, 0x0, "Hughes TOG VME FDDI"},
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{HPHW_FIO, 0x004, 0x00360, 0x0, "Hughes TOG VME FDDI"},
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{HPHW_FIO, 0x076, 0x000AD, 0x00, "Crestone Peak RS-232"},
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{HPHW_IOA, 0x185, 0x0000B, 0x00, "Java BC Summit Port"},
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{HPHW_IOA, 0x185, 0x0000B, 0x00, "Java BC Summit Port"},
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{HPHW_IOA, 0x1FF, 0x0000B, 0x00, "Hitachi Ghostview Summit Port"},
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{HPHW_IOA, 0x1FF, 0x0000B, 0x00, "Hitachi Ghostview Summit Port"},
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{HPHW_IOA, 0x580, 0x0000B, 0x10, "U2-IOA BC Runway Port"},
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{HPHW_IOA, 0x580, 0x0000B, 0x10, "U2-IOA BC Runway Port"},
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@ -860,7 +860,7 @@ ENTRY(flush_dcache_page_asm)
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#endif
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#endif
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ldil L%dcache_stride, %r1
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ldil L%dcache_stride, %r1
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ldw R%dcache_stride(%r1), %r1
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ldw R%dcache_stride(%r1), r31
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_64BIT
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depdi,z 1, 63-PAGE_SHIFT,1, %r25
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depdi,z 1, 63-PAGE_SHIFT,1, %r25
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@ -868,26 +868,26 @@ ENTRY(flush_dcache_page_asm)
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depwi,z 1, 31-PAGE_SHIFT,1, %r25
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depwi,z 1, 31-PAGE_SHIFT,1, %r25
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#endif
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#endif
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add %r28, %r25, %r25
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add %r28, %r25, %r25
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sub %r25, %r1, %r25
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sub %r25, r31, %r25
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1: fdc,m %r1(%r28)
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1: fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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cmpb,COND(<<) %r28, %r25,1b
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cmpb,COND(<<) %r28, %r25,1b
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fdc,m %r1(%r28)
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fdc,m r31(%r28)
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sync
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sync
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@ -936,7 +936,7 @@ ENTRY(flush_icache_page_asm)
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#endif
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#endif
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ldil L%icache_stride, %r1
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ldil L%icache_stride, %r1
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ldw R%icache_stride(%r1), %r1
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ldw R%icache_stride(%r1), %r31
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_64BIT
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depdi,z 1, 63-PAGE_SHIFT,1, %r25
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depdi,z 1, 63-PAGE_SHIFT,1, %r25
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@ -944,28 +944,28 @@ ENTRY(flush_icache_page_asm)
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depwi,z 1, 31-PAGE_SHIFT,1, %r25
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depwi,z 1, 31-PAGE_SHIFT,1, %r25
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#endif
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#endif
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add %r28, %r25, %r25
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add %r28, %r25, %r25
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sub %r25, %r1, %r25
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sub %r25, %r31, %r25
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/* fic only has the type 26 form on PA1.1, requiring an
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/* fic only has the type 26 form on PA1.1, requiring an
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* explicit space specification, so use %sr4 */
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* explicit space specification, so use %sr4 */
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1: fic,m %r1(%sr4,%r28)
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1: fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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cmpb,COND(<<) %r28, %r25,1b
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cmpb,COND(<<) %r28, %r25,1b
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fic,m %r1(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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sync
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sync
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@ -220,6 +220,33 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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}
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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unsigned long prot;
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/*
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* I/O space can be accessed via normal processor loads and stores on
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* this platform but for now we elect not to do this and portable
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* drivers should not do this anyway.
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*/
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if (mmap_state == pci_mmap_io)
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return -EINVAL;
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if (write_combine)
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return -EINVAL;
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/*
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* Ignore write-combine; for now only return uncached mappings.
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*/
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prot = pgprot_val(vma->vm_page_prot);
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prot |= _PAGE_NO_CACHE;
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vma->vm_page_prot = __pgprot(prot);
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return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start, vma->vm_page_prot);
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}
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/*
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/*
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* A driver is enabling the device. We make sure that all the appropriate
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* A driver is enabling the device. We make sure that all the appropriate
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* bits are set to allow the device to operate as the driver is expecting.
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* bits are set to allow the device to operate as the driver is expecting.
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@ -47,7 +47,7 @@ pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((__section__ (".data..vm0.pt
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#ifdef CONFIG_DISCONTIGMEM
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#ifdef CONFIG_DISCONTIGMEM
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struct node_map_data node_data[MAX_NUMNODES] __read_mostly;
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struct node_map_data node_data[MAX_NUMNODES] __read_mostly;
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unsigned char pfnnid_map[PFNNID_MAP_MAX] __read_mostly;
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signed char pfnnid_map[PFNNID_MAP_MAX] __read_mostly;
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#endif
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#endif
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static struct resource data_resource = {
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static struct resource data_resource = {
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@ -811,6 +811,70 @@ int iosapic_fixup_irq(void *isi_obj, struct pci_dev *pcidev)
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return pcidev->irq;
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return pcidev->irq;
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}
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}
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static struct iosapic_info *first_isi = NULL;
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#ifdef CONFIG_64BIT
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int iosapic_serial_irq(int num)
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{
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struct iosapic_info *isi = first_isi;
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struct irt_entry *irte = NULL; /* only used if PAT PDC */
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struct vector_info *vi;
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int isi_line; /* line used by device */
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/* lookup IRT entry for isi/slot/pin set */
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irte = &irt_cell[num];
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DBG_IRT("iosapic_serial_irq(): irte %p %x %x %x %x %x %x %x %x\n",
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irte,
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irte->entry_type,
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irte->entry_length,
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irte->polarity_trigger,
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irte->src_bus_irq_devno,
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irte->src_bus_id,
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irte->src_seg_id,
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irte->dest_iosapic_intin,
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(u32) irte->dest_iosapic_addr);
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isi_line = irte->dest_iosapic_intin;
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/* get vector info for this input line */
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vi = isi->isi_vector + isi_line;
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DBG_IRT("iosapic_serial_irq: line %d vi 0x%p\n", isi_line, vi);
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/* If this IRQ line has already been setup, skip it */
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if (vi->irte)
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goto out;
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vi->irte = irte;
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/*
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* Allocate processor IRQ
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*
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* XXX/FIXME The txn_alloc_irq() code and related code should be
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* moved to enable_irq(). That way we only allocate processor IRQ
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* bits for devices that actually have drivers claiming them.
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* Right now we assign an IRQ to every PCI device present,
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* regardless of whether it's used or not.
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*/
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vi->txn_irq = txn_alloc_irq(8);
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if (vi->txn_irq < 0)
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panic("I/O sapic: couldn't get TXN IRQ\n");
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/* enable_irq() will use txn_* to program IRdT */
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vi->txn_addr = txn_alloc_addr(vi->txn_irq);
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vi->txn_data = txn_alloc_data(vi->txn_irq);
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vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
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vi->eoi_data = cpu_to_le32(vi->txn_data);
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cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
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out:
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return vi->txn_irq;
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}
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#endif
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/*
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/*
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** squirrel away the I/O Sapic Version
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** squirrel away the I/O Sapic Version
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@ -877,6 +941,8 @@ void *iosapic_register(unsigned long hpa)
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vip->irqline = (unsigned char) cnt;
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vip->irqline = (unsigned char) cnt;
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vip->iosapic = isi;
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vip->iosapic = isi;
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}
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}
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if (!first_isi)
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first_isi = isi;
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return isi;
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return isi;
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}
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}
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@ -30,6 +30,12 @@ static int __init serial_init_chip(struct parisc_device *dev)
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unsigned long address;
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unsigned long address;
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int err;
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int err;
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#ifdef CONFIG_64BIT
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extern int iosapic_serial_irq(int cellnum);
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if (!dev->irq && (dev->id.sversion == 0xad))
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dev->irq = iosapic_serial_irq(dev->mod_index-1);
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#endif
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if (!dev->irq) {
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if (!dev->irq) {
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/* We find some unattached serial ports by walking native
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/* We find some unattached serial ports by walking native
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* busses. These should be silently ignored. Otherwise,
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* busses. These should be silently ignored. Otherwise,
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@ -51,7 +57,8 @@ static int __init serial_init_chip(struct parisc_device *dev)
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memset(&uart, 0, sizeof(uart));
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memset(&uart, 0, sizeof(uart));
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uart.port.iotype = UPIO_MEM;
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uart.port.iotype = UPIO_MEM;
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/* 7.272727MHz on Lasi. Assumed the same for Dino, Wax and Timi. */
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/* 7.272727MHz on Lasi. Assumed the same for Dino, Wax and Timi. */
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uart.port.uartclk = 7272727;
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uart.port.uartclk = (dev->id.sversion != 0xad) ?
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7272727 : 1843200;
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uart.port.mapbase = address;
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uart.port.mapbase = address;
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uart.port.membase = ioremap_nocache(address, 16);
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uart.port.membase = ioremap_nocache(address, 16);
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uart.port.irq = dev->irq;
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uart.port.irq = dev->irq;
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@ -73,6 +80,7 @@ static struct parisc_device_id serial_tbl[] = {
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{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00075 },
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{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00075 },
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{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008c },
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{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008c },
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{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008d },
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{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008d },
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{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x000ad },
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{ 0 }
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{ 0 }
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};
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};
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