a7y18lte-ubports/android_kernel_samsung_universal7885
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Merge branch 'cleanups/assorted' into imx-fixes-for-arnd

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Conflicts:
	arch/arm/mach-imx/mm-imx3.c

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2011-11-22 11:32:39 +01:00
commit 9a2ee7152c
7 changed files with 36 additions and 51 deletions
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7
arch/arm/mach-imx/mm-imx3.c
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@ -33,6 +33,8 @@
static void imx3_idle(void) static void imx3_idle(void)
{ {
unsigned long reg = 0; unsigned long reg = 0;
if (!need_resched())
__asm__ __volatile__( __asm__ __volatile__(
/* disable I and D cache */ /* disable I and D cache */
"mrc p15, 0, %0, c1, c0, 0\n" "mrc p15, 0, %0, c1, c0, 0\n"
@ -56,6 +58,7 @@ static void imx3_idle(void)
"orr %0, %0, #0x00000004\n" "orr %0, %0, #0x00000004\n"
"mcr p15, 0, %0, c1, c0, 0\n" "mcr p15, 0, %0, c1, c0, 0\n"
: "=r" (reg)); : "=r" (reg));
local_irq_enable();
} }
static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size, static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@ -131,7 +134,7 @@ void __init imx31_init_early(void)
{ {
mxc_set_cpu_type(MXC_CPU_MX31); mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
imx_idle = imx3_idle; pm_idle = imx3_idle;
imx_ioremap = imx3_ioremap; imx_ioremap = imx3_ioremap;
} }
@ -194,7 +197,7 @@ void __init imx35_init_early(void)
mxc_set_cpu_type(MXC_CPU_MX35); mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
imx_idle = imx3_idle; pm_idle = imx3_idle;
imx_ioremap = imx3_ioremap; imx_ioremap = imx3_ioremap;
} }

5
arch/arm/mach-mx5/cpu.c
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@ -16,7 +16,7 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/module.h> #include <linux/module.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <asm/io.h> #include <linux/io.h>
static int mx5_cpu_rev = -1; static int mx5_cpu_rev = -1;
@ -67,7 +67,8 @@ static int __init mx51_neon_fixup(void)
if (!cpu_is_mx51()) if (!cpu_is_mx51())
return 0; return 0;
if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) { if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
(elf_hwcap & HWCAP_NEON)) {
elf_hwcap &= ~HWCAP_NEON; elf_hwcap &= ~HWCAP_NEON;
pr_info("Turning off NEON support, detected broken NEON implementation\n"); pr_info("Turning off NEON support, detected broken NEON implementation\n");
} }

4
arch/arm/mach-mx5/mm.c
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@ -23,7 +23,9 @@
static void imx5_idle(void) static void imx5_idle(void)
{ {
if (!need_resched())
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
local_irq_enable();
} }
/* /*
@ -89,7 +91,7 @@ void __init imx51_init_early(void)
mxc_set_cpu_type(MXC_CPU_MX51); mxc_set_cpu_type(MXC_CPU_MX51);
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
imx_idle = imx5_idle; pm_idle = imx5_idle;
} }
void __init imx53_init_early(void) void __init imx53_init_early(void)

1
arch/arm/plat-mxc/include/mach/common.h
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@ -85,7 +85,6 @@ enum mxc_cpu_pwr_mode {
}; };
extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
extern void (*imx_idle)(void);
extern void imx_print_silicon_rev(const char *cpu, int srev); extern void imx_print_silicon_rev(const char *cpu, int srev);
void avic_handle_irq(struct pt_regs *); void avic_handle_irq(struct pt_regs *);

14
arch/arm/plat-mxc/include/mach/mxc.h
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@ -50,20 +50,6 @@
#define IMX_CHIP_REVISION_3_3 0x33 #define IMX_CHIP_REVISION_3_3 0x33
#define IMX_CHIP_REVISION_UNKNOWN 0xff #define IMX_CHIP_REVISION_UNKNOWN 0xff
#define IMX_CHIP_REVISION_1_0_STRING "1.0"
#define IMX_CHIP_REVISION_1_1_STRING "1.1"
#define IMX_CHIP_REVISION_1_2_STRING "1.2"
#define IMX_CHIP_REVISION_1_3_STRING "1.3"
#define IMX_CHIP_REVISION_2_0_STRING "2.0"
#define IMX_CHIP_REVISION_2_1_STRING "2.1"
#define IMX_CHIP_REVISION_2_2_STRING "2.2"
#define IMX_CHIP_REVISION_2_3_STRING "2.3"
#define IMX_CHIP_REVISION_3_0_STRING "3.0"
#define IMX_CHIP_REVISION_3_1_STRING "3.1"
#define IMX_CHIP_REVISION_3_2_STRING "3.2"
#define IMX_CHIP_REVISION_3_3_STRING "3.3"
#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown"
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type; extern unsigned int __mxc_cpu_type;
#endif #endif

5
arch/arm/plat-mxc/include/mach/system.h
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@ -17,13 +17,8 @@
#ifndef __ASM_ARCH_MXC_SYSTEM_H__ #ifndef __ASM_ARCH_MXC_SYSTEM_H__
#define __ASM_ARCH_MXC_SYSTEM_H__ #define __ASM_ARCH_MXC_SYSTEM_H__
extern void (*imx_idle)(void);
static inline void arch_idle(void) static inline void arch_idle(void)
{ {
if (imx_idle != NULL)
(imx_idle)();
else
cpu_do_idle(); cpu_do_idle();
} }

1
arch/arm/plat-mxc/system.c
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@ -29,7 +29,6 @@
#include <asm/system.h> #include <asm/system.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
void (*imx_idle)(void) = NULL;
void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL; void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
EXPORT_SYMBOL_GPL(imx_ioremap); EXPORT_SYMBOL_GPL(imx_ioremap);