[ARM] 4832/2: Support AC97CLK on PXA3xx via the clock API
The AC97 clock rate on PXA3xx is generated with a configurable divider from sys_pll. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -109,6 +109,25 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void)
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return (clk / 10000);
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return (clk / 10000);
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}
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}
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/*
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* Return the current AC97 clock frequency.
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*/
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static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
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{
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unsigned long rate = 312000000;
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unsigned long ac97_div;
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ac97_div = AC97_DIV;
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/* This may loose precision for some rates but won't for the
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* standard 24.576MHz.
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*/
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rate /= (ac97_div >> 12) & 0x7fff;
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rate *= (ac97_div & 0xfff);
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return rate;
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}
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/*
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/*
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* Return the current HSIO bus clock frequency
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* Return the current HSIO bus clock frequency
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*/
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*/
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@ -156,6 +175,12 @@ static const struct clkops clk_pxa3xx_hsio_ops = {
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.getrate = clk_pxa3xx_hsio_getrate,
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.getrate = clk_pxa3xx_hsio_getrate,
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};
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};
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static const struct clkops clk_pxa3xx_ac97_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_ac97_getrate,
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};
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static void clk_pout_enable(struct clk *clk)
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static void clk_pout_enable(struct clk *clk)
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{
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{
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OSCC |= OSCC_PEN;
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OSCC |= OSCC_PEN;
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@ -197,8 +222,9 @@ static struct clk pxa3xx_clks[] = {
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.delay = 70,
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.delay = 70,
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},
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},
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PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
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PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
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PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
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PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
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PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL),
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PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
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PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
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PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
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PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
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