a7y18lte-ubports/android_kernel_samsung_universal7885
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PCI: Skip cardbus assigned resource reset during pci bus rescan

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Otherwise when rescan is used for cardbus, assigned resources will get
cleared.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Tested-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Yinghai Lu 2012-02-10 15:33:48 -08:00 committed by Jesse Barnes
parent 1184893439
commit 3796f1e2ca
1 changed files with 14 additions and 0 deletions
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14
drivers/pci/setup-bus.c
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@ -901,6 +901,8 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
u16 ctrl; u16 ctrl;
if (b_res[0].parent)
goto handle_b_res_1;
/* /*
* Reserve some resources for CardBus. We reserve * Reserve some resources for CardBus. We reserve
* a fixed amount of bus space for CardBus bridges. * a fixed amount of bus space for CardBus bridges.
@ -914,6 +916,9 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
pci_cardbus_io_size); pci_cardbus_io_size);
} }
handle_b_res_1:
if (b_res[1].parent)
goto handle_b_res_2;
b_res[1].start = pci_cardbus_io_size; b_res[1].start = pci_cardbus_io_size;
b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
@ -923,6 +928,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
pci_cardbus_io_size); pci_cardbus_io_size);
} }
handle_b_res_2:
/* MEM1 must not be pref mmio */ /* MEM1 must not be pref mmio */
pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
@ -942,6 +948,8 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
} }
if (b_res[2].parent)
goto handle_b_res_3;
/* /*
* If we have prefetchable memory support, allocate * If we have prefetchable memory support, allocate
* two regions. Otherwise, allocate one region of * two regions. Otherwise, allocate one region of
@ -962,6 +970,9 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
b_res_3_size = pci_cardbus_mem_size; b_res_3_size = pci_cardbus_mem_size;
} }
handle_b_res_3:
if (b_res[3].parent)
goto handle_done;
b_res[3].start = pci_cardbus_mem_size; b_res[3].start = pci_cardbus_mem_size;
b_res[3].end = b_res[3].start + b_res_3_size - 1; b_res[3].end = b_res[3].start + b_res_3_size - 1;
b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
@ -970,6 +981,9 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
pci_cardbus_mem_size); pci_cardbus_mem_size);
} }
handle_done:
;
} }
void __ref __pci_bus_size_bridges(struct pci_bus *bus, void __ref __pci_bus_size_bridges(struct pci_bus *bus,