a7y18lte-ubports/android_kernel_samsung_universal7885
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[ALSA] intel8x0: another attempt to fix ac97_clock measure routine

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Appearently, a big delay ~300ms is required before hw is settled and ready
to transfer samples on some hardware variants. Also, return back
"clocking to 48000Hz" message when something fails.

Signed-off-by: Jaroslav Kysela <perex@perex.cz>
This commit is contained in:
Jaroslav Kysela 2009-04-21 15:30:31 +02:00
parent e10f9d87c9
commit 30fd9940ee
1 changed files with 4 additions and 2 deletions
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6
sound/pci/intel8x0.c
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@ -2751,11 +2751,12 @@ static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
if (pos == 0) { if (pos == 0) {
snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n"); snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
__retry: __retry:
if (attempt < 2) { if (attempt < 3) {
msleep(300);
attempt++; attempt++;
goto __again; goto __again;
} }
return; goto __end;
} }
pos /= 4; pos /= 4;
@ -2782,6 +2783,7 @@ static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
else if (pos < 47500 || pos > 48500) else if (pos < 47500 || pos > 48500)
/* not 48000Hz, tuning the clock.. */ /* not 48000Hz, tuning the clock.. */
chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
__end:
printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock); printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0); snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
} }