394 lines
8.8 KiB
C
394 lines
8.8 KiB
C
/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* EXYNOS - CPU PMU(Power Management Unit) support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/smp.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <asm/smp_plat.h>
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#include <soc/samsung/exynos-pmu.h>
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/**
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* "pmureg" has the mapped base address of PMU(Power Management Unit)
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*/
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static struct regmap *pmureg;
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/**
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* No driver refers the "pmureg" directly, through the only exported API.
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*/
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int exynos_pmu_read(unsigned int offset, unsigned int *val)
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{
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return regmap_read(pmureg, offset, val);
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}
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int exynos_pmu_write(unsigned int offset, unsigned int val)
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{
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return regmap_write(pmureg, offset, val);
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}
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int exynos_pmu_update(unsigned int offset, unsigned int mask, unsigned int val)
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{
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return regmap_update_bits(pmureg, offset, mask, val);
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}
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EXPORT_SYMBOL(exynos_pmu_read);
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EXPORT_SYMBOL(exynos_pmu_write);
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EXPORT_SYMBOL(exynos_pmu_update);
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/**
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* CPU power control registers in PMU are arranged at regular intervals
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* (interval = 0x80). pmu_cpu_offset calculates how far cpu is from address
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* of first cpu. This expression is based on cpu and cluster id in MPIDR,
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* refer below.
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* cpu address offset : ((cluster id << 2) | (cpu id)) * 0x80
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*/
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#ifndef CONFIG_SOC_EXYNOS7885
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#define pmu_cpu_offset(mpidr) \
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(( MPIDR_AFFINITY_LEVEL(mpidr, 1) << 2 \
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| MPIDR_AFFINITY_LEVEL(mpidr, 0)) \
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* 0x80)
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#else
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#define CLUSTER0_CORES_CNT (2)
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#define CLUSTER2_CORES_CNT (2)
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unsigned int pmu_cpu_offset(unsigned int mpidr)
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{
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unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int offset = 0;
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unsigned int cpuid = 0;
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// It's base on the PMU's offset.
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switch (cluster) {
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case 1:
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cpuid += CLUSTER2_CORES_CNT;
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case 2:
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cpuid += CLUSTER0_CORES_CNT;
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case 0:
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cpuid += MPIDR_AFFINITY_LEVEL(mpidr, 0);
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break;
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}
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offset = 0x80 * cpuid;
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return offset;
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}
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#endif
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#define PMU_CPU_CONFIG_BASE 0x2000
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#define PMU_CPU_STATUS_BASE 0x2004
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#define CPU_LOCAL_PWR_CFG 0xF
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static void pmu_cpu_ctrl(unsigned int cpu, int enable)
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{
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unsigned int mpidr = cpu_logical_map(cpu);
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unsigned int offset;
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offset = pmu_cpu_offset(mpidr);
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regmap_update_bits(pmureg, PMU_CPU_CONFIG_BASE + offset,
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CPU_LOCAL_PWR_CFG,
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enable ? CPU_LOCAL_PWR_CFG : 0);
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}
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static int pmu_cpu_state(unsigned int cpu)
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{
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unsigned int mpidr = cpu_logical_map(cpu);
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unsigned int offset, val = 0;
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offset = pmu_cpu_offset(mpidr);
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regmap_read(pmureg, PMU_CPU_STATUS_BASE + offset, &val);
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return ((val & CPU_LOCAL_PWR_CFG) == CPU_LOCAL_PWR_CFG);
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}
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#define CLUSTER_ADDR_OFFSET 0x20
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#define PMU_CPUSEQ_OPTION_BASE 0x2488
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#define PMU_NONCPU_STATUS_BASE 0x2404
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#define PMU_L2_STATUS_BASE 0x2604
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#define NONCPU_LOCAL_PWR_CFG 0xF
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#define L2_LOCAL_PWR_CFG 0x7
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#define phy_cluster(cpu) MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1)
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static void pmu_cpuseq_ctrl(unsigned int cpu, int enable)
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{
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unsigned int offset;
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offset = phy_cluster(cpu) * CLUSTER_ADDR_OFFSET;
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regmap_update_bits(pmureg,
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PMU_CPUSEQ_OPTION_BASE + offset, 1, enable);
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}
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static bool pmu_noncpu_state(unsigned int cpu)
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{
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unsigned int noncpu_stat = 0;
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unsigned int offset;
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offset = phy_cluster(cpu) * CLUSTER_ADDR_OFFSET;
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regmap_read(pmureg,
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PMU_NONCPU_STATUS_BASE + offset, &noncpu_stat);
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return !!(noncpu_stat & NONCPU_LOCAL_PWR_CFG);
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}
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static bool pmu_l2_state(unsigned int cpu)
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{
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unsigned int l2_stat = 0;
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unsigned int offset;
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offset = phy_cluster(cpu) * CLUSTER_ADDR_OFFSET;
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regmap_read(pmureg,
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PMU_L2_STATUS_BASE + offset, &l2_stat);
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return !!(l2_stat & L2_LOCAL_PWR_CFG);
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}
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static void exynos_cpu_up(unsigned int cpu)
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{
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pmu_cpu_ctrl(cpu, 1);
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}
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static void exynos_cpu_down(unsigned int cpu)
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{
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pmu_cpu_ctrl(cpu, 0);
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}
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static int exynos_cpu_state(unsigned int cpu)
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{
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return pmu_cpu_state(cpu);
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}
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static void exynos_cluster_up(unsigned int cpu)
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{
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pmu_cpuseq_ctrl(cpu, false);
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}
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static void exynos_cluster_down(unsigned int cpu)
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{
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pmu_cpuseq_ctrl(cpu, true);
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}
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static int exynos_cluster_state(unsigned int cpu)
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{
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return pmu_l2_state(cpu) &&
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pmu_noncpu_state(cpu);
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}
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struct exynos_cpu_power_ops exynos_cpu = {
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.power_up = exynos_cpu_up,
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.power_down = exynos_cpu_down,
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.power_state = exynos_cpu_state,
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.cluster_up = exynos_cluster_up,
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.cluster_down = exynos_cluster_down,
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.cluster_state = exynos_cluster_state,
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};
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#define PMU_CPU_RESET_BASE (0x200C)
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#define DISABLE_WDT_CPUPORESET BIT(12)
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#define DISABLE_CORERESET BIT(9)
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#define DISABLE_CPUPORESET BIT(8)
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#define DISABLE_RESET (DISABLE_WDT_CPUPORESET \
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| DISABLE_CORERESET \
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| DISABLE_CPUPORESET)
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void exynos_cpu_reset_enable(unsigned int cpu)
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{
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unsigned int mpidr = cpu_logical_map(cpu);
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unsigned int offset;
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offset = pmu_cpu_offset(mpidr);
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regmap_update_bits(pmureg, PMU_CPU_RESET_BASE + offset,
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DISABLE_RESET, 0);
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}
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void exynos_cpu_reset_disable(unsigned int cpu)
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{
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unsigned int mpidr = cpu_logical_map(cpu);
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unsigned int offset;
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offset = pmu_cpu_offset(mpidr);
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regmap_update_bits(pmureg, PMU_CPU_RESET_BASE + offset,
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DISABLE_RESET, DISABLE_RESET);
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}
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static struct bus_type exynos_info_subsys = {
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.name = "exynos_info",
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.dev_name = "exynos_info",
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};
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#ifndef CONFIG_SOC_EXYNOS7885
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#define NR_CPUS_PER_CLUSTER 4
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static ssize_t core_status_show(struct kobject *kobj,
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struct kobj_attribute *attr, char *buf)
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{
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ssize_t n = 0;
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int cpu;
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for_each_possible_cpu(cpu) {
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/*
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* Each cluster has four cores.
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* "cpu % NR_CPUS_PER_CLUSTER == 0" means that
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* the cpu is a first one of each cluster.
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*/
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if (!(cpu % NR_CPUS_PER_CLUSTER)) {
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n += scnprintf(buf + n, 24, "%s L2 : %d\n",
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(!cpu) ? "boot" : "nonboot",
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pmu_l2_state(cpu));
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n += scnprintf(buf + n, 24, "%s Noncpu : %d\n",
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(!cpu) ? "boot" : "nonboot",
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pmu_noncpu_state(cpu));
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}
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n += scnprintf(buf + n, 24, "CPU%d : %d\n",
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cpu, pmu_cpu_state(cpu));
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}
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return n;
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}
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#else
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static ssize_t core_status_show(struct kobject *kobj,
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struct kobj_attribute *attr, char *buf)
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{
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ssize_t n = 0;
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int cpu = 0;
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for_each_possible_cpu(cpu) {
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unsigned int mpidr = cpu_logical_map(cpu);
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unsigned int phy_cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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if (!phy_cpu) {
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n += scnprintf(buf + n, 24, "%s L2 : %d\n",
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(!cpu) ? "boot" : "nonboot",
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pmu_l2_state(cpu));
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n += scnprintf(buf + n, 24, "%s Noncpu : %d\n",
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(!cpu) ? "boot" : "nonboot",
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pmu_noncpu_state(cpu));
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}
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n += scnprintf(buf + n, 24, "CPU%d : %d\n",
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cpu, pmu_cpu_state(cpu));
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}
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return n;
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}
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#endif
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static struct kobj_attribute cs_attr =
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__ATTR(core_status, 0644, core_status_show, NULL);
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static struct attribute *cs_sysfs_attrs[] = {
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&cs_attr.attr,
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NULL,
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};
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static struct attribute_group cs_sysfs_group = {
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.attrs = cs_sysfs_attrs,
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};
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static const struct attribute_group *cs_sysfs_groups[] = {
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&cs_sysfs_group,
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NULL,
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};
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#include <linux/delay.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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static int pmu_cpus_notifier(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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unsigned long timeout;
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int cpu, cnt = 0;
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int ret = NOTIFY_OK;
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struct cpumask mask;
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switch (event) {
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case CPUS_DOWN_COMPLETE:
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#ifdef CONFIG_SCHED_HMP
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cpumask_andnot(&mask, &hmp_fast_cpu_mask, (struct cpumask *)data);
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#endif
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/*
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* Wait for core power down
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*/
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timeout = jiffies + msecs_to_jiffies(2000);
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while (time_before(jiffies, timeout)) {
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for_each_cpu(cpu, &mask)
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if (cpu_is_offline(cpu) && !exynos_cpu_state(cpu))
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cnt++;
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if (cnt == cpumask_weight(&mask))
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break;
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cnt = 0;
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udelay(1);
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}
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if (!cnt) {
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pr_err("%s: outgoing CPUs are not turned off during 2sec.\n",
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__func__);
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ret = NOTIFY_BAD;
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}
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break;
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default:
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break;
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}
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return ret;
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}
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static struct notifier_block exynos_pmu_cpus_nb = {
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.notifier_call = pmu_cpus_notifier,
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.priority = INT_MAX, /* want to be called first */
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};
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static int exynos_pmu_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
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"samsung,syscon-phandle");
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if (IS_ERR(pmureg)) {
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pr_err("Fail to get regmap of PMU\n");
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return PTR_ERR(pmureg);
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}
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if (subsys_system_register(&exynos_info_subsys,
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cs_sysfs_groups))
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pr_err("Fail to register exynos_info subsys\n");
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register_cpus_notifier(&exynos_pmu_cpus_nb);
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return 0;
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}
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static const struct of_device_id of_exynos_pmu_match[] = {
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{ .compatible = "samsung,exynos-pmu", },
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{ },
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};
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static const struct platform_device_id exynos_pmu_ids[] = {
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{ "exynos-pmu", },
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{ }
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};
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static struct platform_driver exynos_pmu_driver = {
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.driver = {
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.name = "exynos-pmu",
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.owner = THIS_MODULE,
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.of_match_table = of_exynos_pmu_match,
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},
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.probe = exynos_pmu_probe,
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.id_table = exynos_pmu_ids,
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};
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int __init exynos_pmu_init(void)
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{
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return platform_driver_register(&exynos_pmu_driver);
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}
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subsys_initcall(exynos_pmu_init);
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