android_kernel_samsung_a7y1.../drivers/clk/mmp
Lubomir Rintel a040e70f5b clk: mmp2: Fix the order of timer mux parents
[ Upstream commit 8bea5ac0fbc5b2103f8779ddff216122e3c2e1ad ]

Determined empirically, no documentation is available.

The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
what is going on, ended up just dividing the rate as of
commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")'

Link: https://lore.kernel.org/r/20191218190454.420358-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-04-07 13:48:33 +02:00
..
clk-apbc.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-apmu.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-frac.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-gate.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-mix.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-mmp2.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-of-mmp2.c clk: mmp2: Fix the order of timer mux parents 2020-04-07 13:48:33 +02:00
clk-of-pxa168.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-of-pxa910.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-of-pxa1928.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-pxa168.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-pxa910.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
Makefile A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
reset.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
reset.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30