c067b5bd9a
commit 706d51681d636a0c4a5ef53395ec3b803e45ed4d upstream. Future Intel processors will support "Enhanced IBRS" which is an "always on" mode i.e. IBRS bit in SPEC_CTRL MSR is enabled once and never disabled. >From the specification [1]: "With enhanced IBRS, the predicted targets of indirect branches executed cannot be controlled by software that was executed in a less privileged predictor mode or on another logical processor. As a result, software operating on a processor with enhanced IBRS need not use WRMSR to set IA32_SPEC_CTRL.IBRS after every transition to a more privileged predictor mode. Software can isolate predictor modes effectively simply by setting the bit once. Software need not disable enhanced IBRS prior to entering a sleep state such as MWAIT or HLT." If Enhanced IBRS is supported by the processor then use it as the preferred spectre v2 mitigation mechanism instead of Retpoline. Intel's Retpoline white paper [2] states: "Retpoline is known to be an effective branch target injection (Spectre variant 2) mitigation on Intel processors belonging to family 6 (enumerated by the CPUID instruction) that do not have support for enhanced IBRS. On processors that support enhanced IBRS, it should be used for mitigation instead of retpoline." The reason why Enhanced IBRS is the recommended mitigation on processors which support it is that these processors also support CET which provides a defense against ROP attacks. Retpoline is very similar to ROP techniques and might trigger false positives in the CET defense. If Enhanced IBRS is selected as the mitigation technique for spectre v2, the IBRS bit in SPEC_CTRL MSR is set once at boot time and never cleared. Kernel also has to make sure that IBRS bit remains set after VMEXIT because the guest might have cleared the bit. This is already covered by the existing x86_spec_ctrl_set_guest() and x86_spec_ctrl_restore_host() speculation control functions. Enhanced IBRS still requires IBPB for full mitigation. [1] Speculative-Execution-Side-Channel-Mitigations.pdf [2] Retpoline-A-Branch-Target-Injection-Mitigation.pdf Both documents are available at: https://bugzilla.kernel.org/show_bug.cgi?id=199511 Originally-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Tim C Chen <tim.c.chen@intel.com> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Ravi Shankar <ravi.v.shankar@intel.com> Link: https://lkml.kernel.org/r/1533148945-24095-1-git-send-email-sai.praneeth.prakhya@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> [bwh: Backported to 4.4: - Use the next bit from feature word 7 - Adjust context] Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
338 lines
19 KiB
C
338 lines
19 KiB
C
#ifndef _ASM_X86_CPUFEATURES_H
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#define _ASM_X86_CPUFEATURES_H
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#ifndef _ASM_X86_REQUIRED_FEATURES_H
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#include <asm/required-features.h>
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#endif
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#ifndef _ASM_X86_DISABLED_FEATURES_H
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#include <asm/disabled-features.h>
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#endif
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/*
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* Defines x86 CPU feature bits
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*/
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#define NCAPINTS 19 /* N 32-bit words worth of info */
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#define NBUGINTS 1 /* N 32-bit bug flags */
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/*
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* Note: If the comment begins with a quoted string, that string is used
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* in /proc/cpuinfo instead of the macro name. If the string is "",
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* this feature bit is not displayed in /proc/cpuinfo at all.
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*/
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/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
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#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
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#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
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#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
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#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
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#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
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#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
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#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
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#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
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#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
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#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
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#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
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#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
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#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
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#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
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#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */
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/* (plus FCMOVcc, FCOMI with FPU) */
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#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
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#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
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#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
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#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
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#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
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#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
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#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
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#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
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#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
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#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
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#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
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#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
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#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
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#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
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#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
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/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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/* Don't duplicate feature flags which are redundant with Intel! */
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#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */
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#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */
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#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */
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#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */
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#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
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#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */
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#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */
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#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */
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#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */
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#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */
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/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
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#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
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#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
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#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
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/* Other features, Linux-defined mapping, word 3 */
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/* This range is used for feature bits which conflict or are synthesized */
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#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
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#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
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#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
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#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
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/* cpu types for specific tunings: */
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#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
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#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */
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#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
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#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
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#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
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#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */
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/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */
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#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
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#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
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#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */
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#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */
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#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */
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#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */
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#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
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#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
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/* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */
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#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
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#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
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#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
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#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
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/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
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#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
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#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
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#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
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#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
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#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */
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#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
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#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */
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#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
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#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */
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#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */
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#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */
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#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */
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#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
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#define X86_FEATURE_CID ( 4*32+10) /* Context ID */
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#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */
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#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */
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#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */
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#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */
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#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */
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#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */
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#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
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#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
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#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */
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#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */
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#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */
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#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */
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#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */
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#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
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#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */
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#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */
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#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */
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#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */
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#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */
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/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
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#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */
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#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
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#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
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#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
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#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
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#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */
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#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */
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#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */
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#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */
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#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */
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/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
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#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */
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#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */
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#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */
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#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */
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#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
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#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */
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#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */
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#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
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#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
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#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */
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#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */
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#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */
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#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */
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#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */
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#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */
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#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */
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#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */
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#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */
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#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */
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#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */
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#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
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#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
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#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
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#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */
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#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */
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/*
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* Auxiliary flags: Linux defined - For features scattered in various
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* CPUID levels like 0x6, 0xA etc, word 7.
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*
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* Reuse free bits when adding new feature flags!
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*/
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#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
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#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
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#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 4) /* Effectively INVPCID && CR4.PCIDE=1 */
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#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
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#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */
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#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
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#define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */
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/* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */
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#define X86_FEATURE_KAISER ( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */
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#define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled*/
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#define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
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#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
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#define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation */
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#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
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#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
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#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
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#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
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#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
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#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
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#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
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#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */
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#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
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#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
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#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */
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#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
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#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
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#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
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#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
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#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
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#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
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#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
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#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
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#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
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#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
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#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
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#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
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#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
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#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
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#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */
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#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
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#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
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#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
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#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
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#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
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#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
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/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
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#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
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#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */
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#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */
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#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
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/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
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#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
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/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
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#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
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/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
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#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
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#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
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#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
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#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */
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#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
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#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */
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#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */
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#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */
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#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */
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#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
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#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */
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#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
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#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
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#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
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/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */
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#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
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#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */
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#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */
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#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
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#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
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#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
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#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */
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#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */
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#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
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#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */
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#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
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#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
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/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
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#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */
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#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */
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#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
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#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
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#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
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#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
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#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
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#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
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/*
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* BUG word(s)
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*/
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#define X86_BUG(x) (NCAPINTS*32 + (x))
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#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
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#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
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#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
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#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
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#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
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#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
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#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
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#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
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#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
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#define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */
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#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */
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#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
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#define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */
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#define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
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#endif /* _ASM_X86_CPUFEATURES_H */
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