196 lines
5.7 KiB
C
196 lines
5.7 KiB
C
/*
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* Copyright (C) 2015 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PHY_EXYNOS_USBDRD_H__
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#define __PHY_EXYNOS_USBDRD_H__
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#include "phy-samsung-usb-cal.h"
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#include "phy-samsung-usb3-cal.h"
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#include "phy-exynos-usb3p1.h"
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#include "phy-exynos-usbdp.h"
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#define EXYNOS_USBPHY_VER_02_0_0 0x0200 /* Lhotse - USBDP Combo PHY */
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#define EXYNOS_USBDP_PHY_CONTROL (0x704)
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#define EXYNOS_USB2_PHY_CONTROL (0x72C)
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/* PMU register offset for USB */
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#define EXYNOS_USBDEV_PHY_CONTROL (0x704)
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#define EXYNOS_USBDRD_ENABLE BIT(0)
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#define EXYNOS_USBHOST_ENABLE BIT(1)
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/* Exynos USB PHY registers */
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#define EXYNOS_FSEL_9MHZ6 0x0
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#define EXYNOS_FSEL_10MHZ 0x1
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#define EXYNOS_FSEL_12MHZ 0x2
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#define EXYNOS_FSEL_19MHZ2 0x3
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#define EXYNOS_FSEL_20MHZ 0x4
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#define EXYNOS_FSEL_24MHZ 0x5
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#define EXYNOS_FSEL_26MHZ 0x82
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#define EXYNOS_FSEL_50MHZ 0x7
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/* EXYNOS: USB DRD PHY registers */
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#define EXYNOS_DRD_LINKSYSTEM 0x04
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#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
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#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
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#define EXYNOS_DRD_PHYUTMI 0x08
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#define EXYNOS_DRD_PHYPIPE 0x0c
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#define PHYPIPE_PHY_CLOCK_SEL (0x1 << 4)
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#define EXYNOS_DRD_PHYCLKRST 0x10
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#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
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#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
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#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
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#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
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#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
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#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
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#define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8)
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#define PHYCLKRST_FSEL(_x) ((_x) << 5)
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#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
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#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
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#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
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#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
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#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
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#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
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#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
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#define EXYNOS_DRD_PHYREG0 0x14
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#define EXYNOS_DRD_PHYREG1 0x18
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#define EXYNOS_DRD_PHYPARAM0 0x1c
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#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
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#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
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#define EXYNOS_DRD_PHYPARAM1 0x20
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#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
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#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
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#define EXYNOS_DRD_PHYTERM 0x24
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#define EXYNOS_DRD_PHYTEST 0x28
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#define EXYNOS_DRD_PHYADP 0x2c
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#define EXYNOS_DRD_PHYUTMICLKSEL 0x30
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#define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2)
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#define EXYNOS_DRD_PHYRESUME 0x34
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#define EXYNOS_DRD_LINKPORT 0x44
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#define KHZ 1000
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#define MHZ (KHZ * KHZ)
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#define EXYNOS_DRD_MAX_TUNEPARAM_NUM 32
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enum exynos_usbdrd_phy_id {
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EXYNOS_DRDPHY_UTMI,
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EXYNOS_DRDPHY_PIPE3,
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EXYNOS_DRDPHYS_NUM,
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};
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enum exynos_usbdrd_ext_refclk_state {
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EXYNOS_EXTCLK_SUCCESS = 0,
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EXYNOS_EXTCLK_STARTED,
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EXYNOS_EXTCLK_STOPPED,
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EXYNOS_NOT_STARTED,
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EXYNOS_NOT_STOPPED,
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};
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struct phy_usb_instance;
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struct exynos_usbdrd_phy;
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struct exynos_usbdrd_phy_config {
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u32 id;
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void (*phy_isol)(struct phy_usb_instance *inst, u32 on, unsigned int);
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void (*phy_init)(struct exynos_usbdrd_phy *phy_drd);
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void (*phy_exit)(struct exynos_usbdrd_phy *phy_drd);
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void (*phy_tune)(struct exynos_usbdrd_phy *phy_drd, int);
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void (*phy_set)(struct exynos_usbdrd_phy *phy_drd, int, void *);
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unsigned int (*set_refclk)(struct phy_usb_instance *inst);
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};
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struct exynos_usbdrd_phy_drvdata {
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const struct exynos_usbdrd_phy_config *phy_cfg;
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};
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/**
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* struct exynos_usbdrd_phy - driver data for USB DRD PHY
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* @dev: pointer to device instance of this platform device
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* @reg_phy: usb phy controller register memory base
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* @clk: phy clock for register access
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* @drv_data: pointer to SoC level driver data structure
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* @phys[]: array for 'EXYNOS_DRDPHYS_NUM' number of PHY
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* instances each with its 'phy' and 'phy_cfg'.
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* @extrefclk: frequency select settings when using 'separate
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* reference clocks' for SS and HS operations
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* @ref_clk: reference clock to PHY block from which PHY's
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* operational clocks are derived
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* @ref_rate: rate of above reference clock
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*/
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struct exynos_usbdrd_phy {
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struct device *dev;
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void __iomem *reg_phy;
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void __iomem *reg_phy2;
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void __iomem *reg_phy3;
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struct clk **clocks;
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struct clk **phy_clocks;
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const struct exynos_usbdrd_phy_drvdata *drv_data;
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struct phy_usb_instance {
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struct phy *phy;
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u32 index;
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struct regmap *reg_pmu;
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u32 pmu_offset;
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u32 pmu_offset_dp;
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u32 pmu_mask;
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const struct exynos_usbdrd_phy_config *phy_cfg;
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} phys[EXYNOS_DRDPHYS_NUM];
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u32 extrefclk;
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u32 request_extrefclk;
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bool extrefclk_requested;
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bool use_phy_umux;
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struct completion can_use_extrefclk;
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int (*request_extrefclk_cb)(void);
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int (*release_extrefclk_cb)(void);
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struct clk *ref_clk;
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struct regulator *vbus;
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struct exynos_usbphy_info usbphy_info;
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struct exynos_usbphy_info usbphy_sub_info;
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struct exynos_usbphy_ss_tune ss_value[2];
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struct exynos_usbphy_hs_tune hs_value[2];
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int hs_tune_param_value[EXYNOS_DRD_MAX_TUNEPARAM_NUM][2];
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int ss_tune_param_value[EXYNOS_DRD_MAX_TUNEPARAM_NUM][2];
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u32 ip_type;
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#if IS_ENABLED(CONFIG_EXYNOS_OTP)
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#define OTP_SUPPORT_USBPHY_NUMBER 2
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#define OTP_USB3PHY_INDEX 0
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#define OTP_USB2PHY_INDEX 1
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u8 otp_type[OTP_SUPPORT_USBPHY_NUMBER];
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u8 otp_index[OTP_SUPPORT_USBPHY_NUMBER];
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struct tune_bits *otp_data[OTP_SUPPORT_USBPHY_NUMBER];
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#endif
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u32 phy_port;
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};
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#endif /* __PHY_EXYNOS_USBDRD_H__ */
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