android_kernel_samsung_a7y1.../drivers/clk
Douglas Anderson 4774c97d80 clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288
[ Upstream commit 57a20248ef3e429dc822f0774bc4e00136c46c83 ]

Experimentally it can be seen that going into deep sleep (specifically
setting PMU_CLR_DMA and PMU_CLR_BUS in RK3288_PMU_PWRMODE_CON1)
appears to fail unless "aclk_dmac1" is on.  The failure is that the
system never signals that it made it into suspend on the GLOBAL_PWROFF
pin and it just hangs.

NOTE that it's confirmed that it's the actual suspend that fails, not
one of the earlier calls to read/write registers.  Specifically if you
comment out the "PMU_GLOBAL_INT_DISABLE" setting in
rk3288_slp_mode_set() and then comment out the "cpu_do_idle()" call in
rockchip_lpmode_enter() then you can exercise the whole suspend path
without any crashing.

This is currently not a problem with suspend upstream because there is
no current way to exercise the deep suspend code.  However, anyone
trying to make it work will run into this issue.

This was not a problem on shipping rk3288-based Chromebooks because
those devices all ran on an old kernel based on 3.14.  On that kernel
"aclk_dmac1" appears to be left on all the time.

There are several ways to skin this problem.

A) We could add "aclk_dmac1" to the list of critical clocks and that
apperas to work, but presumably that wastes power.

B) We could keep a list of "struct clk" objects to enable at suspend
time in clk-rk3288.c and use the standard clock APIs.

C) We could make the rk3288-pmu driver keep a list of clocks to enable
at suspend time.  Presumably this would require a dts and bindings
change.

D) We could just whack the clock on in the existing syscore suspend
function where we whack a bunch of other clocks.  This is particularly
easy because we know for sure that the clock's only parent
("aclk_cpu") is a critical clock so we don't need to do anything more
than ungate it.

In this case I have chosen D) because it seemed like the least work,
but any of the other options would presumably also work fine.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-04-06 19:02:15 +02:00
..
at91 A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
bcm A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
berlin A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
h8300 A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
hisilicon A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
imx A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
ingenic A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
keystone A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
mediatek A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
meson A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
mmp A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
mvebu A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
mxs A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
nxp A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
pistachio A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
pxa A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
qcom A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
rockchip clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288 2020-04-06 19:02:15 +02:00
samsung A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
shmobile A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
sirf A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
socfpga A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
spear A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
st A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
sunxi A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
tegra clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider 2020-04-06 18:13:50 +02:00
ti A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
ux500 A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
versatile A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
x86 A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
zte A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
zynq A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-asm9260.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-axi-clkgen.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-axm5516.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-cdce706.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-cdce925.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-clps711x.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-composite.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-conf.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-devres.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-divider.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-efm32gg.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-fixed-factor.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-fixed-rate.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-fractional-divider.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-gate.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-gpio.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-highbank.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-ls1x.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-max-gen.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-max-gen.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-max77686.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-max77802.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-mb86s7x.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-moxart.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-multiplier.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-mux.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-nomadik.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-nspire.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-palmas.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-pwm.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-qoriq.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-rk808.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-s2mps11.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-scpi.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-si514.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-si570.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-si5351.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-si5351.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-stm32f4.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-twl6040.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-u300.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-vt8500.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-wm831x.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-xgene.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clkdev.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
Kconfig A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
Makefile A750FXXU4CTBC 2020-03-27 21:51:54 +05:30