android_kernel_samsung_a7y1.../arch/x86/kvm
Konrad Rzeszutek Wilk 2b0705ab3c x86/bugs: Add AMD's SPEC_CTRL MSR usage
commit 6ac2f49edb1ef5446089c7c660017732886d62d6 upstream.

The AMD document outlining the SSBD handling
124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
mentions that if CPUID 8000_0008.EBX[24] is set we should be using
the SPEC_CTRL MSR (0x48) over the VIRT SPEC_CTRL MSR (0xC001_011f)
for speculative store bypass disable.

This in effect means we should clear the X86_FEATURE_VIRT_SSBD
flag so that we would prefer the SPEC_CTRL MSR.

See the document titled:
   124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf

A copy of this document is available at
   https://bugzilla.kernel.org/show_bug.cgi?id=199889

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
Cc: kvm@vger.kernel.org
Cc: KarimAllah Ahmed <karahmed@amazon.de>
Cc: andrew.cooper3@citrix.com
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Cc: Kees Cook <keescook@chromium.org>
Link: https://lkml.kernel.org/r/20180601145921.9500-3-konrad.wilk@oracle.com
[bwh: Backported to 4.4:
 - Update feature test in guest_cpuid_has_spec_ctrl() instead of
   svm_{get,set}_msr()
 - Adjust context, indentation]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-06 16:50:10 +02:00
..
assigned-dev.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
assigned-dev.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
cpuid.c x86/bugs: Add AMD's SPEC_CTRL MSR usage 2020-04-06 16:50:10 +02:00
cpuid.h x86/bugs: Add AMD's SPEC_CTRL MSR usage 2020-04-06 16:50:10 +02:00
emulate.c KVM: x86: Don't clear EFER during SMM transitions for 32-bit vCPU 2020-04-06 15:49:15 +02:00
hyperv.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
hyperv.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
i8254.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
i8254.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
i8259.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
ioapic.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
ioapic.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
iommu.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
irq_comm.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
irq.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
irq.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
Kconfig A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
kvm_cache_regs.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
lapic.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
lapic.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
Makefile A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
mmu_audit.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
mmu.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
mmu.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
mmutrace.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
mtrr.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
paging_tmpl.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
pmu_amd.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
pmu_intel.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
pmu.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
pmu.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
svm.c x86/bugs: Add AMD's SPEC_CTRL MSR usage 2020-04-06 16:50:10 +02:00
trace.h KVM: x86: avoid misreporting level-triggered irqs as edge-triggered in tracing 2020-04-06 16:43:35 +02:00
tss.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
vmx.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
x86.c KVM: fail KVM_SET_VCPU_EVENTS with invalid exception number 2020-04-06 16:38:35 +02:00
x86.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30