android_kernel_samsung_a7y1.../drivers/clk/rockchip
Heiko Stuebner 73d5dff7f7 clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering
[ Upstream commit ac8cb53829a6ba119082e067f5bc8fab3611ce6a ]

Similar to commit a9f0c0e56371 ("clk: rockchip: fix rk3188 sclk_smc
gate data") there is one other gate clock in the rk3188 clock driver
with a similar wrong ordering, the sclk_mac_lbtest. So fix it as well.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-04-07 12:44:23 +02:00
..
clk-cpu.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-inverter.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-mmc-phase.c clk: rockchip: Don't yell about bad mmc phases when getting 2020-04-06 21:35:47 +02:00
clk-pll.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-rk3188.c clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering 2020-04-07 12:44:23 +02:00
clk-rk3288.c clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288 2020-04-06 19:02:15 +02:00
clk-rk3368.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk-rockchip.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
clk.h A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
Makefile A750FXXU4CTBC 2020-03-27 21:51:54 +05:30
softrst.c A750FXXU4CTBC 2020-03-27 21:51:54 +05:30