491 lines
12 KiB
C
491 lines
12 KiB
C
/*
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* Samsung EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
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*
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* Copyright (C) 2015 Samsung Electronics Co., Ltd.
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* Author: Sewoon Park <seuni.park@samsung.com>
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* Author: Wooki Min <wooki.min@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#define EXYNOS_MIPI_PHY_ISO_BYPASS BIT(0)
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#define EXYNOS_MIPI_PHYS_NUM 6
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#define MIPI_PHY_MxSx_UNIQUE (0 << 1)
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#define MIPI_PHY_MxSx_SHARED (1 << 1)
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#define MIPI_PHY_MxSx_INIT_DONE (2 << 1)
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void __iomem *shared_regs[EXYNOS_MIPI_PHYS_NUM];
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/* reference count for phy-m4s4 */
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static int phy_m4s4_count;
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enum exynos_mipi_phy_type {
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EXYNOS_MIPI_PHY_FOR_DSIM,
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EXYNOS_MIPI_PHY_FOR_CSIS,
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};
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struct mipi_phy_data {
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enum exynos_mipi_phy_type type;
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u8 flags;
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};
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struct exynos_mipi_phy {
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struct device *dev;
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spinlock_t slock;
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void __iomem *regs;
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struct regmap *reg_pmu;
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struct mipi_phy_desc {
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struct phy *phy;
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unsigned int index;
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enum exynos_mipi_phy_type type;
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unsigned int iso_offset;
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unsigned int rst_bit;
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unsigned int init_bit;
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u8 flags;
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} phys[EXYNOS_MIPI_PHYS_NUM];
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};
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/* 1: Isolation bypass, 0: Isolation enable */
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static int __set_phy_isolation(struct regmap *reg_pmu,
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unsigned int offset, unsigned int on)
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{
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unsigned int val;
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int ret;
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val = on ? EXYNOS_MIPI_PHY_ISO_BYPASS : 0;
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ret = regmap_update_bits(reg_pmu, offset,
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EXYNOS_MIPI_PHY_ISO_BYPASS, val);
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pr_debug("%s off=0x%x, val=0x%x\n", __func__, offset, val);
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return ret;
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}
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static int __set_phy_init_ctrl(struct exynos_mipi_phy *state,
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unsigned int bit)
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{
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void __iomem *addr = state->regs;
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unsigned int cfg;
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if (!addr)
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return 0;
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if (IS_ERR(addr)) {
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dev_err(state->dev, "%s Invalid address\n", __func__);
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return -EINVAL;
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}
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cfg = readl(addr);
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cfg &= ~(1 << bit);
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cfg |= (1 << bit);
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writel(cfg, addr);
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pr_debug("%s bit=%d, val=0x%x\n", __func__, bit, cfg);
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return 0;
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}
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/* 1: Enable reset -> release reset, 0: Enable reset */
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static int __set_phy_reset(struct exynos_mipi_phy *state,
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unsigned int bit, unsigned int on)
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{
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void __iomem *addr = state->regs;
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unsigned int cfg;
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if (!addr)
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return 0;
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if (IS_ERR(addr)) {
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dev_err(state->dev, "%s Invalid address\n", __func__);
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return -EINVAL;
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}
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cfg = readl(addr);
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cfg &= ~(1 << bit);
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writel(cfg, addr);
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/* release a reset before using a PHY */
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if (on) {
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cfg |= (1 << bit);
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writel(cfg, addr);
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}
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pr_debug("%s bit=%d, val=0x%x\n", __func__, bit, cfg);
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return 0;
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}
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static int __set_phy_init(struct exynos_mipi_phy *state,
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struct mipi_phy_desc *phy_desc, unsigned int on)
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{
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int ret = 0;
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unsigned int cfg;
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ret = regmap_read(state->reg_pmu,
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phy_desc->iso_offset, &cfg);
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if (ret) {
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dev_err(state->dev, "%s Can't read 0x%x\n",
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__func__, phy_desc->iso_offset);
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ret = -EINVAL;
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goto phy_exit;
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}
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/* Add INIT_DONE flag when ISO is already bypass(LCD_ON_UBOOT) */
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if (cfg && EXYNOS_MIPI_PHY_ISO_BYPASS)
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phy_desc->flags |= MIPI_PHY_MxSx_INIT_DONE;
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if (phy_desc->init_bit != UINT_MAX)
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__set_phy_init_ctrl(state, phy_desc->init_bit);
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phy_exit:
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return ret;
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}
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static int __set_phy_alone(struct exynos_mipi_phy *state,
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struct mipi_phy_desc *phy_desc, unsigned int on)
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{
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&state->slock, flags);
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if (on) {
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ret = __set_phy_isolation(state->reg_pmu,
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phy_desc->iso_offset, on);
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__set_phy_reset(state, phy_desc->rst_bit, on);
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} else {
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__set_phy_reset(state, phy_desc->rst_bit, on);
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ret = __set_phy_isolation(state->reg_pmu,
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phy_desc->iso_offset, on);
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}
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pr_debug("%s: isolation 0x%x, reset 0x%x\n", __func__,
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phy_desc->iso_offset, phy_desc->rst_bit);
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spin_unlock_irqrestore(&state->slock, flags);
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return ret;
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}
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static DEFINE_SPINLOCK(lock_share);
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static int __set_phy_share(struct exynos_mipi_phy *state,
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struct mipi_phy_desc *phy_desc, unsigned int on)
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{
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&lock_share, flags);
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on ? ++phy_m4s4_count : --phy_m4s4_count;
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/* If phy is already initialization(power_on) */
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if (phy_desc->flags & MIPI_PHY_MxSx_INIT_DONE) {
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phy_desc->flags &= (~MIPI_PHY_MxSx_INIT_DONE);
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spin_unlock_irqrestore(&lock_share, flags);
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return ret;
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}
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if (on) {
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/* Isolation bypass when reference count is 1 */
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if (phy_m4s4_count == 1)
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ret = __set_phy_isolation(state->reg_pmu,
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phy_desc->iso_offset, on);
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__set_phy_reset(state, phy_desc->rst_bit, on);
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} else {
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__set_phy_reset(state, phy_desc->rst_bit, on);
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/* Isolation enabled when reference count is zero */
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if (phy_m4s4_count == 0)
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ret = __set_phy_isolation(state->reg_pmu,
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phy_desc->iso_offset, on);
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}
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pr_debug("%s: isolation 0x%x, reset 0x%x\n", __func__,
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phy_desc->iso_offset, phy_desc->rst_bit);
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spin_unlock_irqrestore(&lock_share, flags);
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return ret;
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}
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static int __set_phy_state(struct exynos_mipi_phy *state,
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struct mipi_phy_desc *phy_desc, unsigned int on)
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{
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int ret = 0;
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if (phy_desc->flags & MIPI_PHY_MxSx_SHARED)
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ret = __set_phy_share(state, phy_desc, on);
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else
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ret = __set_phy_alone(state, phy_desc, on);
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return ret;
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}
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static const struct mipi_phy_data mipi_phy_m4sx = {
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.type = EXYNOS_MIPI_PHY_FOR_DSIM,
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.flags = MIPI_PHY_MxSx_SHARED,
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};
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static const struct mipi_phy_data mipi_phy_mxs4 = {
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.type = EXYNOS_MIPI_PHY_FOR_CSIS,
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.flags = MIPI_PHY_MxSx_SHARED,
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};
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static const struct mipi_phy_data mipi_phy_mxs0 = {
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.type = EXYNOS_MIPI_PHY_FOR_DSIM,
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.flags = MIPI_PHY_MxSx_UNIQUE,
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};
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static const struct mipi_phy_data mipi_phy_m0sx = {
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.type = EXYNOS_MIPI_PHY_FOR_CSIS,
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.flags = MIPI_PHY_MxSx_UNIQUE,
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};
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static const struct of_device_id exynos_mipi_phy_of_table[] = {
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{
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.compatible = "samsung,mipi-phy-dsim",
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.data = &mipi_phy_m4sx,
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},
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{
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.compatible = "samsung,mipi-phy-m4",
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.data = &mipi_phy_mxs0,
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},
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{
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.compatible = "samsung,mipi-phy-m2",
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.data = &mipi_phy_mxs0,
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},
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{
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.compatible = "samsung,mipi-phy-m1",
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.data = &mipi_phy_mxs0,
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},
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{
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.compatible = "samsung,mipi-phy-csis",
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.data = &mipi_phy_mxs4,
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},
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{
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.compatible = "samsung,mipi-phy-s4",
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.data = &mipi_phy_m0sx,
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},
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{
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.compatible = "samsung,mipi-phy-s2",
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.data = &mipi_phy_m0sx,
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},
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{
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.compatible = "samsung,mipi-phy-s1",
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.data = &mipi_phy_m0sx,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, exynos_mipi_phy_of_table);
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#define to_mipi_video_phy(desc) \
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container_of((desc), struct exynos_mipi_phy, phys[(desc)->index])
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static int exynos_mipi_phy_init(struct phy *phy)
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{
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struct mipi_phy_desc *phy_desc = phy_get_drvdata(phy);
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struct exynos_mipi_phy *state = to_mipi_video_phy(phy_desc);
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return __set_phy_init(state, phy_desc, 1);
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}
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static int exynos_mipi_phy_power_on(struct phy *phy)
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{
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struct mipi_phy_desc *phy_desc = phy_get_drvdata(phy);
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struct exynos_mipi_phy *state = to_mipi_video_phy(phy_desc);
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return __set_phy_state(state, phy_desc, 1);
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}
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static int exynos_mipi_phy_power_off(struct phy *phy)
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{
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struct mipi_phy_desc *phy_desc = phy_get_drvdata(phy);
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struct exynos_mipi_phy *state = to_mipi_video_phy(phy_desc);
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return __set_phy_state(state, phy_desc, 0);
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}
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static struct phy *exynos_mipi_phy_of_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct exynos_mipi_phy *state = dev_get_drvdata(dev);
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if (WARN_ON(args->args[0] >= EXYNOS_MIPI_PHYS_NUM))
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return ERR_PTR(-ENODEV);
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return state->phys[args->args[0]].phy;
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}
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static struct phy_ops exynos_mipi_phy_ops = {
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.init = exynos_mipi_phy_init,
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.power_on = exynos_mipi_phy_power_on,
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.power_off = exynos_mipi_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int exynos_mipi_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct resource *res;
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struct exynos_mipi_phy *state;
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struct phy_provider *phy_provider;
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struct mipi_phy_data *phy_data;
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const struct of_device_id *of_id;
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unsigned int iso[EXYNOS_MIPI_PHYS_NUM];
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unsigned int rst[EXYNOS_MIPI_PHYS_NUM];
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unsigned int init[EXYNOS_MIPI_PHYS_NUM];
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unsigned int i, elements;
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unsigned int reg_index;
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int ret = 0;
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state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
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if (!state)
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return -ENOMEM;
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state->dev = &pdev->dev;
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of_id = of_match_device(of_match_ptr(exynos_mipi_phy_of_table), dev);
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if (!of_id)
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return -EINVAL;
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phy_data = (struct mipi_phy_data *)of_id->data;
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phy_m4s4_count = 0;
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dev_set_drvdata(dev, state);
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spin_lock_init(&state->slock);
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/* PMU isolation */
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state->reg_pmu = syscon_regmap_lookup_by_phandle(node,
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"samsung,pmu-syscon");
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if (IS_ERR(state->reg_pmu)) {
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dev_err(dev, "Failed to lookup PMU regmap\n");
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return PTR_ERR(state->reg_pmu);
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}
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elements = of_property_count_u32_elems(node, "isolation");
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ret = of_property_read_u32_array(node, "isolation", iso,
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elements);
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if (ret) {
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dev_err(dev, "cannot get mipi-phy isolation!!!\n");
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return ret;
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}
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/* reset control */
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for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; ++i) {
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rst[i] = UINT_MAX;
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init[i] = UINT_MAX;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res) {
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state->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(state->regs))
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return PTR_ERR(state->regs);
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ret = of_property_read_u32_array(node, "reset", rst,
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elements);
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if (ret) {
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dev_err(dev, "cannot get mipi-phy reset!!!\n");
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return ret;
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}
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/* it's optional */
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if (of_property_read_u32_array(node, "init", init,
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elements))
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dev_info(dev, "doesn't use mipi-phy init control!!!\n");
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/* it's optional */
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if (!of_property_read_u32(node, "reg_index", ®_index)) {
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if (reg_index < EXYNOS_MIPI_PHYS_NUM)
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shared_regs[reg_index] = state->regs;
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}
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} else {
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/* it's optional */
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if (of_property_read_u32(node, "reg_index", ®_index)) {
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state->regs = NULL;
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dev_info(dev, "mipi-phy reset be controlled from outside!!!\n");
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} else {
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if (reg_index < EXYNOS_MIPI_PHYS_NUM) {
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state->regs = shared_regs[reg_index];
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if (IS_ERR_OR_NULL(state->regs))
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return PTR_ERR(state->regs);
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ret = of_property_read_u32_array(node, "reset", rst,
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elements);
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if (ret) {
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dev_err(dev, "cannot get mipi-phy reset!!!\n");
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return ret;
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}
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}
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}
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}
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for (i = 0; i < elements; i++) {
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state->phys[i].iso_offset = iso[i];
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state->phys[i].rst_bit = rst[i];
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state->phys[i].init_bit = init[i];
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dev_info(dev, "%s: iso 0x%x, reset %d (%d)\n", __func__,
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state->phys[i].iso_offset, state->phys[i].rst_bit,
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state->phys[i].init_bit);
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}
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for (i = 0; i < elements; i++) {
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struct phy *generic_phy = devm_phy_create(dev, NULL,
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&exynos_mipi_phy_ops);
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if (IS_ERR(generic_phy)) {
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dev_err(dev, "failed to create PHY\n");
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return PTR_ERR(generic_phy);
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}
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state->phys[i].index = i;
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state->phys[i].phy = generic_phy;
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state->phys[i].type = phy_data->type;
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if (i == 0)
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state->phys[i].flags = phy_data->flags;
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else /* 0 index only can support MIPI_PHY_MxSx_SHARED */
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state->phys[i].flags = MIPI_PHY_MxSx_UNIQUE;
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phy_set_drvdata(generic_phy, &state->phys[i]);
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}
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phy_provider = devm_of_phy_provider_register(dev,
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exynos_mipi_phy_of_xlate);
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if (IS_ERR(phy_provider))
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dev_err(dev, "failed to create exynos mipi-phy\n");
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else
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dev_err(dev, "Creating exynos-mipi-phy\n");
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static struct platform_driver exynos_mipi_phy_driver = {
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.probe = exynos_mipi_phy_probe,
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.driver = {
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.name = "exynos-mipi-phy",
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.of_match_table = of_match_ptr(exynos_mipi_phy_of_table),
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}
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};
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module_platform_driver(exynos_mipi_phy_driver);
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MODULE_DESCRIPTION("Samsung EXYNOS SoC MIPI CSI/DSI PHY driver");
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MODULE_LICENSE("GPL v2");
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