544 lines
16 KiB
C
544 lines
16 KiB
C
/*
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* Synopsys DesignWare Multimedia Card Interface driver
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* (Based on NXP driver for lpc 31xx)
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*
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* Copyright (C) 2009 NXP Semiconductors
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* Copyright (C) 2009, 2010 Imagination Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _DW_MMC_H_
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#define _DW_MMC_H_
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#define DW_MMC_MAX_TRANSFER_SIZE 4096
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#define DW_MMC_SECTOR_SIZE 512
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#define MMC_DW_IDMAC_MULTIPLIER 8
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#define DW_MMC_240A 0x240a
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#define DW_MMC_260A 0x260a
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#define SDMMC_CTRL 0x000
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#define SDMMC_PWREN 0x004
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#define SDMMC_CLKDIV 0x008
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#define SDMMC_CLKSRC 0x00c
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#define SDMMC_CLKENA 0x010
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#define SDMMC_TMOUT 0x014
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#define SDMMC_CTYPE 0x018
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#define SDMMC_BLKSIZ 0x01c
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#define SDMMC_BYTCNT 0x020
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#define SDMMC_INTMASK 0x024
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#define SDMMC_CMDARG 0x028
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#define SDMMC_CMD 0x02c
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#define SDMMC_RESP0 0x030
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#define SDMMC_RESP1 0x034
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#define SDMMC_RESP2 0x038
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#define SDMMC_RESP3 0x03c
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#define SDMMC_MINTSTS 0x040
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#define SDMMC_RINTSTS 0x044
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#define SDMMC_STATUS 0x048
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#define SDMMC_FIFOTH 0x04c
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#define SDMMC_CDETECT 0x050
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#define SDMMC_WRTPRT 0x054
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#define SDMMC_GPIO 0x058
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#define SDMMC_TCBCNT 0x05c
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#define SDMMC_TBBCNT 0x060
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#define SDMMC_DEBNCE 0x064
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#define SDMMC_USRID 0x068
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#define SDMMC_VERID 0x06c
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#define SDMMC_HCON 0x070
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#define SDMMC_UHS_REG 0x074
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#define SDMMC_BMOD 0x080
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#define SDMMC_PLDMND 0x084
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#define SDMMC_DBADDR 0x088
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#define SDMMC_IDSTS 0x08c
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#define SDMMC_IDINTEN 0x090
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#define SDMMC_DSCADDR 0x094
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#define SDMMC_BUFADDR 0x098
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#define SDMMC_RESP_TAT 0x0AC
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#define SDMMC_CDTHRCTL 0x100
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#define SDMMC_DATA(x) (x)
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/*
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* Data offset is difference according to Version
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* Lower than 2.40a : data register offest is 0x100
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*/
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#define DATA_OFFSET 0x100
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#define DATA_240A_OFFSET 0x200
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/* shift bit field */
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#define _SBF(f, v) ((v) << (f))
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/* Control register defines */
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#define SDMMC_CTRL_USE_IDMAC BIT(25)
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#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
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#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
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#define SDMMC_CTRL_SEND_CCSD BIT(9)
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#define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
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#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
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#define SDMMC_CTRL_READ_WAIT BIT(6)
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#define SDMMC_CTRL_DMA_ENABLE BIT(5)
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#define SDMMC_CTRL_INT_ENABLE BIT(4)
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#define SDMMC_CTRL_DMA_RESET BIT(2)
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#define SDMMC_CTRL_FIFO_RESET BIT(1)
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#define SDMMC_CTRL_RESET BIT(0)
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/* Clock Enable register defines */
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#define SDMMC_CLKEN_LOW_PWR BIT(16)
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#define SDMMC_CLKEN_ENABLE BIT(0)
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/* time-out register defines */
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#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
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#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
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#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
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#define SDMMC_TMOUT_RESP_MSK 0xFF
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/* card-type register defines */
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#define SDMMC_CTYPE_8BIT BIT(16)
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#define SDMMC_CTYPE_4BIT BIT(0)
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#define SDMMC_CTYPE_1BIT 0
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/* Interrupt status & mask register defines */
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#define SDMMC_INT_SDIO(n) BIT(16 + (n))
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#define SDMMC_INT_EBE BIT(15)
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#define SDMMC_INT_ACD BIT(14)
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#define SDMMC_INT_SBE BIT(13)
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#define SDMMC_INT_HLE BIT(12)
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#define SDMMC_INT_FRUN BIT(11)
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#define SDMMC_INT_HTO BIT(10)
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#define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
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#define SDMMC_INT_DRTO BIT(9)
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#define SDMMC_INT_RTO BIT(8)
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#define SDMMC_INT_DCRC BIT(7)
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#define SDMMC_INT_RCRC BIT(6)
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#define SDMMC_INT_RXDR BIT(5)
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#define SDMMC_INT_TXDR BIT(4)
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#define SDMMC_INT_DATA_OVER BIT(3)
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#define SDMMC_INT_CMD_DONE BIT(2)
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#define SDMMC_INT_RESP_ERR BIT(1)
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#define SDMMC_INT_CD BIT(0)
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#define SDMMC_INT_ERROR 0xbfc2
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/* Command register defines */
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#define SDMMC_CMD_START BIT(31)
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#define SDMMC_CMD_USE_HOLD_REG BIT(29)
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#define SDMMC_CMD_VOLT_SWITCH BIT(28)
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#define SDMMC_CMD_CCS_EXP BIT(23)
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#define SDMMC_CMD_CEATA_RD BIT(22)
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#define SDMMC_CMD_UPD_CLK BIT(21)
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#define SDMMC_CMD_INIT BIT(15)
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#define SDMMC_CMD_STOP BIT(14)
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#define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
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#define SDMMC_CMD_SEND_STOP BIT(12)
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#define SDMMC_CMD_STRM_MODE BIT(11)
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#define SDMMC_CMD_DAT_WR BIT(10)
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#define SDMMC_CMD_DAT_EXP BIT(9)
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#define SDMMC_CMD_RESP_CRC BIT(8)
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#define SDMMC_CMD_RESP_LONG BIT(7)
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#define SDMMC_CMD_RESP_EXP BIT(6)
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#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
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/* Status register defines */
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#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
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#define SDMMC_STATUS_DMA_REQ BIT(31)
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#define SDMMC_STATUS_BUSY BIT(9)
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/* FIFOTH register defines */
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#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
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((r) & 0xFFF) << 16 | \
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((t) & 0xFFF))
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#define SDMMC_FIFOTH_DMA_MULTI_TRANS_SIZE 28
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#define SDMMC_FIFOTH_RX_WMARK 16
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/* HCON register defines */
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#define DMA_INTERFACE_IDMA (0x0)
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#define DMA_INTERFACE_DWDMA (0x1)
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#define DMA_INTERFACE_GDMA (0x2)
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#define DMA_INTERFACE_NODMA (0x3)
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#define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
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#define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
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#define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
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#define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
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/* Internal DMAC interrupt defines */
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#define SDMMC_IDMAC_INT_AI BIT(9)
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#define SDMMC_IDMAC_INT_NI BIT(8)
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#define SDMMC_IDMAC_INT_CES BIT(5)
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#define SDMMC_IDMAC_INT_DU BIT(4)
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#define SDMMC_IDMAC_INT_FBE BIT(2)
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#define SDMMC_IDMAC_INT_RI BIT(1)
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#define SDMMC_IDMAC_INT_TI BIT(0)
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/* Internal DMAC bus mode bits */
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#define SDMMC_IDMAC_ENABLE BIT(7)
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#define SDMMC_IDMAC_FB BIT(1)
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#define SDMMC_IDMAC_SWRESET BIT(0)
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/* Version ID register define */
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#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
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/* Card read threshold */
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#define SDMMC_SET_RD_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
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#define SDMMC_UHS_18V BIT(0)
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/* All ctrl reset bits */
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#define SDMMC_CTRL_ALL_RESET_FLAGS \
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(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
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/* FIFO register access macros. These should not change the data endian-ness
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* as they are written to memory to be dealt with by the upper layers */
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#define mci_fifo_readw(__reg) __raw_readw(__reg)
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#define mci_fifo_readl(__reg) __raw_readl(__reg)
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#ifdef CONFIG_MMC_DW_FORCE_32BIT_SFR_RW
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#define mci_fifo_readq(__reg) ({\
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u64 __ret = 0;\
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u32* ptr = (u32*)&__ret;\
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*ptr++ = __raw_readl(__reg);\
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*ptr = __raw_readl(__reg + 0x4);\
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__ret;\
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})
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#define mci_fifo_writeq(__reg, value) ({\
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u32 *ptr = (u32*)&(value);\
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__raw_writel(*ptr++, __reg);\
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__raw_writel(*ptr, __reg + 0x4);\
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})
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#else
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#define mci_fifo_readq(__reg) __raw_readq(__reg)
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#define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
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#endif /* CONFIG_MMC_DW_FORCE_32BIT_SFR_RW */
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#define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
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#define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
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/* Register access macros */
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#define mci_readl(dev, reg) \
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readl_relaxed((dev)->regs + SDMMC_##reg)
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#define mci_writel(dev, reg, value) \
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writel_relaxed((value), (dev)->regs + SDMMC_##reg)
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/* timeout */
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#define dw_mci_set_timeout(host, value) mci_writel(host, TMOUT, value)
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/* 16-bit FIFO access macros */
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#define mci_readw(dev, reg) \
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readw_relaxed((dev)->regs + SDMMC_##reg)
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#define mci_writew(dev, reg, value) \
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writew_relaxed((value), (dev)->regs + SDMMC_##reg)
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/* 64-bit FIFO access macros */
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#ifdef readq
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#ifdef CONFIG_MMC_DW_FORCE_32BIT_SFR_RW
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#define mci_readq(dev, reg) ({\
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u64 __ret = 0;\
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u32* ptr = (u32*)&__ret;\
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*ptr++ = __raw_readl((dev)->regs + SDMMC_##reg);\
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*ptr = __raw_readl((dev)->regs + SDMMC_##reg + 0x4);\
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__ret;\
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})
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#define mci_writeq(dev, reg, value) ({\
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u32 *ptr = (u32*)&(value);\
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__raw_writel(*ptr++, (dev)->regs + SDMMC_##reg);\
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__raw_writel(*ptr, (dev)->regs + SDMMC_##reg + 0x4);\
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})
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#else
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#define mci_readq(dev, reg) \
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readq_relaxed((dev)->regs + SDMMC_##reg)
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#define mci_writeq(dev, reg, value) \
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writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
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#endif /* CONFIG_MMC_DW_FORCE_32BIT_SFR_RW */
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#else
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/*
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* Dummy readq implementation for architectures that don't define it.
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*
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* We would assume that none of these architectures would configure
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* the IP block with a 64bit FIFO width, so this code will never be
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* executed on those machines. Defining these macros here keeps the
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* rest of the code free from ifdefs.
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*/
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#define mci_readq(dev, reg) \
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(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
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#define mci_writeq(dev, reg, value) \
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(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
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#define __raw_writeq(__value, __reg) \
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(*(volatile u64 __force *)(__reg) = (__value))
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#define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
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#endif
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/*
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* platform-dependent miscellaneous control
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*
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* Input arguments for platform-dependent control may be different
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* for each one, respectively. If we would add functions like them
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* whenever we need to do that, this common header file(dw_mmc.h)
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* will be modified so frequently.
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* The following enumeration type is to minimize an amount of changes
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* of common files.
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*/
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enum dw_mci_misc_control {
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CTRL_RESTORE_CLKSEL = 0,
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CTRL_REQUEST_EXT_IRQ,
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CTRL_CHECK_CD,
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CTRL_ADD_SYSFS,
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};
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#define SDMMC_DATA_TMOUT_SHIFT 11
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#define SDMMC_RESP_TMOUT 0xFF
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#define SDMMC_DATA_TMOUT_CRT 8
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#define SDMMC_DATA_TMOUT_EXT 0x1
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#define SDMMC_DATA_TMOUT_EXT_SHIFT 8
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#define SDMMC_DATA_TMOUT_MAX_CNT 0x1FFFFF
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#define SDMMC_DATA_TMOUT_MAX_EXT_CNT 0xFFFFFF
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#define SDMMC_HTO_TMOUT_SHIFT 8
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extern u32 dw_mci_calc_timeout(struct dw_mci *host);
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extern int dw_mci_probe(struct dw_mci *host, struct platform_device *pdev);
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extern void dw_mci_remove(struct dw_mci *host);
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#ifdef CONFIG_PM_SLEEP
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extern int dw_mci_suspend(struct dw_mci *host);
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extern int dw_mci_resume(struct dw_mci *host);
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#endif
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/**
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* struct dw_mci_slot - MMC slot state
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* @mmc: The mmc_host representing this slot.
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* @host: The MMC controller this slot is using.
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* @ctype: Card type for this slot.
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* @mrq: mmc_request currently being processed or waiting to be
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* processed, or NULL when the slot is idle.
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* @queue_node: List node for placing this node in the @queue list of
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* &struct dw_mci.
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* @clock: Clock rate configured by set_ios(). Protected by host->lock.
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* @__clk_old: The last clock value that was requested from core.
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* Keeping track of this helps us to avoid spamming the console.
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* @flags: Random state bits associated with the slot.
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* @id: Number of this slot.
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* @sdio_id: Number of this slot in the SDIO interrupt registers.
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* @last_detect_state: Most recently observed card detect state.
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*/
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struct dw_mci_slot {
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struct mmc_host *mmc;
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struct dw_mci *host;
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int quirks;
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u32 ctype;
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struct mmc_request *mrq;
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struct list_head queue_node;
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unsigned int clock;
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unsigned int __clk_old;
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unsigned long flags;
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#define DW_MMC_CARD_PRESENT 0
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#define DW_MMC_CARD_NEED_INIT 1
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#define DW_MMC_CARD_NO_LOW_PWR 2
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int id;
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int sdio_id;
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int last_detect_state;
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};
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/**
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* struct dw_mci_debug_data - DwMMC debugging infomation
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* @host_count: a number of all hosts
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* @info_count: a number of set of debugging information
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* @info_index: index of debugging information for each host
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* @host: pointer of each dw_mci structure
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* @debug_info: debugging information structure
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*/
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struct dw_mci_cmd_log {
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u64 send_time;
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u64 done_time;
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u8 cmd;
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u32 arg;
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u8 data_size;
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/* no data CMD = CD, data CMD = DTO */
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/*
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* 0b1000 0000 : new_cmd with without send_cmd
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* 0b0000 1000 : error occurs
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* 0b0000 0100 : data_done : DTO(Data Transfer Over)
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* 0b0000 0010 : resp : CD(Command Done)
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* 0b0000 0001 : send_cmd : set 1 only start_command
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*/
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u8 seq_status; /* 0bxxxx xxxx : error data_done resp send */
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#define DW_MCI_FLAG_SEND_CMD BIT(0)
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#define DW_MCI_FLAG_CD BIT(1)
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#define DW_MCI_FLAG_DTO BIT(2)
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#define DW_MCI_FLAG_ERROR BIT(3)
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#define DW_MCI_FLAG_NEW_CMD_ERR BIT(7)
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u16 rint_sts; /* RINTSTS value in case of error */
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u8 status_count; /* TBD : It can be changed */
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};
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#define NUM_OF_CQ_LOG_CTX 5
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struct dw_mci_cq_cmd_log {
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u64 send_time;
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u64 done_time;
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/*
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* context to be stored
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*
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* idx 0 - tag
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* idx 1 - doorbell
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*/
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u32 data1[NUM_OF_CQ_LOG_CTX];
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u32 data2[NUM_OF_CQ_LOG_CTX];
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};
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enum dw_mci_req_log_state {
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STATE_REQ_START = 0,
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STATE_REQ_CMD_PROCESS,
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STATE_REQ_DATA_PROCESS,
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STATE_REQ_END,
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};
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struct dw_mci_req_log {
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u64 timestamp;
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u32 info0;
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u32 info1;
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u32 info2;
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u32 info3;
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unsigned long pending_events;
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unsigned long completed_events;
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enum dw_mci_state state;
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enum dw_mci_state state_cmd;
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enum dw_mci_state state_dat;
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enum dw_mci_req_log_state log_state;
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};
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#define DWMCI_LOG_MAX 0x80
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#define DWMCI_REQ_LOG_MAX 0x40
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struct dw_mci_debug_info {
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struct dw_mci_cmd_log cmd_log[DWMCI_LOG_MAX];
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atomic_t cmd_log_count;
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struct dw_mci_cq_cmd_log cq_cmd_log[DWMCI_LOG_MAX];
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atomic_t cq_cmd_log_count;
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struct dw_mci_req_log req_log[DWMCI_REQ_LOG_MAX];
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atomic_t req_log_count;
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unsigned char en_logging;
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#define DW_MCI_DEBUG_ON_CMD BIT(0)
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#define DW_MCI_DEBUG_ON_REQ BIT(1)
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};
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#define DWMCI_DBG_NUM_HOST 3
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#define DWMCI_DBG_NUM_INFO 3 /* configurable */
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#define DWMCI_DBG_MASK_INFO (BIT(0) | BIT(1) | BIT(2)) /* configurable */
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#define DWMCI_DBG_BIT_HOST(x) BIT(x)
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struct dw_mci_debug_data {
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unsigned char host_count;
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unsigned char info_count;
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unsigned char info_index[DWMCI_DBG_NUM_HOST];
|
|
struct dw_mci *host[DWMCI_DBG_NUM_HOST];
|
|
struct dw_mci_debug_info debug_info[DWMCI_DBG_NUM_INFO];
|
|
};
|
|
|
|
struct dw_mci_tuning_data {
|
|
const u8 *blk_pattern;
|
|
unsigned int blksz;
|
|
};
|
|
|
|
/**
|
|
* dw_mci driver data - dw-mshc implementation specific driver data.
|
|
* @caps: mmc subsystem specified capabilities of the controller(s).
|
|
* @init: early implementation specific initialization.
|
|
* @setup_clock: implementation specific clock configuration.
|
|
* @prepare_command: handle CMD register extensions.
|
|
* @set_ios: handle bus specific extensions.
|
|
* @parse_dt: parse implementation specific device tree properties.
|
|
* @execute_tuning: implementation specific tuning procedure.
|
|
*
|
|
* Provide controller implementation specific extensions. The usage of this
|
|
* data structure is fully optional and usage of each member in this structure
|
|
* is optional as well.
|
|
*/
|
|
struct dw_mci_drv_data {
|
|
unsigned long *caps;
|
|
int (*init)(struct dw_mci *host);
|
|
int (*setup_clock)(struct dw_mci *host);
|
|
void (*prepare_command)(struct dw_mci *host, u32 *cmdr);
|
|
void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
|
|
int (*parse_dt)(struct dw_mci *host);
|
|
int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode,
|
|
struct dw_mci_tuning_data *tuning_data);
|
|
int (*prepare_hs400_tuning)(struct dw_mci *host,
|
|
struct mmc_ios *ios);
|
|
int (*switch_voltage)(struct mmc_host *mmc,
|
|
struct mmc_ios *ios);
|
|
void (*hwacg_control)(struct dw_mci *host, u32 flag, int mode);
|
|
int (*misc_control)(struct dw_mci *host,
|
|
enum dw_mci_misc_control control, void *priv);
|
|
int (*crypto_engine_cfg)(struct dw_mci *host,
|
|
void *desc,
|
|
struct mmc_data *data,
|
|
struct page *page,
|
|
int sector_offset,
|
|
bool cmdq_enabled);
|
|
int (*crypto_engine_clear)(struct dw_mci *host, void *desc,
|
|
bool cmdq_enabled);
|
|
int (*access_control_get_dev)(struct dw_mci *host);
|
|
int (*access_control_sec_cfg)(struct dw_mci *host);
|
|
int (*access_control_init)(struct dw_mci *host);
|
|
int (*access_control_abort)(struct dw_mci *host);
|
|
int (*access_control_resume)(struct dw_mci *host);
|
|
};
|
|
|
|
struct dw_mci_sfe_ram_dump {
|
|
u32 contrl;
|
|
u32 pwren;
|
|
u32 clkdiv;
|
|
u32 clkena;
|
|
u32 clksrc;
|
|
u32 tmout;
|
|
u32 ctype;
|
|
u32 blksiz;
|
|
u32 bytcnt;
|
|
u32 intmask;
|
|
u32 cmdarg;
|
|
u32 cmd;
|
|
u32 mintsts;
|
|
u32 rintsts;
|
|
u32 status;
|
|
u32 fifoth;
|
|
u32 tcbcnt;
|
|
u32 tbbcnt;
|
|
u32 debnce;
|
|
u32 uhs_reg;
|
|
u32 bmod;
|
|
u32 pldmnd;
|
|
u32 dbaddrl;
|
|
u32 dbaddru;
|
|
u32 dscaddrl;
|
|
u32 dscaddru;
|
|
u32 bufaddru;
|
|
u32 dbaddr;
|
|
u32 dscaddr;
|
|
u32 bufaddr;
|
|
u32 clksel;
|
|
u32 idsts64;
|
|
u32 idinten64;
|
|
u32 force_clk_stop;
|
|
u32 cdthrctl;
|
|
u32 hs400_rdqs_en;
|
|
u32 hs400_acync_fifo_ctrl;
|
|
u32 hs400_dline_ctrl;
|
|
u32 fmp_emmcp_base;
|
|
u32 mpsecurity;
|
|
u32 mpstat;
|
|
u32 mpsbegin;
|
|
u32 mpsend;
|
|
u32 mpsctrl;
|
|
u32 cmd_status;
|
|
u32 data_status;
|
|
unsigned long pending_events;
|
|
unsigned long completed_events;
|
|
u32 host_state;
|
|
u32 cmd_index;
|
|
u32 fifo_count;
|
|
u32 data_busy;
|
|
u32 data_3_state;
|
|
u32 fifo_tx_watermark;
|
|
u32 fifo_rx_watermark;
|
|
u32 sha_cmd_ie;
|
|
u32 sha_cmd_is;
|
|
};
|
|
#endif /* _DW_MMC_H_ */
|