370 lines
11 KiB
C
370 lines
11 KiB
C
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/*
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* s2mu205-irq.c - Interrupt controller support for s2mu205
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*
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* Copyright (C) 2018 Samsung Electronics Co.Ltd
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/gpio.h>
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#include <linux/mfd/samsung/s2mu205.h>
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#include <linux/err.h>
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/* TODO : add IP Header file include*/
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#if defined(CONFIG_CHARGER_S2MU205)
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#include "../battery_v2/include/charger/s2mu205_charger.h"
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#endif
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#if defined(CONFIG_MUIC_S2MU205)
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#include <linux/muic/s2mu205-muic.h>
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#endif
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#if defined(CONFIG_LEDS_S2MU205_FLASH)
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#include <linux/leds-s2mu205.h>
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#endif
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#define S2MU205_IRQ_GROUP_MAX
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static const u8 s2mu205_mask_reg[] = {
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#if defined(CONFIG_CHARGER_S2MU205)
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[CHG_INT1] = S2MU205_CHG_INT1M,
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[CHG_INT2] = S2MU205_CHG_INT2M,
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[CHG_INT3] = S2MU205_CHG_INT3M,
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#endif
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#if defined(CONFIG_LEDS_S2MU205_FLASH)
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[FLED_INT1] = S2MU205_FLED_INT1_MASK,
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#endif
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#if defined(CONFIG_MUIC_S2MU205)
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[MUIC_INT1] = S2MU205_REG_MUIC_INT1,
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[MUIC_INT2] = S2MU205_REG_MUIC_INT2,
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#endif
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};
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struct s2mu205_irq_data {
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int mask;
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enum s2mu205_irq_source group;
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};
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static struct i2c_client *get_i2c(struct s2mu205_dev *s2mu205,
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enum s2mu205_irq_source src)
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{
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switch (src) {
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#if defined(CONFIG_CHARGER_S2MU205)
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case CHG_INT1 ... CHG_INT3:
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return s2mu205->i2c;
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#endif
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#if defined(CONFIG_LEDS_S2MU205_FLASH)
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case FLED_INT1:
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return s2mu205->i2c;
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#endif
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#if defined(CONFIG_MUIC_S2MU205)
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case MUIC_INT1 ... MUIC_INT2:
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return s2mu205->muic;
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#endif
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default:
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return ERR_PTR(-EINVAL);
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}
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}
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#define DECLARE_IRQ(idx, _group, _mask) \
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[(idx)] = { .group = (_group), .mask = (_mask) }
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static const struct s2mu205_irq_data s2mu205_irqs[] = {
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#if defined(CONFIG_CHARGER_S2MU205)
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DECLARE_IRQ(S2MU205_CHG1_IRQ_SYS, CHG_INT1, 1 << 0),
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DECLARE_IRQ(S2MU205_CHG1_IRQ_CV, CHG_INT1, 1 << 1),
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DECLARE_IRQ(S2MU205_CHG1_IRQ_CHG_Fault, CHG_INT1, 1 << 2),
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DECLARE_IRQ(S2MU205_CHG1_IRQ_CHG_RSTART, CHG_INT1, 1 << 3),
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DECLARE_IRQ(S2MU205_CHG1_IRQ_DONE, CHG_INT1, 1 << 4),
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DECLARE_IRQ(S2MU205_CHG1_IRQ_TOP_OFF, CHG_INT1, 1 << 5),
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DECLARE_IRQ(S2MU205_CHG1_IRQ_CHGIN, CHG_INT1, 1 << 6),
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DECLARE_IRQ(S2MU205_CHG2_IRQ_ICR, CHG_INT2, 1 << 0),
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DECLARE_IRQ(S2MU205_CHG2_IRQ_IVR, CHG_INT2, 1 << 1),
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DECLARE_IRQ(S2MU205_CHG2_IRQ_AICL, CHG_INT2, 1 << 2),
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DECLARE_IRQ(S2MU205_CHG2_IRQ_VBUS_Short, CHG_INT2, 1 << 3),
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DECLARE_IRQ(S2MU205_CHG2_IRQ_BST, CHG_INT2, 1 << 4),
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DECLARE_IRQ(S2MU205_CHG2_IRQ_OTG, CHG_INT2, 1 << 5),
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DECLARE_IRQ(S2MU205_CHG2_IRQ_BAT, CHG_INT2, 1 << 6),
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DECLARE_IRQ(S2MU205_CHG2_IRQ_MaxDuty, CHG_INT2, 1 << 7),
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DECLARE_IRQ(S2MU205_CHG3_IRQ_BATID, CHG_INT3, 1 << 0),
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DECLARE_IRQ(S2MU205_CHG3_IRQ_BATID_DONE, CHG_INT3, 1 << 1),
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DECLARE_IRQ(S2MU205_CHG3_IRQ_QBAT_OFF, CHG_INT3, 1 << 2),
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DECLARE_IRQ(S2MU205_CHG3_IRQ_BATN_OPEN, CHG_INT3, 1 << 4),
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DECLARE_IRQ(S2MU205_CHG3_IRQ_BATP_OPEN, CHG_INT3, 1 << 5),
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DECLARE_IRQ(S2MU205_CHG3_IRQ_BAT_Contact_CK_Done, CHG_INT3, 1 << 6),
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#endif
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#if defined(CONFIG_LEDS_S2MU205_FLASH)
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DECLARE_IRQ(S2MU205_FLED1_IRQ_OPEN_CH2, FLED_INT1, 1 << 4),
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DECLARE_IRQ(S2MU205_FLED1_IRQ_OPEN_CH1, FLED_INT1, 1 << 5),
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DECLARE_IRQ(S2MU205_FLED1_IRQ_SHORT_CH2, FLED_INT1, 1 << 6),
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DECLARE_IRQ(S2MU205_FLED1_IRQ_SHORT_CH1, FLED_INT1, 1 << 7),
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#endif
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#if defined(CONFIG_MUIC_S2MU205)
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/* declare order is priority : DETACH -> ATTACH */
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DECLARE_IRQ(S2MU205_MUIC_IRQ1_DETACH, MUIC_INT1, 1 << 1),
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DECLARE_IRQ(S2MU205_MUIC_IRQ1_ATTACH, MUIC_INT1, 1 << 0),
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DECLARE_IRQ(S2MU205_MUIC_IRQ1_KP, MUIC_INT1, 1 << 2),
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DECLARE_IRQ(S2MU205_MUIC_IRQ1_LKP, MUIC_INT1, 1 << 3),
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DECLARE_IRQ(S2MU205_MUIC_IRQ1_LKR, MUIC_INT1, 1 << 4),
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DECLARE_IRQ(S2MU205_MUIC_IRQ1_RID_CHG, MUIC_INT1, 1 << 5),
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DECLARE_IRQ(S2MU205_MUIC_IRQ1_USB_Killer, MUIC_INT1, 1 << 6),
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DECLARE_IRQ(S2MU205_MUIC_IRQ1_RID_WAKEUP, MUIC_INT1, 1 << 7),
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DECLARE_IRQ(S2MU205_MUIC_IRQ2_VBUS_ON, MUIC_INT2, 1 << 0),
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DECLARE_IRQ(S2MU205_MUIC_IRQ2_RSVD_ATTACH, MUIC_INT2, 1 << 1),
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DECLARE_IRQ(S2MU205_MUIC_IRQ2_ADC_CHANGE, MUIC_INT2, 1 << 2),
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DECLARE_IRQ(S2MU205_MUIC_IRQ2_STUCK, MUIC_INT2, 1 << 3),
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DECLARE_IRQ(S2MU205_MUIC_IRQ2_STUCKRCV, MUIC_INT2, 1 << 4),
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DECLARE_IRQ(S2MU205_MUIC_IRQ2_MHDL, MUIC_INT2, 1 << 5),
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DECLARE_IRQ(S2MU205_MUIC_IRQ2_AV_CHARGE, MUIC_INT2, 1 << 6),
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DECLARE_IRQ(S2MU205_MUIC_IRQ2_VBUS_OFF, MUIC_INT2, 1 << 7),
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#endif
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};
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static void s2mu205_irq_lock(struct irq_data *data)
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{
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struct s2mu205_dev *s2mu205 = irq_get_chip_data(data->irq);
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mutex_lock(&s2mu205->irqlock);
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}
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static void s2mu205_irq_sync_unlock(struct irq_data *data)
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{
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struct s2mu205_dev *s2mu205 = irq_get_chip_data(data->irq);
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int i;
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u8 mask_reg;
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struct i2c_client *i2c;
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for (i = 0; i < S2MU205_IRQ_GROUP_NR; i++) {
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mask_reg = s2mu205_mask_reg[i];
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i2c = get_i2c(s2mu205, i);
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if (mask_reg == S2MU205_REG_INVALID ||
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IS_ERR_OR_NULL(i2c))
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continue;
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s2mu205->irq_masks_cache[i] = s2mu205->irq_masks_cur[i];
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s2mu205_write_reg(i2c, s2mu205_mask_reg[i],
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s2mu205->irq_masks_cur[i]);
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}
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mutex_unlock(&s2mu205->irqlock);
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}
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static const inline struct s2mu205_irq_data *
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irq_to_s2mu205_irq(struct s2mu205_dev *s2mu205, int irq)
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{
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return &s2mu205_irqs[irq - s2mu205->irq_base];
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}
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static void s2mu205_irq_mask(struct irq_data *data)
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{
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struct s2mu205_dev *s2mu205 = irq_get_chip_data(data->irq);
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const struct s2mu205_irq_data *irq_data =
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irq_to_s2mu205_irq(s2mu205, data->irq);
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if (irq_data->group >= S2MU205_IRQ_GROUP_NR)
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return;
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s2mu205->irq_masks_cur[irq_data->group] |= irq_data->mask;
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}
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static void s2mu205_irq_unmask(struct irq_data *data)
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{
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struct s2mu205_dev *s2mu205 = irq_get_chip_data(data->irq);
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const struct s2mu205_irq_data *irq_data =
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irq_to_s2mu205_irq(s2mu205, data->irq);
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if (irq_data->group >= S2MU205_IRQ_GROUP_NR)
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return;
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s2mu205->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
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}
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static struct irq_chip s2mu205_irq_chip = {
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.name = MFD_DEV_NAME,
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.irq_bus_lock = s2mu205_irq_lock,
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.irq_bus_sync_unlock = s2mu205_irq_sync_unlock,
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.irq_mask = s2mu205_irq_mask,
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.irq_unmask = s2mu205_irq_unmask,
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};
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static irqreturn_t s2mu205_irq_thread(int irq, void *data)
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{
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struct s2mu205_dev *s2mu205 = data;
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u8 irq_reg[S2MU205_IRQ_GROUP_NR] = {0, };
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int i, ret;
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u8 irq_src;
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ret = s2mu205_read_reg(s2mu205->i2c, S2MU205_REG_IPINT, &irq_src);
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if (ret) {
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pr_err("%s:%s Failed to read interrupt source: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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pr_info("%s: Top interrupt(0x%02x)\n", __func__, irq_src);
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#if defined(CONFIG_CHARGER_S2MU205)
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if (irq_src & S2MU205_IRQSRC_CHG) {
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ret = s2mu205_bulk_read(s2mu205->i2c, S2MU205_CHG_INT1,
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S2MU205_NUM_IRQ_CHG_REGS, &irq_reg[CHG_INT1]);
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if (ret) {
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pr_err("%s:%s Failed to read charger interrupt: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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pr_info("%s() CHARGER intrrupt(0x%02x, 0x%02x, 0x%02x)\n",
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__func__, irq_reg[CHG_INT1], irq_reg[CHG_INT2],
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irq_reg[CHG_INT3]);
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}
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#endif
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#if defined(CONFIG_LEDS_S2MU205_FLASH)
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if (irq_src & S2MU205_IRQSRC_FLED) {
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ret = s2mu205_read_reg(s2mu205->i2c, S2MU205_FLED_INT1,
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&irq_reg[FLED_INT1]);
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if (ret) {
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pr_err("%s:%s Failed to read led interrupt: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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pr_info("%s() FLED intrrupt(0x%02x)\n", __func__, irq_reg[FLED_INT1]);
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}
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#endif
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#if defined(CONFIG_MUIC_S2MU205)
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if (irq_src & S2MU205_IRQSRC_MUIC) {
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s2mu205_read_reg(s2mu205->muic, S2MU205_REG_MUIC_INT1, &irq_reg[MUIC_INT1]);
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s2mu205_read_reg(s2mu205->muic, S2MU205_REG_MUIC_INT2, &irq_reg[MUIC_INT2]);
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pr_info("%s: MUIC interrupt(0x%02x, 0x%02x)\n", __func__, irq_reg[MUIC_INT1],
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irq_reg[MUIC_INT2]);
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}
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#endif
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/* Apply masking */
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for (i = 0; i < S2MU205_IRQ_GROUP_NR; i++)
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irq_reg[i] &= ~s2mu205->irq_masks_cur[i];
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/* Report */
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for (i = 0; i < S2MU205_IRQ_NR; i++) {
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if (irq_reg[s2mu205_irqs[i].group] & s2mu205_irqs[i].mask)
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handle_nested_irq(s2mu205->irq_base + i);
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}
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return IRQ_HANDLED;
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}
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static int irq_is_enable = true;
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int s2mu205_irq_init(struct s2mu205_dev *s2mu205)
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{
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int i;
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int ret;
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struct i2c_client *i2c = s2mu205->i2c;
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int cur_irq;
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u8 i2c_data;
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if (!s2mu205->irq_gpio) {
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dev_warn(s2mu205->dev, "No interrupt specified.\n");
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s2mu205->irq_base = 0;
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return 0;
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}
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if (!s2mu205->irq_base) {
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dev_err(s2mu205->dev, "No interrupt base specified.\n");
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return 0;
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}
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mutex_init(&s2mu205->irqlock);
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s2mu205->irq = gpio_to_irq(s2mu205->irq_gpio);
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pr_err("%s:%s irq=%d, irq->gpio=%d\n", MFD_DEV_NAME, __func__,
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s2mu205->irq, s2mu205->irq_gpio);
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ret = gpio_request(s2mu205->irq_gpio, "if_pmic_irq");
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if (ret) {
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dev_err(s2mu205->dev, "%s: failed requesting gpio %d\n",
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__func__, s2mu205->irq_gpio);
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return ret;
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}
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gpio_direction_input(s2mu205->irq_gpio);
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gpio_free(s2mu205->irq_gpio);
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/* Mask individual interrupt sources */
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for (i = 0; i < S2MU205_IRQ_GROUP_NR; i++) {
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|
|
||
|
|
s2mu205->irq_masks_cur[i] = 0xff;
|
||
|
|
s2mu205->irq_masks_cache[i] = 0xff;
|
||
|
|
i2c = get_i2c(s2mu205, i);
|
||
|
|
|
||
|
|
if (IS_ERR_OR_NULL(i2c))
|
||
|
|
continue;
|
||
|
|
if (s2mu205_mask_reg[i] == S2MU205_REG_INVALID)
|
||
|
|
continue;
|
||
|
|
s2mu205_write_reg(i2c, s2mu205_mask_reg[i], 0xff);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Register with genirq */
|
||
|
|
for (i = 0; i < S2MU205_IRQ_NR; i++) {
|
||
|
|
cur_irq = 0;
|
||
|
|
cur_irq = i + s2mu205->irq_base;
|
||
|
|
irq_set_chip_data(cur_irq, s2mu205);
|
||
|
|
irq_set_chip_and_handler(cur_irq, &s2mu205_irq_chip,
|
||
|
|
handle_level_irq);
|
||
|
|
irq_set_nested_thread(cur_irq, 1);
|
||
|
|
#ifdef CONFIG_ARM
|
||
|
|
set_irq_flags(cur_irq, IRQF_VALID);
|
||
|
|
#else
|
||
|
|
irq_set_noprobe(cur_irq);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Unmask S2MU205 interrupt */
|
||
|
|
i2c_data = 0xff;
|
||
|
|
#if defined(CONFIG_CHARGER_S2MU205)
|
||
|
|
i2c_data &= ~(S2MU205_IRQSRC_CHG);
|
||
|
|
#endif
|
||
|
|
#if defined(CONFIG_LEDS_S2MU205_FLASH)
|
||
|
|
i2c_data &= ~(S2MU205_IRQSRC_FLED);
|
||
|
|
#endif
|
||
|
|
#if defined(CONFIG_MUIC_S2MU205)
|
||
|
|
i2c_data &= ~(S2MU205_IRQSRC_MUIC);
|
||
|
|
#endif
|
||
|
|
s2mu205_write_reg(s2mu205->i2c, S2MU205_REG_IPINT_MASK, i2c_data);
|
||
|
|
pr_info("%s: %s init top-irq mask(0x%02x)\n", MFD_DEV_NAME, __func__, i2c_data);
|
||
|
|
pr_info("%s: irq gpio pre-state(0x%02x)\n", __func__,
|
||
|
|
gpio_get_value(s2mu205->irq_gpio));
|
||
|
|
|
||
|
|
if (irq_is_enable) {
|
||
|
|
ret = request_threaded_irq(s2mu205->irq, NULL,
|
||
|
|
s2mu205_irq_thread,
|
||
|
|
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
|
||
|
|
"s2mu205-irq", s2mu205);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
dev_err(s2mu205->dev, "Failed to request IRQ %d: %d\n",
|
||
|
|
s2mu205->irq, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void s2mu205_irq_exit(struct s2mu205_dev *s2mu205)
|
||
|
|
{
|
||
|
|
if (s2mu205->irq)
|
||
|
|
free_irq(s2mu205->irq, s2mu205);
|
||
|
|
}
|