25708 lines
858 KiB
Plaintext
25708 lines
858 KiB
Plaintext
/dts-v1/;
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/ {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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model = "Samsung A71 PROJECT Rev0.6 (board-id,06)";
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compatible = "qcom,sdmmagpie-idp\0qcom,sdmmagpie\0qcom,idp";
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qcom,msm-id = <0x16d 0x00>;
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qcom,msm-name = "SDMMAGPIE";
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interrupt-parent = <0x01>;
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qcom,pmic-name = "PM6150";
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qcom,board-id = <0x22 0x06>;
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cpus {
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#address-cells = <0x02>;
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#size-cells = <0x00>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x00>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x400>;
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sched-energy-costs = <0x02 0x03>;
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next-level-cache = <0x04>;
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qcom,lmh-dcvs = <0x05>;
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#cooling-cells = <0x02>;
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phandle = <0x11>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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next-level-cache = <0x06>;
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phandle = <0x04>;
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l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x03>;
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phandle = <0x06>;
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};
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};
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l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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phandle = <0x35>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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phandle = <0x3d>;
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};
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l2-tlb {
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qcom,dump-size = <0x5000>;
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phandle = <0x49>;
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};
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x400>;
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sched-energy-costs = <0x02 0x03>;
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next-level-cache = <0x07>;
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qcom,lmh-dcvs = <0x05>;
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#cooling-cells = <0x02>;
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phandle = <0x12>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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next-level-cache = <0x06>;
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phandle = <0x07>;
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};
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l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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phandle = <0x36>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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phandle = <0x3e>;
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};
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l2-tlb {
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qcom,dump-size = <0x5000>;
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phandle = <0x4a>;
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};
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x200>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x400>;
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sched-energy-costs = <0x02 0x03>;
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next-level-cache = <0x08>;
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qcom,lmh-dcvs = <0x05>;
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#cooling-cells = <0x02>;
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phandle = <0x13>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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next-level-cache = <0x06>;
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phandle = <0x08>;
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};
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l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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phandle = <0x37>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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phandle = <0x3f>;
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};
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l2-tlb {
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qcom,dump-size = <0x5000>;
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phandle = <0x4b>;
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};
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x300>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x400>;
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sched-energy-costs = <0x02 0x03>;
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next-level-cache = <0x09>;
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qcom,lmh-dcvs = <0x05>;
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#cooling-cells = <0x02>;
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phandle = <0x14>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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next-level-cache = <0x06>;
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phandle = <0x09>;
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};
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l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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phandle = <0x38>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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phandle = <0x40>;
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};
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l2-tlb {
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qcom,dump-size = <0x5000>;
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phandle = <0x4c>;
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};
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};
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cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x400>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x400>;
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sched-energy-costs = <0x02 0x03>;
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next-level-cache = <0x0a>;
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qcom,lmh-dcvs = <0x05>;
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#cooling-cells = <0x02>;
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phandle = <0x15>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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next-level-cache = <0x06>;
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phandle = <0x0a>;
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};
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l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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phandle = <0x39>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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phandle = <0x41>;
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};
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l2-tlb {
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qcom,dump-size = <0x5000>;
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phandle = <0x4d>;
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};
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};
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cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x500>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x400>;
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sched-energy-costs = <0x02 0x03>;
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next-level-cache = <0x0b>;
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qcom,lmh-dcvs = <0x05>;
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#cooling-cells = <0x02>;
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phandle = <0x16>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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next-level-cache = <0x06>;
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phandle = <0x0b>;
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};
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l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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phandle = <0x3a>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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phandle = <0x42>;
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};
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l2-tlb {
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qcom,dump-size = <0x5000>;
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phandle = <0x4e>;
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};
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};
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cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x600>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x6cc>;
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sched-energy-costs = <0x0c 0x0d>;
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next-level-cache = <0x0e>;
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qcom,lmh-dcvs = <0x0f>;
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#cooling-cells = <0x02>;
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phandle = <0x17>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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next-level-cache = <0x06>;
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qcom,dump-size = <0x48000>;
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phandle = <0x0e>;
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};
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l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x11000>;
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phandle = <0x3b>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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phandle = <0x43>;
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};
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l1-itlb {
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qcom,dump-size = <0x300>;
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phandle = <0x45>;
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};
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l1-dtlb {
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qcom,dump-size = <0x480>;
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phandle = <0x47>;
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};
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l2-tlb {
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qcom,dump-size = <0x7800>;
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phandle = <0x4f>;
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};
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};
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cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x700>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x6cc>;
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sched-energy-costs = <0x0c 0x0d>;
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next-level-cache = <0x10>;
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qcom,lmh-dcvs = <0x0f>;
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#cooling-cells = <0x02>;
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phandle = <0x18>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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next-level-cache = <0x06>;
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qcom,dump-size = <0x48000>;
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phandle = <0x10>;
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};
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l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x11000>;
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phandle = <0x3c>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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phandle = <0x44>;
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};
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l1-itlb {
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qcom,dump-size = <0x300>;
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phandle = <0x46>;
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};
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l1-dtlb {
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qcom,dump-size = <0x480>;
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phandle = <0x48>;
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};
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l2-tlb {
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qcom,dump-size = <0x7800>;
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phandle = <0x50>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x11>;
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};
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core1 {
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cpu = <0x12>;
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};
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core2 {
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cpu = <0x13>;
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};
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core3 {
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cpu = <0x14>;
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};
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core4 {
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cpu = <0x15>;
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};
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core5 {
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cpu = <0x16>;
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};
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};
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cluster1 {
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core0 {
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cpu = <0x17>;
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};
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core1 {
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cpu = <0x18>;
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};
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};
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};
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};
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soc {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x00 0xffffffff>;
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compatible = "simple-bus";
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phandle = <0x2a0>;
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sec_hw_param {
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param0 = <0x01 0x03>;
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};
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jtagmm@7040000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x7040000 0x1000>;
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reg-names = "etm-base";
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clocks = <0x19 0x00>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <0x11>;
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phandle = <0x2a1>;
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};
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jtagmm@7140000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x7140000 0x1000>;
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reg-names = "etm-base";
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clocks = <0x19 0x00>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <0x12>;
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phandle = <0x2a2>;
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};
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jtagmm@7240000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x7240000 0x1000>;
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reg-names = "etm-base";
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clocks = <0x19 0x00>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <0x13>;
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phandle = <0x2a3>;
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};
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jtagmm@7340000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x7340000 0x1000>;
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reg-names = "etm-base";
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clocks = <0x19 0x00>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <0x14>;
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phandle = <0x2a4>;
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};
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jtagmm@7440000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x7440000 0x1000>;
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reg-names = "etm-base";
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clocks = <0x19 0x00>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <0x15>;
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phandle = <0x2a5>;
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};
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jtagmm@7540000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x7540000 0x1000>;
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reg-names = "etm-base";
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clocks = <0x19 0x00>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <0x16>;
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phandle = <0x2a6>;
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};
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jtagmm@7640000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x7640000 0x1000>;
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reg-names = "etm-base";
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clocks = <0x19 0x00>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <0x17>;
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phandle = <0x2a7>;
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};
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jtagmm@7740000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x7740000 0x1000>;
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reg-names = "etm-base";
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clocks = <0x19 0x00>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <0x18>;
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phandle = <0x2a8>;
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};
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interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <0x03>;
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interrupt-controller;
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#redistributor-regions = <0x01>;
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redistributor-stride = <0x00 0x20000>;
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reg = <0x17a00000 0x10000 0x17a60000 0x100000>;
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interrupts = <0x01 0x09 0x04>;
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interrupt-parent = <0x1a>;
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phandle = <0x1a>;
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};
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interrupt-controller@b220000 {
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compatible = "qcom,pdc-sdmmagpie";
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reg = <0xb220000 0x400>;
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#interrupt-cells = <0x03>;
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interrupt-parent = <0x1a>;
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interrupt-controller;
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phandle = <0x01>;
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};
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qcom,memshare {
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compatible = "qcom,memshare";
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qcom,client_1 {
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compatible = "qcom,memshare-peripheral";
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qcom,peripheral-size = <0x00>;
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qcom,client-id = <0x00>;
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qcom,allocate-boot-time;
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label = "modem";
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};
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qcom,client_2 {
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compatible = "qcom,memshare-peripheral";
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qcom,peripheral-size = <0x00>;
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qcom,client-id = <0x02>;
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label = "modem";
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};
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qcom,client_3 {
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compatible = "qcom,memshare-peripheral";
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qcom,peripheral-size = <0x500000>;
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qcom,client-id = <0x01>;
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qcom,allocate-on-request;
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label = "modem";
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phandle = <0x2a9>;
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};
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qcom,client_4 {
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compatible = "qcom,memshare-peripheral";
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memory-region = <0x530>;
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qcom,peripheral-size = <0x2000000>;
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qcom,reserved-size = <0x4000000>;
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qcom,client-id = <0x03>;
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qcom,allocate-boot-time;
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label = "modem";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <0x01 0x01 0xf08 0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x00 0xf08>;
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clock-frequency = <0x124f800>;
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};
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timer@0x17c20000 {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17c20000 0x1000>;
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clock-frequency = <0x124f800>;
|
|
|
|
frame@0x17c21000 {
|
|
frame-number = <0x00>;
|
|
interrupts = <0x00 0x08 0x04 0x00 0x06 0x04>;
|
|
reg = <0x17c21000 0x1000 0x17c22000 0x1000>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
frame-number = <0x01>;
|
|
interrupts = <0x00 0x09 0x04>;
|
|
reg = <0x17c23000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
frame-number = <0x02>;
|
|
interrupts = <0x00 0x0a 0x04>;
|
|
reg = <0x17c25000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
frame-number = <0x03>;
|
|
interrupts = <0x00 0x0b 0x04>;
|
|
reg = <0x17c27000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
frame-number = <0x04>;
|
|
interrupts = <0x00 0x0c 0x04>;
|
|
reg = <0x17c29000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <0x05>;
|
|
interrupts = <0x00 0x0d 0x04>;
|
|
reg = <0x17c2b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <0x06>;
|
|
interrupts = <0x00 0x0e 0x04>;
|
|
reg = <0x17c2d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
|
|
sleep-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x7d00>;
|
|
clock-output-names = "chip_sleep_clk";
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x2aa>;
|
|
};
|
|
};
|
|
|
|
qcom,rpmh {
|
|
compatible = "qcom,rpmh-clk-sdmmagpie";
|
|
mboxes = <0x1b 0x00>;
|
|
mbox-names = "apps";
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x2f>;
|
|
};
|
|
|
|
qcom,aopclk {
|
|
compatible = "qcom,aop-qmp-clk";
|
|
#clock-cells = <0x01>;
|
|
mboxes = <0x1c 0x00>;
|
|
mbox-names = "qdss_clk";
|
|
phandle = <0x19>;
|
|
};
|
|
|
|
qcom,gcc@100000 {
|
|
compatible = "qcom,gcc-sdmmagpie\0syscon";
|
|
vdd_cx-supply = <0x1d>;
|
|
vdd_cx_ao-supply = <0x1e>;
|
|
reg = <0x100000 0x1f0000>;
|
|
reg-names = "cc_base";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x27>;
|
|
};
|
|
|
|
qcom,camcc {
|
|
compatible = "qcom,camcc-sdmmagpie\0syscon";
|
|
vdd_cx-supply = <0x1d>;
|
|
vdd_mx-supply = <0x1f>;
|
|
reg = <0xad00000 0x10000>;
|
|
reg-names = "cc_base";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x29>;
|
|
};
|
|
|
|
qcom,gpucc {
|
|
compatible = "qcom,gpucc-sdmmagpie\0syscon";
|
|
reg = <0x5090000 0x9000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <0x1d>;
|
|
vdd_mx-supply = <0x1f>;
|
|
vdd_gfx-supply = <0x20>;
|
|
qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <0x21>;
|
|
qcom,gpu_cc_gmu_clk_src-opp-handle = <0x22>;
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x2b>;
|
|
};
|
|
|
|
qcom,videocc@ab00000 {
|
|
compatible = "qcom,videocc-sdmmagpie\0syscon";
|
|
vdd_cx-supply = <0x1d>;
|
|
reg = <0xab00000 0x10000 0x786018 0x04>;
|
|
reg-names = "cc_base\0efuse";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x28>;
|
|
};
|
|
|
|
qcom,dispcc@af00000 {
|
|
compatible = "qcom,dispcc-sdmmagpie\0syscon";
|
|
vdd_cx-supply = <0x1d>;
|
|
reg = <0xaf00000 0x20000>;
|
|
reg-names = "cc_base";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x2a>;
|
|
};
|
|
|
|
qcom,npucc {
|
|
compatible = "qcom,npucc-sdmmagpie\0syscon";
|
|
reg = <0x9910000 0x10000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <0x1d>;
|
|
npu_gdsc-supply = <0x23>;
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x2c>;
|
|
};
|
|
|
|
qcom,cpucc@18321000 {
|
|
compatible = "qcom,clk-cpu-osm-sdmmagpie";
|
|
reg = <0x18321000 0x1400 0x18323000 0x1400 0x18325800 0x1400>;
|
|
reg-names = "osm_l3_base\0osm_pwrcl_base\0osm_perfcl_base";
|
|
l3-devs = <0x24 0x25 0x26>;
|
|
#clock-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
phandle = <0xb8>;
|
|
|
|
qcom,limits-dcvs@18358800 {
|
|
compatible = "qcom,msm-hw-limits";
|
|
interrupts = <0x00 0x20 0x04>;
|
|
qcom,affinity = <0x00>;
|
|
reg = <0x18358800 0x1000 0x18323000 0x1000>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x05>;
|
|
};
|
|
|
|
qcom,limits-dcvs@18350800 {
|
|
compatible = "qcom,msm-hw-limits";
|
|
interrupts = <0x00 0x21 0x04>;
|
|
qcom,affinity = <0x01>;
|
|
reg = <0x18350800 0x1000 0x18325800 0x1000>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x0f>;
|
|
};
|
|
};
|
|
|
|
syscon@182a0018 {
|
|
compatible = "syscon";
|
|
reg = <0x182a0018 0x04>;
|
|
phandle = <0x2d>;
|
|
};
|
|
|
|
syscon@90b0000 {
|
|
compatible = "syscon";
|
|
reg = <0x90b0000 0x1000>;
|
|
phandle = <0x2e>;
|
|
};
|
|
|
|
qcom,cc-debug {
|
|
compatible = "qcom,debugcc-sdmmagpie";
|
|
qcom,cc-count = <0x08>;
|
|
qcom,gcc = <0x27>;
|
|
qcom,videocc = <0x28>;
|
|
qcom,camcc = <0x29>;
|
|
qcom,dispcc = <0x2a>;
|
|
qcom,gpucc = <0x2b>;
|
|
qcom,npucc = <0x2c>;
|
|
qcom,cpucc = <0x2d>;
|
|
qcom,mccc = <0x2e>;
|
|
clocks = <0x2f 0x00>;
|
|
clock-names = "xo_clk_src";
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x2ab>;
|
|
};
|
|
|
|
qcom,sps {
|
|
compatible = "qcom,msm-sps-4k";
|
|
qcom,pipe-attr-ee;
|
|
};
|
|
|
|
cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
qcom,irq-is-percpu;
|
|
interrupts = <0x01 0x05 0x04>;
|
|
phandle = <0x2ac>;
|
|
};
|
|
|
|
dsu_pmu@0 {
|
|
compatible = "arm,dsu-pmu";
|
|
interrupts = <0x00 0x32 0x04>;
|
|
cpus = <0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18>;
|
|
};
|
|
|
|
qcom,msm-imem@146aa000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x146aa000 0x1000>;
|
|
ranges = <0x00 0x146aa000 0x1000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x08>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x04>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x04>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0x0c>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,msm-imem-pil";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
|
|
upload_cause@66c {
|
|
compatible = "qcom,msm-imem-upload_cause";
|
|
reg = <0x66c 0x04>;
|
|
};
|
|
};
|
|
|
|
restart@c264000 {
|
|
compatible = "qcom,pshold";
|
|
reg = <0xc264000 0x04 0x1fd3000 0x04>;
|
|
reg-names = "pshold-base\0tcsr-boot-misc-detect";
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@0xc221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <0x8000>;
|
|
};
|
|
|
|
aop-msg-client {
|
|
compatible = "qcom,debugfs-qmp-client";
|
|
mboxes = <0x1c 0x00>;
|
|
mbox-names = "aop";
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
qcom,gpi-dma@0x800000 {
|
|
#dma-cells = <0x05>;
|
|
compatible = "qcom,gpi-dma";
|
|
reg = <0x800000 0x60000>;
|
|
reg-names = "gpi-top";
|
|
interrupts = <0x00 0xf4 0x00 0x00 0xf5 0x00 0x00 0xf6 0x00 0x00 0xf7 0x00 0x00 0xf8 0x00 0x00 0xf9 0x00 0x00 0xfa 0x00 0x00 0xfb 0x00>;
|
|
qcom,max-num-gpii = <0x08>;
|
|
qcom,gpii-mask = <0x0f>;
|
|
qcom,ev-factor = <0x02>;
|
|
iommus = <0x30 0x216 0x00>;
|
|
qcom,smmu-cfg = <0x01>;
|
|
qcom,iova-range = <0x00 0x100000 0x00 0x100000>;
|
|
status = "ok";
|
|
phandle = <0x15d>;
|
|
};
|
|
|
|
qcom,gpi-dma@0xa00000 {
|
|
#dma-cells = <0x05>;
|
|
compatible = "qcom,gpi-dma";
|
|
reg = <0xa00000 0x60000>;
|
|
reg-names = "gpi-top";
|
|
interrupts = <0x00 0x117 0x00 0x00 0x118 0x00 0x00 0x119 0x00 0x00 0x11a 0x00 0x00 0x11b 0x00 0x00 0x11c 0x00 0x00 0x125 0x00 0x00 0x126 0x00>;
|
|
qcom,max-num-gpii = <0x08>;
|
|
qcom,gpii-mask = <0x0f>;
|
|
qcom,ev-factor = <0x02>;
|
|
iommus = <0x30 0x4d6 0x00>;
|
|
qcom,smmu-cfg = <0x01>;
|
|
qcom,iova-range = <0x00 0x100000 0x00 0x100000>;
|
|
status = "ok";
|
|
phandle = <0x17b>;
|
|
};
|
|
|
|
bt_wcn3990 {
|
|
compatible = "qca,wcn3990";
|
|
qca,bt-vdd-io-supply = <0x31>;
|
|
qca,bt-vdd-core-supply = <0x32>;
|
|
qca,bt-vdd-pa-supply = <0x33>;
|
|
qca,bt-vdd-xtal-supply = <0x34>;
|
|
qca,bt-vdd-io-voltage-level = <0x19f0a0 0x1cfde0>;
|
|
qca,bt-vdd-core-voltage-level = <0x12ff48 0x149970>;
|
|
qca,bt-vdd-pa-voltage-level = <0x30d400 0x33e140>;
|
|
qca,bt-vdd-xtal-voltage-level = <0x19f0a0 0x1cfde0>;
|
|
qca,bt-vdd-io-current-level = <0x01>;
|
|
qca,bt-vdd-core-current-level = <0x01>;
|
|
qca,bt-vdd-pa-current-level = <0x01>;
|
|
qca,bt-vdd-xtal-current-level = <0x01>;
|
|
phandle = <0x2ad>;
|
|
};
|
|
|
|
slim@62dc0000 {
|
|
cell-index = <0x01>;
|
|
compatible = "qcom,slim-ngd";
|
|
reg = <0x62dc0000 0x2c000 0x62d84000 0x2a000>;
|
|
reg-names = "slimbus_physical\0slimbus_bam_physical";
|
|
interrupts = <0x00 0xa3 0x00 0x00 0xa4 0x00>;
|
|
interrupt-names = "slimbus_irq\0slimbus_bam_irq";
|
|
qcom,apps-ch-pipes = <0x7c0000>;
|
|
qcom,ea-pc = <0x300>;
|
|
status = "disabled";
|
|
qcom,iommu-s1-bypass;
|
|
phandle = <0x2ae>;
|
|
|
|
qcom,iommu_slim_ctrl_cb {
|
|
compatible = "qcom,iommu-slim-ctrl-cb";
|
|
iommus = <0x30 0x1be6 0x08 0x30 0x1bed 0x02 0x30 0x1bf0 0x01>;
|
|
phandle = <0x2af>;
|
|
};
|
|
|
|
msm_dai_slim {
|
|
status = "disabled";
|
|
compatible = "qcom,msm-dai-slim";
|
|
elemental-addr = [ff ff ff fe 17 02];
|
|
phandle = <0x2b0>;
|
|
};
|
|
|
|
tavil_codec {
|
|
status = "disabled";
|
|
compatible = "qcom,tavil-slim-pgd";
|
|
elemental-addr = [00 01 50 02 17 02];
|
|
interrupt-parent = <0x52c>;
|
|
interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>;
|
|
qcom,wcd-rst-gpio-node = <0x52d>;
|
|
clock-names = "wcd_clk";
|
|
clocks = <0x52e 0x00>;
|
|
cdc-vdd-buck-supply = <0x52f>;
|
|
qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>;
|
|
qcom,cdc-vdd-buck-current = <0x91050>;
|
|
cdc-buck-sido-supply = <0x52f>;
|
|
qcom,cdc-buck-sido-voltage = <0x1b7740 0x1b7740>;
|
|
qcom,cdc-buck-sido-current = <0x7a120>;
|
|
cdc-vdd-tx-h-supply = <0x52f>;
|
|
qcom,cdc-vdd-tx-h-voltage = <0x1b7740 0x1b7740>;
|
|
qcom,cdc-vdd-tx-h-current = <0x61a8>;
|
|
cdc-vdd-rx-h-supply = <0x52f>;
|
|
qcom,cdc-vdd-rx-h-voltage = <0x1b7740 0x1b7740>;
|
|
qcom,cdc-vdd-rx-h-current = <0x61a8>;
|
|
cdc-vddpx-1-supply = <0x52f>;
|
|
qcom,cdc-vddpx-1-voltage = <0x1b7740 0x1b7740>;
|
|
qcom,cdc-vddpx-1-current = <0x2710>;
|
|
cdc-vdd-mic-bias-supply = <0x3fc>;
|
|
qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K";
|
|
qcom,cdc-vdd-mic-bias-current = <0x76c0 0xf4241>;
|
|
qcom,cdc-static-supplies = "cdc-vdd-buck\0cdc-buck-sido\0cdc-vdd-tx-h\0cdc-vdd-rx-h\0cdc-vddpx-1";
|
|
qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";
|
|
qcom,cdc-micbias1-mv = <0x708>;
|
|
qcom,cdc-micbias2-mv = <0x708>;
|
|
qcom,cdc-micbias3-mv = <0x708>;
|
|
qcom,cdc-micbias4-mv = <0x708>;
|
|
qcom,cdc-mclk-clk-rate = <0x927c00>;
|
|
qcom,cdc-slim-ifd = "tavil-slim-ifd";
|
|
qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02];
|
|
qcom,cdc-dmic-sample-rate = "\0I>";
|
|
qcom,cdc-mad-dmic-rate = <0x927c0>;
|
|
qcom,wdsp-cmpnt-dev-name = "tavil_codec";
|
|
qcom,vreg-micb-supply = <0x3fc>;
|
|
phandle = <0x52a>;
|
|
|
|
wcd_spi {
|
|
compatible = "qcom,wcd-spi-v2";
|
|
qcom,master-bus-num = <0x00>;
|
|
qcom,chip-select = <0x00>;
|
|
qcom,max-frequency = <0x16e3600>;
|
|
qcom,mem-base-addr = <0x100000>;
|
|
phandle = <0x52b>;
|
|
};
|
|
};
|
|
};
|
|
|
|
slim@62e40000 {
|
|
cell-index = <0x03>;
|
|
compatible = "qcom,slim-ngd";
|
|
reg = <0x62e40000 0x2c000 0x62e04000 0x20000>;
|
|
reg-names = "slimbus_physical\0slimbus_bam_physical";
|
|
interrupts = <0x00 0x123 0x00 0x00 0x124 0x00>;
|
|
interrupt-names = "slimbus_irq\0slimbus_bam_irq";
|
|
status = "ok";
|
|
qcom,iommu-s1-bypass;
|
|
phandle = <0x2b1>;
|
|
|
|
qcom,iommu_slim_ctrl_cb {
|
|
compatible = "qcom,iommu-slim-ctrl-cb";
|
|
iommus = <0x30 0x1bf3 0x00>;
|
|
phandle = <0x2b2>;
|
|
};
|
|
|
|
wcn3990 {
|
|
compatible = "qcom,btfmslim_slave";
|
|
elemental-addr = [00 01 20 02 17 02];
|
|
qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
|
|
qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
|
|
phandle = <0x2b3>;
|
|
};
|
|
};
|
|
|
|
qcom,wdt@17c10000 {
|
|
compatible = "qcom,msm-watchdog";
|
|
reg = <0x17c10000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <0x00 0x00 0x00 0x00 0x01 0x00>;
|
|
qcom,bark-time = <0x2af8>;
|
|
qcom,pet-time = <0x2490>;
|
|
qcom,ipi-ping;
|
|
qcom,wakeup-enable;
|
|
qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100 0x10100 0x10100 0x25900 0x25900>;
|
|
phandle = <0x2b4>;
|
|
};
|
|
|
|
qcom,msm-eud@88e0000 {
|
|
compatible = "qcom,msm-eud";
|
|
interrupt-names = "eud_irq";
|
|
interrupts = <0x00 0x1ec 0x04>;
|
|
reg = <0x88e0000 0x2000 0x88e4000 0x1000>;
|
|
reg-names = "eud_base\0eud_mode_mgr2";
|
|
qcom,secure-eud-en;
|
|
qcom,eud-clock-vote-req;
|
|
clocks = <0x27 0x97>;
|
|
clock-names = "eud_ahb2phy_clk";
|
|
status = "ok";
|
|
phandle = <0x254>;
|
|
};
|
|
|
|
qcom,chd_sliver {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "silver";
|
|
qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058 0x18040058 0x18050058>;
|
|
qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060 0x18040060 0x18050060>;
|
|
};
|
|
|
|
qcom,chd_gold {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "gold";
|
|
qcom,threshold-arr = <0x18060058 0x18070058>;
|
|
qcom,config-arr = <0x18060060 0x18070060>;
|
|
};
|
|
|
|
kryo-erp {
|
|
compatible = "arm,arm64-kryo-cpu-erp";
|
|
interrupts = <0x01 0x06 0x04 0x00 0x23 0x04>;
|
|
interrupt-names = "l1-l2-faultirq\0l3-scu-faultirq";
|
|
};
|
|
|
|
qcom,ghd {
|
|
compatible = "qcom,gladiator-hang-detect-v3";
|
|
qcom,threshold-arr = <0x17e0041c>;
|
|
qcom,config-reg = <0x17e00434>;
|
|
};
|
|
|
|
cpuss_dump {
|
|
compatible = "qcom,cpuss-dump";
|
|
|
|
qcom,l1_i_cache0 {
|
|
qcom,dump-node = <0x35>;
|
|
qcom,dump-id = <0x60>;
|
|
};
|
|
|
|
qcom,l1_i_cache100 {
|
|
qcom,dump-node = <0x36>;
|
|
qcom,dump-id = <0x61>;
|
|
};
|
|
|
|
qcom,l1_i_cache200 {
|
|
qcom,dump-node = <0x37>;
|
|
qcom,dump-id = <0x62>;
|
|
};
|
|
|
|
qcom,l1_i_cache300 {
|
|
qcom,dump-node = <0x38>;
|
|
qcom,dump-id = <0x63>;
|
|
};
|
|
|
|
qcom,l1_i_cache400 {
|
|
qcom,dump-node = <0x39>;
|
|
qcom,dump-id = <0x64>;
|
|
};
|
|
|
|
qcom,l1_i_cache500 {
|
|
qcom,dump-node = <0x3a>;
|
|
qcom,dump-id = <0x65>;
|
|
};
|
|
|
|
qcom,l1_i_cache600 {
|
|
qcom,dump-node = <0x3b>;
|
|
qcom,dump-id = <0x66>;
|
|
};
|
|
|
|
qcom,l1_i_cache700 {
|
|
qcom,dump-node = <0x3c>;
|
|
qcom,dump-id = <0x67>;
|
|
};
|
|
|
|
qcom,l1_d_cache0 {
|
|
qcom,dump-node = <0x3d>;
|
|
qcom,dump-id = <0x80>;
|
|
};
|
|
|
|
qcom,l1_d_cache100 {
|
|
qcom,dump-node = <0x3e>;
|
|
qcom,dump-id = <0x81>;
|
|
};
|
|
|
|
qcom,l1_d_cache200 {
|
|
qcom,dump-node = <0x3f>;
|
|
qcom,dump-id = <0x82>;
|
|
};
|
|
|
|
qcom,l1_d_cache300 {
|
|
qcom,dump-node = <0x40>;
|
|
qcom,dump-id = <0x83>;
|
|
};
|
|
|
|
qcom,l1_d_cache400 {
|
|
qcom,dump-node = <0x41>;
|
|
qcom,dump-id = <0x84>;
|
|
};
|
|
|
|
qcom,l1_d_cache500 {
|
|
qcom,dump-node = <0x42>;
|
|
qcom,dump-id = <0x85>;
|
|
};
|
|
|
|
qcom,l1_d_cache600 {
|
|
qcom,dump-node = <0x43>;
|
|
qcom,dump-id = <0x86>;
|
|
};
|
|
|
|
qcom,l1_d_cache700 {
|
|
qcom,dump-node = <0x44>;
|
|
qcom,dump-id = <0x87>;
|
|
};
|
|
|
|
qcom,l1_i_tlb_dump600 {
|
|
qcom,dump-node = <0x45>;
|
|
qcom,dump-id = <0x26>;
|
|
};
|
|
|
|
qcom,l1_i_tlb_dump700 {
|
|
qcom,dump-node = <0x46>;
|
|
qcom,dump-id = <0x27>;
|
|
};
|
|
|
|
qcom,l1_d_tlb_dump600 {
|
|
qcom,dump-node = <0x47>;
|
|
qcom,dump-id = <0x46>;
|
|
};
|
|
|
|
qcom,l1_d_tlb_dump700 {
|
|
qcom,dump-node = <0x48>;
|
|
qcom,dump-id = <0x47>;
|
|
};
|
|
|
|
qcom,l2_cache_dump600 {
|
|
qcom,dump-node = <0x0e>;
|
|
qcom,dump-id = <0xc6>;
|
|
};
|
|
|
|
qcom,l2_cache_dump700 {
|
|
qcom,dump-node = <0x10>;
|
|
qcom,dump-id = <0xc7>;
|
|
};
|
|
|
|
qcom,l2_tlb_dump0 {
|
|
qcom,dump-node = <0x49>;
|
|
qcom,dump-id = <0x120>;
|
|
};
|
|
|
|
qcom,l2_tlb_dump100 {
|
|
qcom,dump-node = <0x4a>;
|
|
qcom,dump-id = <0x121>;
|
|
};
|
|
|
|
qcom,l2_tlb_dump200 {
|
|
qcom,dump-node = <0x4b>;
|
|
qcom,dump-id = <0x122>;
|
|
};
|
|
|
|
qcom,l2_tlb_dump300 {
|
|
qcom,dump-node = <0x4c>;
|
|
qcom,dump-id = <0x123>;
|
|
};
|
|
|
|
qcom,l2_tlb_dump400 {
|
|
qcom,dump-node = <0x4d>;
|
|
qcom,dump-id = <0x124>;
|
|
};
|
|
|
|
qcom,l2_tlb_dump500 {
|
|
qcom,dump-node = <0x4e>;
|
|
qcom,dump-id = <0x125>;
|
|
};
|
|
|
|
qcom,l2_tlb_dump600 {
|
|
qcom,dump-node = <0x4f>;
|
|
qcom,dump-id = <0x126>;
|
|
};
|
|
|
|
qcom,l2_tlb_dump700 {
|
|
qcom,dump-node = <0x50>;
|
|
qcom,dump-id = <0x127>;
|
|
};
|
|
|
|
qcom,llcc1_d_cache {
|
|
qcom,dump-node = <0x51>;
|
|
qcom,dump-id = <0x140>;
|
|
};
|
|
|
|
qcom,llcc2_d_cache {
|
|
qcom,dump-node = <0x52>;
|
|
qcom,dump-id = <0x141>;
|
|
};
|
|
};
|
|
|
|
mem_dump {
|
|
compatible = "qcom,mem-dump";
|
|
memory-region = <0x53>;
|
|
|
|
rpmh {
|
|
qcom,dump-size = <0x2000000>;
|
|
qcom,dump-id = <0xec>;
|
|
};
|
|
|
|
rpm_sw {
|
|
qcom,dump-size = <0x28000>;
|
|
qcom,dump-id = <0xea>;
|
|
};
|
|
|
|
pmic {
|
|
qcom,dump-size = <0x10000>;
|
|
qcom,dump-id = <0xe4>;
|
|
};
|
|
|
|
fcm {
|
|
qcom,dump-size = <0x8400>;
|
|
qcom,dump-id = <0xee>;
|
|
};
|
|
|
|
tmc_etf {
|
|
qcom,dump-size = <0x10000>;
|
|
qcom,dump-id = <0xf0>;
|
|
};
|
|
|
|
etf_swao {
|
|
qcom,dump-size = <0x8400>;
|
|
qcom,dump-id = <0xf1>;
|
|
};
|
|
|
|
etr_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x100>;
|
|
};
|
|
|
|
etf_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x101>;
|
|
};
|
|
|
|
etfswao_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x102>;
|
|
};
|
|
|
|
misc_data {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0xe8>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
phandle = <0x2b5>;
|
|
|
|
pm6150-tz {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x54>;
|
|
wake-capable-sensor;
|
|
phandle = <0x2b6>;
|
|
disable-thermal-zone;
|
|
|
|
trips {
|
|
|
|
trip0 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
phandle = <0x2b7>;
|
|
};
|
|
|
|
trip1 {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
phandle = <0x2b8>;
|
|
};
|
|
|
|
trip2 {
|
|
temperature = <0x23668>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
trip0_bat {
|
|
trip = <0x2b7>;
|
|
cooling-device = <0x80 0xfffffffd 0xfffffffd>;
|
|
};
|
|
|
|
trip1_bat {
|
|
trip = <0x2b8>;
|
|
cooling-device = <0x80 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150-ibat-lvl0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x55 0x00>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
ibat-lvl0 {
|
|
temperature = <0x157c>;
|
|
hysteresis = <0xc8>;
|
|
type = "passive";
|
|
phandle = <0x2b9>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150-ibat-lvl1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x55 0x01>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
ibat-lvl1 {
|
|
temperature = <0x1770>;
|
|
hysteresis = <0xc8>;
|
|
type = "passive";
|
|
phandle = <0x2ba>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150-vbat-lvl0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "low_limits_cap";
|
|
thermal-sensors = <0x55 0x02>;
|
|
wake-capable-sensor;
|
|
tracks-low;
|
|
|
|
trips {
|
|
|
|
vbat-lvl0 {
|
|
temperature = <0xbb8>;
|
|
hysteresis = <0xc8>;
|
|
type = "passive";
|
|
phandle = <0x2bb>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150-vbat-lvl1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "low_limits_cap";
|
|
thermal-sensors = <0x55 0x03>;
|
|
wake-capable-sensor;
|
|
tracks-low;
|
|
|
|
trips {
|
|
|
|
vbat-lvl1 {
|
|
temperature = <0xaf0>;
|
|
hysteresis = <0xc8>;
|
|
type = "passive";
|
|
phandle = <0x2bc>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150-vbat-lvl2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "low_limits_cap";
|
|
thermal-sensors = <0x55 0x04>;
|
|
wake-capable-sensor;
|
|
tracks-low;
|
|
|
|
trips {
|
|
|
|
vbat-lvl2 {
|
|
temperature = <0xa28>;
|
|
hysteresis = <0xc8>;
|
|
type = "passive";
|
|
phandle = <0x2bd>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150-bcl-lvl0 {
|
|
disable-thermal-zone;
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x55 0x05>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
bcl-lvl0 {
|
|
temperature = <0x01>;
|
|
hysteresis = <0x01>;
|
|
type = "passive";
|
|
phandle = <0x2be>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
vbat_cpu6 {
|
|
trip = <0x2be>;
|
|
cooling-device = <0x17 0xfffffffe 0xfffffffe>;
|
|
};
|
|
|
|
vbat_cpu7 {
|
|
trip = <0x2be>;
|
|
cooling-device = <0x18 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150-bcl-lvl1 {
|
|
disable-thermal-zone;
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x55 0x06>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
bcl-lvl1 {
|
|
temperature = <0x01>;
|
|
hysteresis = <0x01>;
|
|
type = "passive";
|
|
phandle = <0x2bf>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
ibat_cpu6 {
|
|
trip = <0x2bf>;
|
|
cooling-device = <0x17 0xfffffffe 0xfffffffe>;
|
|
};
|
|
|
|
ibat_cpu7 {
|
|
trip = <0x2bf>;
|
|
cooling-device = <0x18 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150-bcl-lvl2 {
|
|
disable-thermal-zone;
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x55 0x07>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
bcl-lvl2 {
|
|
temperature = <0x01>;
|
|
hysteresis = <0x01>;
|
|
type = "passive";
|
|
phandle = <0x2c0>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
ibat_cpu6 {
|
|
trip = <0x2c0>;
|
|
cooling-device = <0x17 0xfffffffe 0xfffffffe>;
|
|
};
|
|
|
|
ibat_cpu7 {
|
|
trip = <0x2c0>;
|
|
cooling-device = <0x18 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
soc {
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "low_limits_cap";
|
|
thermal-sensors = <0x56>;
|
|
wake-capable-sensor;
|
|
tracks-low;
|
|
disable-thermal-zone;
|
|
|
|
trips {
|
|
|
|
soc-trip {
|
|
temperature = <0x0a>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
phandle = <0x2c1>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
soc_cpu6 {
|
|
trip = <0x2c1>;
|
|
cooling-device = <0x17 0xfffffffe 0xfffffffe>;
|
|
};
|
|
|
|
soc_cpu7 {
|
|
trip = <0x2c1>;
|
|
cooling-device = <0x18 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150l-tz {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x57>;
|
|
wake-capable-sensor;
|
|
phandle = <0x2c2>;
|
|
disable-thermal-zone;
|
|
|
|
trips {
|
|
|
|
trip0 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
phandle = <0x2c3>;
|
|
};
|
|
|
|
trip1 {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
phandle = <0x2c4>;
|
|
};
|
|
|
|
trip2 {
|
|
temperature = <0x23668>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
trip0_cpu0 {
|
|
trip = <0x2c3>;
|
|
cooling-device = <0x11 0xfffffffd 0xfffffffd>;
|
|
};
|
|
|
|
trip0_cpu1 {
|
|
trip = <0x2c3>;
|
|
cooling-device = <0x12 0xfffffffd 0xfffffffd>;
|
|
};
|
|
|
|
trip0_cpu2 {
|
|
trip = <0x2c3>;
|
|
cooling-device = <0x13 0xfffffffd 0xfffffffd>;
|
|
};
|
|
|
|
trip0_cpu3 {
|
|
trip = <0x2c3>;
|
|
cooling-device = <0x14 0xfffffffd 0xfffffffd>;
|
|
};
|
|
|
|
trip0_cpu4 {
|
|
trip = <0x2c3>;
|
|
cooling-device = <0x15 0xfffffffd 0xfffffffd>;
|
|
};
|
|
|
|
trip0_cpu5 {
|
|
trip = <0x2c3>;
|
|
cooling-device = <0x16 0xfffffffd 0xfffffffd>;
|
|
};
|
|
|
|
trip0_cpu6 {
|
|
trip = <0x2c3>;
|
|
cooling-device = <0x17 0xfffffffd 0xfffffffd>;
|
|
};
|
|
|
|
trip0_cpu7 {
|
|
trip = <0x2c3>;
|
|
cooling-device = <0x18 0xfffffffd 0xfffffffd>;
|
|
};
|
|
|
|
trip1_cpu1 {
|
|
trip = <0x2c4>;
|
|
cooling-device = <0x12 0xfffffffe 0xfffffffe>;
|
|
};
|
|
|
|
trip1_cpu2 {
|
|
trip = <0x2c4>;
|
|
cooling-device = <0x13 0xfffffffe 0xfffffffe>;
|
|
};
|
|
|
|
trip1_cpu3 {
|
|
trip = <0x2c4>;
|
|
cooling-device = <0x14 0xfffffffe 0xfffffffe>;
|
|
};
|
|
|
|
trip1_cpu4 {
|
|
trip = <0x2c4>;
|
|
cooling-device = <0x15 0xfffffffe 0xfffffffe>;
|
|
};
|
|
|
|
trip1_cpu5 {
|
|
trip = <0x2c4>;
|
|
cooling-device = <0x16 0xfffffffe 0xfffffffe>;
|
|
};
|
|
|
|
trip1_cpu6 {
|
|
trip = <0x2c4>;
|
|
cooling-device = <0x17 0xfffffffe 0xfffffffe>;
|
|
};
|
|
|
|
trip1_cpu7 {
|
|
trip = <0x2c4>;
|
|
cooling-device = <0x18 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150l-vph-lvl0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "low_limits_cap";
|
|
thermal-sensors = <0x58 0x02>;
|
|
wake-capable-sensor;
|
|
tracks-low;
|
|
|
|
trips {
|
|
|
|
vph-lvl0 {
|
|
temperature = <0xbb8>;
|
|
hysteresis = <0xc8>;
|
|
type = "passive";
|
|
phandle = <0x2c5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150l-vph-lvl1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "low_limits_cap";
|
|
thermal-sensors = <0x58 0x03>;
|
|
wake-capable-sensor;
|
|
tracks-low;
|
|
|
|
trips {
|
|
|
|
vph-lvl1 {
|
|
temperature = <0xabe>;
|
|
hysteresis = <0xc8>;
|
|
type = "passive";
|
|
phandle = <0x2c6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150l-vph-lvl2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "low_limits_cap";
|
|
thermal-sensors = <0x58 0x04>;
|
|
wake-capable-sensor;
|
|
tracks-low;
|
|
|
|
trips {
|
|
|
|
vph-lvl2 {
|
|
temperature = <0x9c4>;
|
|
hysteresis = <0xc8>;
|
|
type = "passive";
|
|
phandle = <0x2c7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150l-bcl-lvl0 {
|
|
disable-thermal-zone;
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x58 0x05>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
l-bcl-lvl0 {
|
|
temperature = <0x01>;
|
|
hysteresis = <0x01>;
|
|
type = "passive";
|
|
phandle = <0x2c8>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150l-bcl-lvl1 {
|
|
disable-thermal-zone;
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x58 0x06>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
l-bcl-lvl1 {
|
|
temperature = <0x01>;
|
|
hysteresis = <0x01>;
|
|
type = "passive";
|
|
phandle = <0x2c9>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm6150l-bcl-lvl2 {
|
|
disable-thermal-zone;
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x58 0x07>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
l-bcl-lvl2 {
|
|
temperature = <0x01>;
|
|
hysteresis = <0x01>;
|
|
type = "passive";
|
|
phandle = <0x2ca>;
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-0-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x59 0x00>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-0-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x59 0x01>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-1-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x59 0x02>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-2-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x59 0x03>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-3-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x04>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-4-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x05>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-5-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x06>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-0-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x07>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-1-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x08>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x09>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-1-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x0a>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-2-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x0b>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-3-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x0c>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-0-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x0d>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-1-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x59 0x0e>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-1-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x00>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cwlan-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x01>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
audio-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x02>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddr-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x03>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
q6-hvx-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x04>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
camera-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x05>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mdm-core-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x06>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mdm-dsp-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x07>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
npu-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x08>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
video-usr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x09>;
|
|
thermal-governor = "user_space";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
xo-therm-adc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x5b 0x4c>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
rf-pa0-therm-adc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x5b 0x4e>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
rf-pa1-therm-adc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x5b 0x4f>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
quiet-therm-adc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x5b 0x50>;
|
|
wake-capable-sensor;
|
|
status = "disabled";
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
conn-therm-adc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x5c 0x4d>;
|
|
wake-capable-sensor;
|
|
status = "disabled";
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
camera-ftherm-adc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x5c 0x4f>;
|
|
wake-capable-sensor;
|
|
status = "disabled";
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nvm-therm-adc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x5c 0x55>;
|
|
wake-capable-sensor;
|
|
status = "disabled";
|
|
|
|
trips {
|
|
|
|
active-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
lmh-dcvs-00 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x05>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config {
|
|
temperature = <0x14c08>;
|
|
hysteresis = <0x7530>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
lmh-dcvs-01 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <0x0f>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
active-config {
|
|
temperature = <0x14c08>;
|
|
hysteresis = <0x7530>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-max-step {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x64>;
|
|
thermal-governor = "step_wise";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
gpu-trip {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
phandle = <0x5d>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu_cdev {
|
|
trip = <0x5d>;
|
|
cooling-device = <0x21 0xffffffff 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-max-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
silver-trip {
|
|
temperature = <0x1d4c0>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-max-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
gold-trip {
|
|
temperature = <0x1d4c0>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-0-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x59 0x01>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
cpu0-config {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x5e>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu0_cdev {
|
|
trip = <0x5e>;
|
|
cooling-device = <0x11 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-1-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x59 0x02>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
cpu1-config {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x5f>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu1_cdev {
|
|
trip = <0x5f>;
|
|
cooling-device = <0x12 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-2-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x59 0x03>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
cpu2-config {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x60>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu2_cdev {
|
|
trip = <0x60>;
|
|
cooling-device = <0x13 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-3-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x59 0x04>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
cpu3-config {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x61>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu3_cdev {
|
|
trip = <0x61>;
|
|
cooling-device = <0x14 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-4-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x59 0x05>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
cpu4-config {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x62>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu4_cdev {
|
|
trip = <0x62>;
|
|
cooling-device = <0x15 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-5-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x59 0x06>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
cpu5-config {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x63>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu5_cdev {
|
|
trip = <0x63>;
|
|
cooling-device = <0x16 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x59 0x09>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
cpu6-0-config {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x64>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu6_cdev {
|
|
trip = <0x64>;
|
|
cooling-device = <0x17 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-1-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x59 0x0a>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
cpu6-1-config {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x65>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu6_cdev {
|
|
trip = <0x65>;
|
|
cooling-device = <0x17 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-2-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x59 0x0b>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
cpu7-0-config {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x66>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu7_cdev {
|
|
trip = <0x66>;
|
|
cooling-device = <0x18 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-3-step {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x59 0x0c>;
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
cpu7-1-config {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x67>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu7_cdev {
|
|
trip = <0x67>;
|
|
cooling-device = <0x18 0xfffffffe 0xfffffffe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-lowc {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "low_limits_cap";
|
|
thermal-sensors = <0x59 0x00>;
|
|
wake-capable-sensor;
|
|
tracks-low;
|
|
|
|
trips {
|
|
|
|
aoss-lowc {
|
|
temperature = <0x1388>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x68>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
audio_cdev {
|
|
trip = <0x68>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-lowf {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "low_limits_floor";
|
|
thermal-sensors = <0x59 0x09>;
|
|
wake-capable-sensor;
|
|
tracks-low;
|
|
|
|
trips {
|
|
|
|
cpu-1-0-trip {
|
|
temperature = <0x1388>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x69>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu0_cdev {
|
|
trip = <0x69>;
|
|
cooling-device = <0x11 0x02 0x02>;
|
|
};
|
|
|
|
cpu1_cdev {
|
|
trip = <0x69>;
|
|
cooling-device = <0x17 0x04 0x04>;
|
|
};
|
|
|
|
gpu_vdd_cdev {
|
|
trip = <0x69>;
|
|
cooling-device = <0x21 0xfffffffb 0xfffffffb>;
|
|
};
|
|
|
|
cx_vdd_cdev {
|
|
trip = <0x69>;
|
|
cooling-device = <0x6a 0x00 0x00>;
|
|
};
|
|
|
|
mx_vdd_cdev {
|
|
trip = <0x69>;
|
|
cooling-device = <0x6b 0x00 0x00>;
|
|
};
|
|
|
|
modem_vdd_cdev {
|
|
trip = <0x69>;
|
|
cooling-device = <0x6c 0x00 0x00>;
|
|
};
|
|
|
|
adsp_vdd_cdev {
|
|
trip = <0x69>;
|
|
cooling-device = <0x6d 0x00 0x00>;
|
|
};
|
|
|
|
cdsp_vdd_cdev {
|
|
trip = <0x69>;
|
|
cooling-device = <0x6e 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
npu-step {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x08>;
|
|
thermal-governor = "step_wise";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
npu-trip0 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
phandle = <0x6f>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
npu_cdev {
|
|
trip = <0x6f>;
|
|
cooling-device = <0x70 0xffffffff 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
q6-hvx-step {
|
|
polling-delay-passive = <0x0a>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x5a 0x04>;
|
|
thermal-governor = "step_wise";
|
|
wake-capable-sensor;
|
|
|
|
trips {
|
|
|
|
q6-hvx-trip0 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x4e20>;
|
|
type = "passive";
|
|
phandle = <0x71>;
|
|
};
|
|
|
|
q6-hvx-trip1 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
phandle = <0x73>;
|
|
};
|
|
|
|
q6-hvx-trip2 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x75>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cxip-cdev {
|
|
trip = <0x71>;
|
|
cooling-device = <0x72 0x01 0x01>;
|
|
};
|
|
|
|
cdsp-cdev0 {
|
|
trip = <0x73>;
|
|
cooling-device = <0x74 0xffffffff 0x04>;
|
|
};
|
|
|
|
cdsp-cdev1 {
|
|
trip = <0x75>;
|
|
cooling-device = <0x74 0x04 0x04>;
|
|
};
|
|
};
|
|
};
|
|
|
|
quiet-therm-step {
|
|
polling-delay-passive = <0x3e8>;
|
|
polling-delay = <0x00>;
|
|
thermal-governor = "step_wise";
|
|
thermal-sensors = <0x5b 0x50>;
|
|
wake-capable-sensor;
|
|
status = "disabled";
|
|
|
|
trips {
|
|
|
|
batt-trip0 {
|
|
temperature = <0xa7f8>;
|
|
hysteresis = <0xfa0>;
|
|
type = "passive";
|
|
phandle = <0x7f>;
|
|
};
|
|
|
|
batt-trip1 {
|
|
temperature = <0xafc8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0x81>;
|
|
};
|
|
|
|
batt-trip2 {
|
|
temperature = <0xb798>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0x82>;
|
|
};
|
|
|
|
modem-trip0 {
|
|
temperature = <0xbb80>;
|
|
hysteresis = <0xfa0>;
|
|
type = "passive";
|
|
phandle = <0x7d>;
|
|
};
|
|
|
|
batt-trip3 {
|
|
temperature = <0xbf68>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0x83>;
|
|
};
|
|
|
|
modem-trip1-hvx-trip {
|
|
temperature = <0xc350>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0x79>;
|
|
};
|
|
|
|
gold-trip {
|
|
temperature = <0xc350>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
phandle = <0x76>;
|
|
};
|
|
|
|
batt-trip4 {
|
|
temperature = <0xc738>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0x84>;
|
|
};
|
|
|
|
skin-gpu-trip {
|
|
temperature = <0xcb20>;
|
|
hysteresis = <0xfa0>;
|
|
type = "passive";
|
|
phandle = <0x78>;
|
|
};
|
|
|
|
modem-trip2 {
|
|
temperature = <0xcb20>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0x7b>;
|
|
};
|
|
|
|
silver-trip {
|
|
temperature = <0xd2f0>;
|
|
hysteresis = <0x00>;
|
|
type = "passive";
|
|
phandle = <0x77>;
|
|
};
|
|
|
|
modem-trip3 {
|
|
temperature = <0xe290>;
|
|
hysteresis = <0xfa0>;
|
|
type = "passive";
|
|
phandle = <0x7c>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
skin_cpu6 {
|
|
trip = <0x76>;
|
|
cooling-device = <0x17 0xffffffff 0xfffffff5>;
|
|
};
|
|
|
|
skin_cpu7 {
|
|
trip = <0x76>;
|
|
cooling-device = <0x18 0xffffffff 0xfffffff5>;
|
|
};
|
|
|
|
skin_cpu0 {
|
|
trip = <0x77>;
|
|
cooling-device = <0x11 0xffffffff 0xfffffff7>;
|
|
};
|
|
|
|
skin_cpu1 {
|
|
trip = <0x77>;
|
|
cooling-device = <0x12 0xffffffff 0xfffffff7>;
|
|
};
|
|
|
|
skin_cpu2 {
|
|
trip = <0x77>;
|
|
cooling-device = <0x13 0xffffffff 0xfffffff7>;
|
|
};
|
|
|
|
skin_cpu3 {
|
|
trip = <0x77>;
|
|
cooling-device = <0x14 0xffffffff 0xfffffff7>;
|
|
};
|
|
|
|
skin_cpu4 {
|
|
trip = <0x77>;
|
|
cooling-device = <0x15 0xffffffff 0xfffffff7>;
|
|
};
|
|
|
|
skin_cpu5 {
|
|
trip = <0x77>;
|
|
cooling-device = <0x16 0xffffffff 0xfffffff7>;
|
|
};
|
|
|
|
skin_gpu {
|
|
trip = <0x78>;
|
|
cooling-device = <0x21 0xfffffff9 0xfffffff9>;
|
|
};
|
|
|
|
modem_lvl1 {
|
|
trip = <0x79>;
|
|
cooling-device = <0x7a 0x01 0x01>;
|
|
};
|
|
|
|
modem_lvl2 {
|
|
trip = <0x7b>;
|
|
cooling-device = <0x7a 0x02 0x02>;
|
|
};
|
|
|
|
modem_lvl3 {
|
|
trip = <0x7c>;
|
|
cooling-device = <0x7a 0x03 0x03>;
|
|
};
|
|
|
|
modem_proc_lvl1 {
|
|
trip = <0x7d>;
|
|
cooling-device = <0x7e 0x01 0x01>;
|
|
};
|
|
|
|
modem_proc_lvl3 {
|
|
trip = <0x7c>;
|
|
cooling-device = <0x7e 0x03 0x03>;
|
|
};
|
|
|
|
cdsp_cdev1 {
|
|
trip = <0x79>;
|
|
cooling-device = <0x74 0x04 0x04>;
|
|
};
|
|
|
|
battery_lvl0 {
|
|
trip = <0x7f>;
|
|
cooling-device = <0x80 0x01 0x01>;
|
|
};
|
|
|
|
battery_lvl1 {
|
|
trip = <0x81>;
|
|
cooling-device = <0x80 0x02 0x02>;
|
|
};
|
|
|
|
battery_lvl2 {
|
|
trip = <0x82>;
|
|
cooling-device = <0x80 0x04 0x04>;
|
|
};
|
|
|
|
battery_lvl3 {
|
|
trip = <0x83>;
|
|
cooling-device = <0x80 0x05 0x05>;
|
|
};
|
|
|
|
battery_lvl4 {
|
|
trip = <0x84>;
|
|
cooling-device = <0x80 0x06 0x06>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tsens@c222000 {
|
|
compatible = "qcom,tsens24xx";
|
|
reg = <0xc222000 0x08 0xc263000 0x1ff>;
|
|
reg-names = "tsens_srot_physical\0tsens_tm_physical";
|
|
interrupts = <0x00 0x1fa 0x00 0x00 0x1fc 0x00>;
|
|
interrupt-names = "tsens-upper-lower\0tsens-critical";
|
|
tsens-reinit-wa;
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x59>;
|
|
};
|
|
|
|
tsens@c223000 {
|
|
compatible = "qcom,tsens24xx";
|
|
reg = <0xc223000 0x08 0xc265000 0x1ff>;
|
|
reg-names = "tsens_srot_physical\0tsens_tm_physical";
|
|
interrupts = <0x00 0x1fb 0x00 0x00 0x1fd 0x00>;
|
|
interrupt-names = "tsens-upper-lower\0tsens-critical";
|
|
tsens-reinit-wa;
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x5a>;
|
|
};
|
|
|
|
dcc_v2@10a2000 {
|
|
compatible = "qcom,dcc-v2";
|
|
reg = <0x10a2000 0x1000 0x10ae000 0x2000>;
|
|
reg-names = "dcc-base\0dcc-ram-base";
|
|
dcc-ram-offset = <0x6000>;
|
|
phandle = <0x2cb>;
|
|
qcom,curr-link-list = <0x03>;
|
|
qcom,link-list = <0x00 0x9680000 0x01 0x00 0x00 0x9680004 0x01 0x00 0x02 0x08 0x00 0x00 0x00 0x9681000 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9681004 0x01 0x00 0x00 0x9681008 0x01 0x00 0x00 0x968100c 0x01 0x00 0x00 0x9681010 0x01 0x00 0x00 0x9681014 0x01 0x00 0x00 0x968101c 0x01 0x00 0x00 0x9681020 0x01 0x00 0x00 0x9681024 0x01 0x00 0x00 0x9681028 0x01 0x00 0x00 0x968102c 0x01 0x00 0x00 0x9681030 0x01 0x00 0x00 0x9681034 0x01 0x00 0x00 0x968103c 0x01 0x00 0x00 0x9698100 0x01 0x00 0x00 0x9698104 0x01 0x00 0x00 0x9698108 0x01 0x00 0x00 0x9698110 0x01 0x00 0x00 0x9698120 0x01 0x00 0x00 0x9698124 0x01 0x00 0x00 0x9698128 0x01 0x00 0x00 0x969812c 0x01 0x00 0x00 0x9698130 0x01 0x00 0x00 0x9698134 0x01 0x00 0x00 0x9698138 0x01 0x00 0x00 0x969813c 0x01 0x00 0x00 0x9698500 0x01 0x00 0x00 0x9698504 0x01 0x00 0x00 0x9698508 0x01 0x00 0x00 0x969850c 0x01 0x00 0x00 0x9698510 0x01 0x00 0x00 0x9698514 0x01 0x00 0x00 0x9698518 0x01 0x00 0x00 0x969851c 0x01 0x00 0x00 0x9698700 0x01 0x00 0x00 0x9698704 0x01 0x00 0x00 0x9698708 0x01 0x00 0x00 0x969870c 0x01 0x00 0x00 0x9698714 0x01 0x00 0x00 0x9698718 0x01 0x00 0x00 0x969871c 0x01 0x00 0x00 0x1620204 0x01 0x00 0x00 0x1620240 0x01 0x00 0x00 0x1620248 0x01 0x00 0x00 0x1620288 0x01 0x00 0x00 0x162028c 0x01 0x00 0x00 0x1620290 0x01 0x00 0x00 0x1620294 0x01 0x00 0x00 0x16202a8 0x01 0x00 0x00 0x16202ac 0x01 0x00 0x00 0x16202b0 0x01 0x00 0x00 0x16202b4 0x01 0x00 0x00 0x1620300 0x01 0x00 0x00 0x1700204 0x01 0x00 0x00 0x1700240 0x01 0x00 0x00 0x1700248 0x01 0x00 0x00 0x1700288 0x01 0x00 0x00 0x1700290 0x01 0x00 0x00 0x1700300 0x01 0x00 0x00 0x1700304 0x01 0x00 0x00 0x1700308 0x01 0x00 0x00 0x170030c 0x01 0x00 0x00 0x1700310 0x01 0x00 0x00 0x1700314 0x01 0x00 0x00 0x1700c08 0x01 0x00 0x00 0x1700c10 0x01 0x00 0x00 0x1700c20 0x01 0x00 0x00 0x1700c24 0x01 0x00 0x00 0x1700c28 0x01 0x00 0x00 0x1700c2c 0x01 0x00 0x00 0x1700c30 0x01 0x00 0x00 0x1700c34 0x01 0x00 0x00 0x1700c38 0x01 0x00 0x00 0x1700c3c 0x01 0x00 0x00 0x1740240 0x01 0x00 0x00 0x1740248 0x01 0x00 0x00 0x1740288 0x01 0x00 0x00 0x1740290 0x01 0x00 0x00 0x1740300 0x01 0x00 0x00 0x1740304 0x01 0x00 0x00 0x1740308 0x01 0x00 0x00 0x174030c 0x01 0x00 0x00 0x1740310 0x01 0x00 0x00 0x1740314 0x01 0x00 0x00 0x1740004 0x01 0x00 0x00 0x1740008 0x01 0x00 0x00 0x1740010 0x01 0x00 0x00 0x1740020 0x01 0x00 0x00 0x1740024 0x01 0x00 0x00 0x1740028 0x01 0x00 0x00 0x174002c 0x01 0x00 0x00 0x1740030 0x01 0x00 0x00 0x1740034 0x01 0x00 0x00 0x1740038 0x01 0x00 0x00 0x174003c 0x01 0x00 0x00 0x9698204 0x01 0x00 0x00 0x9698240 0x01 0x00 0x00 0x9698244 0x01 0x00 0x00 0x9698248 0x01 0x00 0x00 0x969824c 0x01 0x00 0x00 0x9681010 0x01 0x00 0x00 0x9681014 0x01 0x00 0x00 0x9681018 0x01 0x00 0x00 0x968101c 0x01 0x00 0x00 0x9681020 0x01 0x00 0x00 0x9681024 0x01 0x00 0x00 0x9681028 0x01 0x00 0x00 0x968102c 0x01 0x00 0x00 0x9681030 0x01 0x00 0x00 0x9681034 0x01 0x00 0x00 0x968103c 0x01 0x00 0x00 0x9698100 0x01 0x00 0x00 0x9698104 0x01 0x00 0x00 0x9698108 0x01 0x00 0x00 0x9698110 0x01 0x00 0x00 0x9698120 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|
|
};
|
|
|
|
qcom,llcc@9200000 {
|
|
compatible = "qcom,llcc-core\0syscon\0simple-mfd";
|
|
reg = <0x9200000 0x450000>;
|
|
reg-names = "llcc_base";
|
|
qcom,llcc-banks-off = <0x00 0x80000>;
|
|
qcom,llcc-broadcast-off = <0x400000>;
|
|
|
|
qcom,sdmmagpie-llcc {
|
|
compatible = "qcom,sdmmagpie-llcc";
|
|
#cache-cells = <0x01>;
|
|
max-slices = <0x20>;
|
|
cap-based-alloc-and-pwr-collapse;
|
|
phandle = <0x19f>;
|
|
};
|
|
|
|
qcom,llcc-perfmon {
|
|
compatible = "qcom,llcc-perfmon";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "qdss_clk";
|
|
};
|
|
|
|
qcom,llcc-erp {
|
|
compatible = "qcom,llcc-erp";
|
|
};
|
|
|
|
qcom,llcc-amon {
|
|
compatible = "qcom,llcc-amon";
|
|
};
|
|
|
|
llcc_1_dcache {
|
|
qcom,dump-size = <0x6c000>;
|
|
phandle = <0x51>;
|
|
};
|
|
|
|
llcc_2_dcache {
|
|
qcom,dump-size = <0x6c000>;
|
|
phandle = <0x52>;
|
|
};
|
|
};
|
|
|
|
mailbox@18220000 {
|
|
compatible = "qcom,tcs-drv";
|
|
label = "apps_rsc";
|
|
reg = <0x18220000 0x100 0x18220d00 0x3000>;
|
|
interrupts = <0x00 0x05 0x00>;
|
|
#mbox-cells = <0x01>;
|
|
qcom,drv-id = <0x02>;
|
|
qcom,tcs-config = <0x02 0x02 0x00 0x03 0x01 0x03 0x03 0x01>;
|
|
phandle = <0x1b>;
|
|
};
|
|
|
|
mailbox@af20000 {
|
|
compatible = "qcom,tcs-drv";
|
|
label = "display_rsc";
|
|
reg = <0xaf20000 0x100 0xaf21c00 0x3000>;
|
|
interrupts = <0x00 0x81 0x00>;
|
|
#mbox-cells = <0x01>;
|
|
qcom,drv-id = <0x00>;
|
|
qcom,tcs-config = <0x00 0x01 0x01 0x01 0x02 0x02 0x03 0x00>;
|
|
phandle = <0xc7>;
|
|
};
|
|
|
|
system_pm {
|
|
compatible = "qcom,system-pm";
|
|
mboxes = <0x1b 0x00>;
|
|
};
|
|
|
|
qcom,cmd-db@c3f000c {
|
|
compatible = "qcom,cmd-db";
|
|
reg = <0xc3f000c 0x08>;
|
|
phandle = <0x2cc>;
|
|
};
|
|
|
|
syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
phandle = <0x85>;
|
|
};
|
|
|
|
hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <0x85 0x00 0x1000>;
|
|
#hwlock-cells = <0x01>;
|
|
phandle = <0x87>;
|
|
};
|
|
|
|
qcom,smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <0x86>;
|
|
hwlocks = <0x87 0x03>;
|
|
phandle = <0x2cd>;
|
|
};
|
|
|
|
syscon@17c0000c {
|
|
compatible = "syscon";
|
|
reg = <0x17c0000c 0x04>;
|
|
phandle = <0x8f>;
|
|
};
|
|
|
|
mailbox@17c00000 {
|
|
compatible = "qcom,sm8150-apcs-hmss-global";
|
|
reg = <0x17c00000 0x1000>;
|
|
#mbox-cells = <0x01>;
|
|
phandle = <0x89>;
|
|
};
|
|
|
|
qcom,msm-cdsp-loader {
|
|
compatible = "qcom,cdsp-loader";
|
|
qcom,proc-img-to-load = "cdsp";
|
|
};
|
|
|
|
qcom,msm-adsprpc-mem {
|
|
compatible = "qcom,msm-adsprpc-mem-region";
|
|
memory-region = <0x88>;
|
|
restrict-access;
|
|
};
|
|
|
|
qcom,msm_fastrpc {
|
|
compatible = "qcom,msm-fastrpc-compute";
|
|
qcom,rpc-latency-us = <0x263>;
|
|
qcom,secure-domains = <0x0f>;
|
|
qcom,adsp-remoteheap-vmid = <0x16 0x25>;
|
|
qcom,fastrpc-adsp-audio-pdr;
|
|
qcom,fastrpc-adsp-sensors-pdr;
|
|
|
|
qcom,msm_fastrpc_compute_cb1 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <0x30 0x1421 0x00 0x30 0x1441 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb2 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <0x30 0x1422 0x00 0x30 0x1442 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb3 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <0x30 0x1423 0x00 0x30 0x1443 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb4 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <0x30 0x1424 0x00 0x30 0x1444 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb5 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <0x30 0x1425 0x00 0x30 0x1445 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb6 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <0x30 0x1406 0x60>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb9 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
qcom,secure-context-bank;
|
|
iommus = <0x30 0x1409 0x60>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb10 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <0x30 0x1b23 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb11 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <0x30 0x1b24 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb12 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <0x30 0x1b25 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb13 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <0x30 0x1b26 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb14 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <0x30 0x1b27 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb15 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <0x30 0x1b28 0x00>;
|
|
shared-cb = <0x03>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
|
|
modem {
|
|
qcom,remote-pid = <0x01>;
|
|
transport = "smem";
|
|
mboxes = <0x89 0x0c>;
|
|
mbox-names = "mpss_smem";
|
|
interrupts = <0x00 0x1c1 0x01>;
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
phandle = <0x8c>;
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 0x40>;
|
|
};
|
|
|
|
qcom,modem_ds {
|
|
qcom,glink-channels = "DS";
|
|
qcom,intents = <0x4000 0x02>;
|
|
};
|
|
|
|
qcom,modem_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <0x8a 0x8b>;
|
|
};
|
|
};
|
|
|
|
adsp {
|
|
qcom,remote-pid = <0x02>;
|
|
transport = "smem";
|
|
mboxes = <0x89 0x18>;
|
|
mbox-names = "adsp_smem";
|
|
interrupts = <0x00 0xaa 0x01>;
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
phandle = <0x8a>;
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;
|
|
};
|
|
|
|
qcom,apr_tal_rpmsg {
|
|
qcom,glink-channels = "apr_audio_svc";
|
|
qcom,intents = <0x200 0x14>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 0x40>;
|
|
};
|
|
|
|
qcom,adsp_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <0x8c 0x8b>;
|
|
};
|
|
};
|
|
|
|
cdsp {
|
|
qcom,remote-pid = <0x05>;
|
|
transport = "smem";
|
|
mboxes = <0x89 0x04>;
|
|
mbox-names = "cdsp_smem";
|
|
interrupts = <0x00 0x23e 0x01>;
|
|
label = "cdsp";
|
|
qcom,glink-label = "cdsp";
|
|
phandle = <0x8b>;
|
|
|
|
qcom,cdsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 0x40>;
|
|
};
|
|
|
|
qcom,msm_cdsprm_rpmsg {
|
|
compatible = "qcom,msm-cdsprm-rpmsg";
|
|
qcom,glink-channels = "cdsprmglink-apps-dsp";
|
|
qcom,intents = <0x20 0x0c>;
|
|
|
|
qcom,cdsp-cdsp-l3-gov {
|
|
compatible = "qcom,cdsp-l3";
|
|
qcom,target-dev = <0x26>;
|
|
};
|
|
|
|
qcom,msm_cdsp_rm {
|
|
compatible = "qcom,msm-cdsp-rm";
|
|
qcom,qos-latency-us = <0x2c>;
|
|
qcom,qos-maxhold-ms = <0x14>;
|
|
qcom,compute-cx-limit-en;
|
|
qcom,compute-priority-mode = <0x02>;
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x74>;
|
|
};
|
|
|
|
qcom,msm_hvx_rm {
|
|
compatible = "qcom,msm-hvx-rm";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x2ce>;
|
|
};
|
|
};
|
|
|
|
qcom,cdsp_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <0x8c 0x8a>;
|
|
};
|
|
};
|
|
|
|
wdsp {
|
|
qcom,remote-pid = <0x0a>;
|
|
transport = "spi";
|
|
tx-descriptors = <0x12000 0x12004>;
|
|
rx-descriptors = <0x1200c 0x12010>;
|
|
label = "wdsp";
|
|
qcom,glink-label = "wdsp";
|
|
phandle = <0x2cf>;
|
|
|
|
qcom,wdsp_ctrl {
|
|
qcom,glink-channels = "g_glink_ctrl";
|
|
qcom,intents = <0x400 0x01>;
|
|
};
|
|
|
|
qcom,wdsp_ild {
|
|
qcom,glink-channels = "g_glink_persistent_data_ild";
|
|
};
|
|
|
|
qcom,wdsp_nild {
|
|
qcom,glink-channels = "g_glink_persistent_data_nild";
|
|
};
|
|
|
|
qcom,wdsp_data {
|
|
qcom,glink-channels = "g_glink_audio_data";
|
|
qcom,intents = <0x1000 0x02>;
|
|
};
|
|
|
|
qcom,diag_data {
|
|
qcom,glink-channels = "DIAG_DATA";
|
|
qcom,intents = <0x4000 0x02>;
|
|
};
|
|
|
|
qcom,diag_ctrl {
|
|
qcom,glink-channels = "DIAG_CTRL";
|
|
qcom,intents = <0x4000 0x01>;
|
|
};
|
|
|
|
qcom,diag_cmd {
|
|
qcom,glink-channels = "DIAG_CMD";
|
|
qcom,intents = <0x4000 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
|
|
qcom,glinkpkt-glinkbridge {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "glink_bridge";
|
|
qcom,glinkpkt-dev-name = "smd4";
|
|
};
|
|
};
|
|
|
|
qcom,qmp-npu-low@9818000 {
|
|
compatible = "qcom,qmp-mbox";
|
|
reg = <0x9818000 0x8000 0x17c00010 0x04>;
|
|
reg-names = "msgram\0irq-reg-base";
|
|
qcom,irq-mask = <0x20>;
|
|
interrupts = <0x00 0x24c 0x01>;
|
|
label = "npu_qmp_low";
|
|
priority = <0x00>;
|
|
mbox-desc-offset = <0x00>;
|
|
#mbox-cells = <0x01>;
|
|
phandle = <0x29e>;
|
|
};
|
|
|
|
qcom,qmp-npu-high@9818000 {
|
|
compatible = "qcom,qmp-mbox";
|
|
reg = <0x9818000 0x8000 0x17c00010 0x04>;
|
|
reg-names = "msgram\0irq-reg-base";
|
|
qcom,irq-mask = <0x40>;
|
|
interrupts = <0x00 0x24d 0x01>;
|
|
label = "npu_qmp_high";
|
|
priority = <0x01>;
|
|
mbox-desc-offset = <0x2000>;
|
|
#mbox-cells = <0x01>;
|
|
phandle = <0x29f>;
|
|
};
|
|
|
|
qcom,qmp-aop@c300000 {
|
|
compatible = "qcom,qmp-mbox";
|
|
reg = <0xc300000 0x1000 0x17c0000c 0x04>;
|
|
reg-names = "msgram\0irq-reg-base";
|
|
qcom,irq-mask = <0x01>;
|
|
interrupts = <0x00 0x185 0x01>;
|
|
label = "aop";
|
|
qcom,early-boot;
|
|
priority = <0x00>;
|
|
mbox-desc-offset = <0x00>;
|
|
#mbox-cells = <0x01>;
|
|
phandle = <0x1c>;
|
|
};
|
|
|
|
qcom,smp2p_sleepstate {
|
|
compatible = "qcom,smp2p-sleepstate";
|
|
qcom,smem-states = <0x8d 0x00>;
|
|
interrupt-parent = <0x8e>;
|
|
interrupts = <0x00 0x00>;
|
|
interrupt-names = "smp2p-sleepstate-in";
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x1b3 0x1ac>;
|
|
interrupts = <0x00 0x1c3 0x01>;
|
|
qcom,ipc = <0x8f 0x00 0x0e>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x01>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0xab>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xaa>;
|
|
};
|
|
|
|
qcom,smp2p-ipa-1-out {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0xb2>;
|
|
};
|
|
|
|
qcom,smp2p-ipa-1-in {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xb3>;
|
|
};
|
|
|
|
qcom,smp2p-wlan-1-in {
|
|
qcom,entry-name = "wlan";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xb1>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x1bb 0x1ad>;
|
|
interrupts = <0x00 0xac 0x01>;
|
|
qcom,ipc = <0x8f 0x00 0x1a>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x02>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x99>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x98>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg2-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x1b4>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg2-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1b5>;
|
|
};
|
|
|
|
sleepstate-out {
|
|
qcom,entry-name = "sleepstate";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x8d>;
|
|
};
|
|
|
|
qcom,sleepstate-in {
|
|
qcom,entry-name = "sleepstate_see";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x8e>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-cdsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x5e 0x1b0>;
|
|
interrupts = <0x00 0x240 0x01>;
|
|
qcom,ipc = <0x8f 0x00 0x06>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x05>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0xa7>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xa6>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg5-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x1b6>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg5-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1b7>;
|
|
};
|
|
|
|
qcom,smp2p-qvrexternal5-out {
|
|
qcom,entry-name = "qvrexternal";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x1b8>;
|
|
};
|
|
};
|
|
|
|
sdcc1ice@7C8000 {
|
|
compatible = "qcom,ice";
|
|
reg = <0x7c8000 0x8000>;
|
|
qcom,enable-ice-clk;
|
|
clock-names = "ice_core_clk_src\0ice_core_clk\0bus_clk\0iface_clk";
|
|
clocks = <0x27 0x6f 0x27 0x6e 0x27 0x6b 0x27 0x6c>;
|
|
qcom,op-freq-hz = <0x11e1a300 0x00 0x00 0x00>;
|
|
qcom,msm-bus,name = "sdcc_ice_noc";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x01 0x2f5 0x00 0x00 0x01 0x2f5 0x3e8 0x00>;
|
|
qcom,bus-vector-names = "MIN\0MAX";
|
|
qcom,instance-type = "sdcc";
|
|
phandle = <0x2d0>;
|
|
};
|
|
|
|
sdhci@7c4000 {
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x7c4000 0x1000 0x7c5000 0x1000 0x7c8000 0x8000>;
|
|
reg-names = "hc_mem\0cmdq_mem\0cmdq_ice";
|
|
interrupts = <0x00 0x281 0x00 0x00 0x284 0x00>;
|
|
interrupt-names = "hc_irq\0pwr_irq";
|
|
qcom,bus-width = <0x08>;
|
|
qcom,large-address-bus;
|
|
qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xb71b000 0x16e36000>;
|
|
qcom,bus-speed-mode = "HS400_1p8v\0HS200_1p8v\0DDR_1p8v";
|
|
qcom,devfreq,freq-table = <0x2faf080 0xbebc200>;
|
|
qcom,msm-bus,name = "sdhc1";
|
|
qcom,msm-bus,num-cases = <0x09>;
|
|
qcom,msm-bus,num-paths = <0x02>;
|
|
qcom,msm-bus,vectors-KBps = <0x96 0x200 0x00 0x00 0x01 0x326 0x00 0x00 0x96 0x200 0x3e8 0x7d0 0x01 0x326 0x7d0 0xfa0 0x96 0x200 0x61a8 0xc350 0x01 0x326 0x4e20 0x9c40 0x96 0x200 0xc350 0x186a0 0x01 0x326 0x7530 0xea60 0x96 0x200 0x13880 0x249f0 0x01 0x326 0x9c40 0x13880 0x96 0x200 0x186a0 0x30d40 0x01 0x326 0xc350 0x186a0 0x96 0x200 0x249f0 0x3d090 0x01 0x326 0x13880 0x1d4c0 0x96 0x200 0x3fd3e 0x297c66 0x01 0x326 0x493e0 0x14be33 0x96 0x200 0x146cc2 0x3e8000 0x01 0x326 0x146cc2 0x3e8000>;
|
|
qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x60152b0 0xbebc200 0x17d78400 0xffffffff>;
|
|
qcom,pm-qos-irq-type = "affine_irq";
|
|
qcom,pm-qos-irq-latency = <0x43 0x43>;
|
|
qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
|
|
qcom,pm-qos-cmdq-latency-us = <0x43 0x43 0x43 0x43>;
|
|
qcom,pm-qos-legacy-latency-us = <0x43 0x43 0x43 0x43>;
|
|
clocks = <0x27 0x6b 0x27 0x6c 0x27 0x6e>;
|
|
clock-names = "iface_clk\0core_clk\0ice_core_clk";
|
|
qcom,ice-clk-rates = <0x11e1a300 0x47868c0>;
|
|
qcom,scaling-lower-bus-speed-mode = "DDR52";
|
|
qcom,dll-hsr-list = <0xf642c 0x00 0x00 0x10800 0x80040868>;
|
|
qcom,nonremovable;
|
|
status = "disabled";
|
|
phandle = <0x2d1>;
|
|
vdd-supply = <0x3f4>;
|
|
qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;
|
|
qcom,vdd-current-level = <0x00 0x8b290>;
|
|
vdd-io-supply = <0x3ee>;
|
|
qcom,vdd-io-always-on;
|
|
qcom,vdd-io-lpm-sup;
|
|
qcom,vdd-io-voltage-level = <0x1b7740 0x1b7740>;
|
|
qcom,vdd-io-current-level = <0x00 0x4f588>;
|
|
pinctrl-names = "active\0sleep";
|
|
pinctrl-0 = <0x3d1 0x3d3 0x3d5 0x3d7>;
|
|
pinctrl-1 = <0x3d2 0x3d4 0x3d6 0x3d8>;
|
|
};
|
|
|
|
sdhci@8804000 {
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x8804000 0x1000>;
|
|
reg-names = "hc_mem";
|
|
interrupts = <0x00 0xcc 0x00 0x00 0xde 0x00>;
|
|
interrupt-names = "hc_irq\0pwr_irq";
|
|
qcom,bus-width = <0x04>;
|
|
qcom,large-address-bus;
|
|
qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xc0a4680>;
|
|
qcom,bus-speed-mode = "SDR12\0SDR25\0SDR50\0DDR50\0SDR104";
|
|
qcom,devfreq,freq-table = <0x2faf080 0xc0a4680>;
|
|
qcom,msm-bus,name = "sdhc2";
|
|
qcom,msm-bus,num-cases = <0x08>;
|
|
qcom,msm-bus,num-paths = <0x02>;
|
|
qcom,msm-bus,vectors-KBps = <0x51 0x200 0x00 0x00 0x01 0x260 0x00 0x00 0x51 0x200 0x3e8 0x7d0 0x01 0x260 0x640 0x4e20 0x51 0x200 0x4e20 0x9c40 0x01 0x260 0x4e20 0x9c40 0x51 0x200 0x9c40 0x13880 0x01 0x260 0x7530 0xea60 0x51 0x200 0xea60 0x1d4c0 0x01 0x260 0x9c40 0x13880 0x51 0x200 0x13880 0x27100 0x01 0x260 0xc350 0x186a0 0x51 0x200 0x186a0 0x30d40 0x01 0x260 0xea60 0x1d4c0 0x51 0x200 0x146cc2 0x3e8000 0x01 0x260 0x146cc2 0x3e8000>;
|
|
qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x60152b0 0xbebc200 0xffffffff>;
|
|
qcom,pm-qos-irq-type = "affine_irq";
|
|
qcom,pm-qos-irq-latency = <0x43 0x43>;
|
|
qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
|
|
qcom,pm-qos-legacy-latency-us = <0x43 0x43 0x43 0x43>;
|
|
clocks = <0x27 0x70 0x27 0x71>;
|
|
clock-names = "iface_clk\0core_clk";
|
|
qcom,dll-hsr-list = <0x7642c 0x00 0x00 0x10800 0x80040868>;
|
|
status = "ok";
|
|
phandle = <0x2d2>;
|
|
vdd-supply = <0x3fa>;
|
|
qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;
|
|
qcom,vdd-current-level = <0x00 0xc3500>;
|
|
vdd-io-supply = <0x3f7>;
|
|
qcom,vdd-io-voltage-level = <0x1b7740 0x2d0370>;
|
|
qcom,vdd-io-current-level = <0x00 0x55f0>;
|
|
pinctrl-names = "active\0sleep";
|
|
pinctrl-0 = <0x3d9 0x3db 0x3dd 0x4f4>;
|
|
pinctrl-1 = <0x3da 0x3dc 0x3de 0x4f5>;
|
|
cd-gpios = <0x16c 0x58 0x00>;
|
|
};
|
|
|
|
qseecom@86d00000 {
|
|
compatible = "qcom,qseecom";
|
|
reg = <0x86d00000 0xe00000>;
|
|
reg-names = "secapp-region";
|
|
memory-region = <0x90>;
|
|
qcom,hlos-num-ce-hw-instances = <0x01>;
|
|
qcom,hlos-ce-hw-instance = <0x00>;
|
|
qcom,qsee-ce-hw-instance = <0x00>;
|
|
qcom,disk-encrypt-pipe-pair = <0x02>;
|
|
qcom,support-fde;
|
|
qcom,no-clock-support;
|
|
qcom,fde-key-size;
|
|
qcom,appsbl-qseecom-support;
|
|
qcom,commonlib64-loaded-by-uefi;
|
|
qcom,qsee-reentrancy-support = <0x02>;
|
|
phandle = <0x2d3>;
|
|
};
|
|
|
|
smcinvoke@86d00000 {
|
|
compatible = "qcom,smcinvoke";
|
|
reg = <0x86d00000 0xe00000>;
|
|
reg-names = "secapp-region";
|
|
phandle = <0x2d4>;
|
|
};
|
|
|
|
qrng@793000 {
|
|
compatible = "qcom,msm-rng";
|
|
reg = <0x793000 0x1000>;
|
|
qcom,msm-rng-iface-clk;
|
|
qcom,no-qrng-config;
|
|
qcom,msm-bus,name = "msm-rng-noc";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x01 0x26a 0x00 0x00 0x01 0x26a 0x00 0x493e0>;
|
|
clocks = <0x27 0x41>;
|
|
clock-names = "iface_clk";
|
|
phandle = <0x2d5>;
|
|
};
|
|
|
|
ufsice@1d90000 {
|
|
compatible = "qcom,ice";
|
|
reg = <0x1d90000 0x8000>;
|
|
qcom,enable-ice-clk;
|
|
clock-names = "ufs_core_clk\0bus_clk\0iface_clk\0ice_core_clk";
|
|
clocks = <0x27 0x7e 0x27 0x7c 0x27 0x7d 0x27 0x81>;
|
|
qcom,op-freq-hz = <0x00 0x00 0x00 0x11e1a300>;
|
|
vdd-hba-supply = <0x91>;
|
|
qcom,msm-bus,name = "ufs_ice_noc";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x01 0x28a 0x00 0x00 0x01 0x28a 0x3e8 0x00>;
|
|
qcom,bus-vector-names = "MIN\0MAX";
|
|
qcom,instance-type = "ufs";
|
|
phandle = <0x2d6>;
|
|
};
|
|
|
|
ufsphy_mem@1d87000 {
|
|
reg = <0x1d87000 0xddc>;
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0x00>;
|
|
lanes-per-direction = <0x01>;
|
|
clock-names = "ref_clk_src\0ref_clk\0ref_aux_clk";
|
|
clocks = <0x2f 0x00 0x27 0x7c 0x27 0x84>;
|
|
status = "ok";
|
|
phandle = <0x92>;
|
|
compatible = "qcom,ufs-phy-qmp-v3";
|
|
vdda-phy-supply = <0x1a1>;
|
|
vdda-pll-supply = <0x1a0>;
|
|
vdda-phy-max-microamp = <0xf5b4>;
|
|
vdda-pll-max-microamp = <0x477c>;
|
|
};
|
|
|
|
ufshc@1d84000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x1d84000 0x3000 0x1d90000 0x8000>;
|
|
reg-names = "ufs_mem\0ufs_ice";
|
|
interrupts = <0x00 0x109 0x00>;
|
|
phys = <0x92>;
|
|
phy-names = "ufsphy";
|
|
lanes-per-direction = <0x01>;
|
|
dev-ref-clk-freq = <0x00>;
|
|
clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk";
|
|
clocks = <0x27 0x7e 0x27 0x09 0x27 0x7d 0x27 0x89 0x27 0x81 0x2f 0x00 0x27 0x88 0x27 0x87>;
|
|
freq-table-hz = <0x2faf080 0xbebc200 0x00 0x00 0x00 0x00 0x23c3460 0x8f0d180 0x47868c0 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
qcom,msm-bus,name = "ufshc_mem";
|
|
qcom,msm-bus,num-cases = <0x0c>;
|
|
qcom,msm-bus,num-paths = <0x02>;
|
|
qcom,msm-bus,vectors-KBps = <0x7b 0x200 0x00 0x00 0x01 0x2f5 0x00 0x00 0x7b 0x200 0x39a 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x734 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0xe68 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1cd0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1f334 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x3e667 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x247ae 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x48ccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x74a000 0x00 0x01 0x2f5 0x4b000 0x00>;
|
|
qcom,bus-vector-names = "MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0MAX";
|
|
qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
|
|
qcom,pm-qos-cpu-group-latency-us = <0x43 0x43>;
|
|
qcom,pm-qos-default-cpu = <0x00>;
|
|
pinctrl-names = "dev-reset-assert\0dev-reset-deassert";
|
|
pinctrl-0 = <0x93>;
|
|
pinctrl-1 = <0x94>;
|
|
resets = <0x27 0x03>;
|
|
reset-names = "core_reset";
|
|
non-removable;
|
|
status = "ok";
|
|
phandle = <0x2d7>;
|
|
vdd-hba-supply = <0x91>;
|
|
vdd-hba-fixed-regulator;
|
|
vcc-supply = <0x3f4>;
|
|
vcc-voltage-level = <0x2d0370 0x2d2a80>;
|
|
vccq2-supply = <0x3ee>;
|
|
vccq2-voltage-level = <0x1b7740 0x1b7740>;
|
|
vcc-max-microamp = <0x927c0>;
|
|
vccq2-max-microamp = <0x927c0>;
|
|
qcom,vddp-ref-clk-supply = <0x1a0>;
|
|
qcom,vddp-ref-clk-max-microamp = <0x64>;
|
|
};
|
|
|
|
qcom,lpass@62400000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0x62400000 0x100>;
|
|
vdd_lpi_cx-supply = <0x95>;
|
|
qcom,vdd_cx-uV-uA = <0x181 0x00>;
|
|
vdd_lpi_mx-supply = <0x96>;
|
|
qcom,vdd_mx-uV-uA = <0x181 0x00>;
|
|
qcom,proxy-reg-names = "vdd_lpi_cx\0vdd_lpi_mx";
|
|
clocks = <0x2f 0x00>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
qcom,pas-id = <0x01>;
|
|
qcom,proxy-timeout-ms = <0x2710>;
|
|
qcom,smem-id = <0x1a7>;
|
|
qcom,sysmon-id = <0x01>;
|
|
qcom,ssctl-instance-id = <0x14>;
|
|
qcom,firmware-name = "adsp";
|
|
memory-region = <0x97>;
|
|
qcom,signal-aop;
|
|
qcom,complete-ramdump;
|
|
interrupts-extended = <0x01 0x00 0xa2 0x01 0x98 0x00 0x00 0x98 0x01 0x00 0x98 0x02 0x00 0x98 0x03 0x00>;
|
|
interrupt-names = "qcom,wdog\0qcom,err-fatal\0qcom,err-ready\0qcom,proxy-unvote\0qcom,stop-ack";
|
|
qcom,smem-states = <0x99 0x00>;
|
|
qcom,smem-state-names = "qcom,force-stop";
|
|
mboxes = <0x1c 0x00>;
|
|
mbox-names = "adsp-pil";
|
|
sensor_vdd-supply = <0x3f9>;
|
|
qcom,sensor_vdd-uV-uA = <0x1b7740 0x00>;
|
|
qcom,active-reg-names = "sensor_vdd";
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x00 0x200000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x01>;
|
|
qcom,guard-memory;
|
|
};
|
|
|
|
qcedev@1de0000 {
|
|
compatible = "qcom,qcedev";
|
|
reg = <0x1de0000 0x20000 0x1dc4000 0x24000>;
|
|
reg-names = "crypto-base\0crypto-bam-base";
|
|
interrupts = <0x00 0x110 0x00>;
|
|
qcom,bam-pipe-pair = <0x03>;
|
|
qcom,ce-hw-instance = <0x00>;
|
|
qcom,ce-device = <0x00>;
|
|
qcom,ce-hw-shared;
|
|
qcom,bam-ee = <0x00>;
|
|
qcom,msm-bus,name = "qcedev-noc";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180>;
|
|
qcom,smmu-s1-enable;
|
|
qcom,no-clock-support;
|
|
iommus = <0x30 0x506 0x11 0x30 0x516 0x11>;
|
|
phandle = <0x2d8>;
|
|
};
|
|
|
|
qcom,msm_hdcp {
|
|
compatible = "qcom,msm-hdcp";
|
|
phandle = <0x2d9>;
|
|
};
|
|
|
|
qcrypto@1de0000 {
|
|
compatible = "qcom,qcrypto";
|
|
reg = <0x1de0000 0x20000 0x1dc4000 0x24000>;
|
|
reg-names = "crypto-base\0crypto-bam-base";
|
|
interrupts = <0x00 0x110 0x00>;
|
|
qcom,bam-pipe-pair = <0x02>;
|
|
qcom,ce-hw-instance = <0x00>;
|
|
qcom,ce-device = <0x00>;
|
|
qcom,bam-ee = <0x00>;
|
|
qcom,ce-hw-shared;
|
|
qcom,clk-mgmt-sus-res;
|
|
qcom,msm-bus,name = "qcrypto-noc";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180>;
|
|
qcom,use-sw-aes-cbc-ecb-ctr-algo;
|
|
qcom,use-sw-aes-xts-algo;
|
|
qcom,use-sw-aes-ccm-algo;
|
|
qcom,use-sw-ahash-algo;
|
|
qcom,use-sw-aead-algo;
|
|
qcom,use-sw-hmac-algo;
|
|
qcom,smmu-s1-enable;
|
|
qcom,no-clock-support;
|
|
iommus = <0x30 0x504 0x11 0x30 0x514 0x11>;
|
|
phandle = <0x2da>;
|
|
};
|
|
|
|
tz-log@146aa720 {
|
|
compatible = "qcom,tz-log";
|
|
reg = <0x146aa720 0x3000>;
|
|
qcom,hyplog-enabled;
|
|
hyplog-address-offset = <0x410>;
|
|
hyplog-size-offset = <0x414>;
|
|
phandle = <0x2db>;
|
|
};
|
|
|
|
qcom,spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc440000 0x1100 0xc600000 0x2000000 0xe600000 0x100000 0xe700000 0xa0000 0xc40a000 0x26000>;
|
|
reg-names = "core\0chnls\0obsrvr\0intr\0cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <0x00 0x1e1 0x00>;
|
|
qcom,ee = <0x00>;
|
|
qcom,channel = <0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x04>;
|
|
cell-index = <0x00>;
|
|
phandle = <0x2dc>;
|
|
|
|
qcom,pm6150@0 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x00 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
|
|
qcom,revid@100 {
|
|
compatible = "qcom,qpnp-revid";
|
|
reg = <0x100 0x100>;
|
|
phandle = <0x9a>;
|
|
};
|
|
|
|
qcom,power-on@800 {
|
|
compatible = "qcom,qpnp-power-on";
|
|
reg = <0x800 0x100>;
|
|
interrupts = <0x00 0x08 0x00 0x00 0x00 0x08 0x01 0x00 0x00 0x08 0x04 0x00 0x00 0x08 0x05 0x00>;
|
|
interrupt-names = "kpdpwr\0resin\0resin-bark\0kpdpwr-resin-bark";
|
|
qcom,pon-dbc-delay = <0x3d09>;
|
|
qcom,kpdpwr-sw-debounce;
|
|
qcom,system-reset;
|
|
qcom,store-hard-reset-reason;
|
|
qcom,s3-debounce = <0x80>;
|
|
|
|
qcom,pon_1 {
|
|
qcom,pon-type = <0x00>;
|
|
qcom,pull-up;
|
|
linux,code = <0x74>;
|
|
qcom,support-reset = <0x00>;
|
|
};
|
|
|
|
qcom,pon_2 {
|
|
qcom,pon-type = <0x01>;
|
|
qcom,pull-up;
|
|
linux,code = <0x72>;
|
|
qcom,support-reset = <0x00>;
|
|
};
|
|
|
|
qcom,pon_3 {
|
|
qcom,pon-type = <0x03>;
|
|
qcom,support-reset = <0x01>;
|
|
qcom,pull-up = <0x01>;
|
|
qcom,s1-timer = <0x1a40>;
|
|
qcom,s2-timer = <0x3e8>;
|
|
qcom,s2-type = <0x08>;
|
|
qcom,use-bark;
|
|
};
|
|
};
|
|
|
|
vadc@3100 {
|
|
compatible = "qcom,spmi-adc5";
|
|
reg = <0x3100 0x100 0x3700 0x100>;
|
|
reg-names = "adc5-usr-base\0adc5-cal-base";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x31 0x00 0x01>;
|
|
interrupt-names = "eoc-int-en-set";
|
|
qcom,adc-vdd-reference = <0x753>;
|
|
#io-channel-cells = <0x01>;
|
|
io-channel-ranges;
|
|
qcom,pmic-revid = <0x9a>;
|
|
phandle = <0x9b>;
|
|
|
|
ref_gnd {
|
|
reg = <0x00>;
|
|
label = "ref_gnd";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
vref_1p25 {
|
|
reg = <0x01>;
|
|
label = "vref_1p25";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
die_temp {
|
|
reg = <0x06>;
|
|
label = "die_temp";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
vph_pwr {
|
|
reg = <0x83>;
|
|
label = "vph_pwr";
|
|
qcom,pre-scaling = <0x01 0x03>;
|
|
};
|
|
|
|
vbat_sns {
|
|
reg = <0x84>;
|
|
label = "vbat_sns";
|
|
qcom,pre-scaling = <0x01 0x03>;
|
|
};
|
|
|
|
vcoin {
|
|
reg = <0x85>;
|
|
label = "vcoin";
|
|
qcom,pre-scaling = <0x01 0x03>;
|
|
};
|
|
|
|
usb_in_i_uv {
|
|
reg = <0x07>;
|
|
label = "usb_in_i_uv";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
usb_in_v_div_16 {
|
|
reg = <0x08>;
|
|
label = "usb_in_v_div_16";
|
|
qcom,pre-scaling = <0x01 0x10>;
|
|
};
|
|
|
|
chg_temp {
|
|
reg = <0x09>;
|
|
label = "chg_temp";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
bat_therm {
|
|
reg = <0x4a>;
|
|
label = "bat_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
bat_therm_30k {
|
|
reg = <0x2a>;
|
|
label = "bat_therm_30k";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
bat_therm_400k {
|
|
reg = <0x6a>;
|
|
label = "bat_therm_400k";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
bat_id {
|
|
reg = <0x4b>;
|
|
label = "bat_id";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
xo_therm {
|
|
reg = <0x4c>;
|
|
label = "xo_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
chg_sbux {
|
|
reg = <0x99>;
|
|
label = "chg_sbux";
|
|
qcom,pre-scaling = <0x01 0x03>;
|
|
};
|
|
|
|
mid_chg_div6 {
|
|
reg = <0x1e>;
|
|
label = "chg_mid";
|
|
qcom,pre-scaling = <0x01 0x06>;
|
|
};
|
|
|
|
v_i_int_ext {
|
|
reg = <0xb0>;
|
|
label = "v_i_int_vbat_vdata";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
v_i_parallel {
|
|
reg = <0xb4>;
|
|
label = "v_i_parallel_vbat_vdata";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
rf_pa0_therm {
|
|
reg = <0x4e>;
|
|
label = "pa_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
qcom,decimation = <0x348>;
|
|
qcom,avg-samples = <0x08>;
|
|
};
|
|
|
|
rf_pa1_therm {
|
|
reg = <0x4f>;
|
|
label = "wf_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
qcom,decimation = <0x348>;
|
|
qcom,avg-samples = <0x08>;
|
|
};
|
|
|
|
quiet_therm {
|
|
reg = <0x50>;
|
|
label = "quiet_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bat_thm {
|
|
reg = <0x50>;
|
|
label = "bat_thm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
};
|
|
|
|
adc_tm@3500 {
|
|
compatible = "qcom,adc-tm5";
|
|
reg = <0x3500 0x100>;
|
|
interrupts = <0x00 0x35 0x00 0x01>;
|
|
interrupt-names = "thr-int-en";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
#thermal-sensor-cells = <0x01>;
|
|
io-channels = <0x9b 0x4c 0x9b 0x4e 0x9b 0x4f>;
|
|
phandle = <0x5b>;
|
|
|
|
xo_therm {
|
|
reg = <0x4c>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
};
|
|
|
|
rf_pa0_therm {
|
|
reg = <0x4e>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
};
|
|
|
|
rf_pa1_therm {
|
|
reg = <0x4f>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
};
|
|
|
|
quiet_therm {
|
|
reg = <0x50>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom,misc@900 {
|
|
compatible = "qcom,qpnp-misc";
|
|
reg = <0x900 0x100>;
|
|
phandle = <0x2dd>;
|
|
};
|
|
|
|
qcom,qpnp-smb5 {
|
|
compatible = "qcom,qpnp-smb5";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
#cooling-cells = <0x02>;
|
|
qcom,pmic-revid = <0x9a>;
|
|
phandle = <0x80>;
|
|
io-channels = <0x9b 0x08 0x9b 0x07 0x9b 0x09 0x9b 0x06 0x9b 0x99 0x9b 0x83>;
|
|
io-channel-names = "usb_in_voltage\0usb_in_current\0chg_temp\0die_temp\0sbux_res\0vph_voltage";
|
|
qcom,battery-data = <0x4f6>;
|
|
qcom,auto-recharge-soc = <0x62>;
|
|
qcom,step-charging-enable;
|
|
qcom,sw-jeita-enable;
|
|
qcom,fcc-stepping-enable;
|
|
qcom,suspend-input-on-debug-batt;
|
|
qcom,sec-charger-config = <0x03>;
|
|
qcom,thermal-mitigation = <0x401640 0x3567e0 0x2dc6c0 0x2625a0 0x1e8480 0x16e360 0xf4240 0x7a120>;
|
|
dpdm-supply = <0x252>;
|
|
qcom,charger-temp-max = <0x320>;
|
|
qcom,smb-temp-max = <0x320>;
|
|
|
|
qcom,chgr@1000 {
|
|
reg = <0x1000 0x100>;
|
|
interrupts = <0x00 0x10 0x00 0x01 0x00 0x10 0x01 0x01 0x00 0x10 0x02 0x01 0x00 0x10 0x03 0x01 0x00 0x10 0x04 0x01 0x00 0x10 0x05 0x01 0x00 0x10 0x06 0x01 0x00 0x10 0x07 0x01>;
|
|
interrupt-names = "chgr-error\0chg-state-change\0step-chg-state-change\0step-chg-soc-update-fail\0step-chg-soc-update-req\0fg-fvcal-qualified\0vph-alarm\0vph-drop-prechg";
|
|
};
|
|
|
|
qcom,dcdc@1100 {
|
|
reg = <0x1100 0x100>;
|
|
interrupts = <0x00 0x11 0x00 0x01 0x00 0x11 0x01 0x01 0x00 0x11 0x02 0x01 0x00 0x11 0x03 0x03 0x00 0x11 0x04 0x03 0x00 0x11 0x05 0x03 0x00 0x11 0x06 0x01 0x00 0x11 0x07 0x03>;
|
|
interrupt-names = "otg-fail\0otg-oc-disable-sw\0otg-oc-hiccup\0bsm-active\0high-duty-cycle\0input-current-limiting\0concurrent-mode-disable\0switcher-power-ok";
|
|
};
|
|
|
|
qcom,batif@1200 {
|
|
reg = <0x1200 0x100>;
|
|
interrupts = <0x00 0x12 0x00 0x01 0x00 0x12 0x02 0x03 0x00 0x12 0x03 0x03 0x00 0x12 0x04 0x03 0x00 0x12 0x05 0x03 0x00 0x12 0x06 0x03 0x00 0x12 0x07 0x03>;
|
|
interrupt-names = "bat-temp\0bat-ov\0bat-low\0bat-therm-or-id-missing\0bat-terminal-missing\0buck-oc\0vph-ov";
|
|
};
|
|
|
|
qcom,usb@1300 {
|
|
reg = <0x1300 0x100>;
|
|
interrupts = <0x00 0x13 0x00 0x03 0x00 0x13 0x01 0x03 0x00 0x13 0x02 0x03 0x00 0x13 0x03 0x03 0x00 0x13 0x04 0x03 0x00 0x13 0x05 0x01 0x00 0x13 0x06 0x01 0x00 0x13 0x07 0x01>;
|
|
interrupt-names = "usbin-collapse\0usbin-vashdn\0usbin-uv\0usbin-ov\0usbin-plugin\0usbin-revi-change\0usbin-src-change\0usbin-icl-change";
|
|
};
|
|
|
|
qcom,dc@1400 {
|
|
reg = <0x1400 0x100>;
|
|
interrupts = <0x00 0x14 0x01 0x03 0x00 0x14 0x02 0x03 0x00 0x14 0x03 0x03 0x00 0x14 0x04 0x03 0x00 0x14 0x05 0x01 0x00 0x14 0x06 0x01 0x00 0x14 0x07 0x01>;
|
|
interrupt-names = "dcin-vashdn\0dcin-uv\0dcin-ov\0dcin-plugin\0dcin-revi\0dcin-pon\0dcin-en";
|
|
};
|
|
|
|
qcom,typec@1500 {
|
|
reg = <0x1500 0x100>;
|
|
interrupts = <0x00 0x15 0x00 0x01 0x00 0x15 0x01 0x01 0x00 0x15 0x02 0x01 0x00 0x15 0x03 0x01 0x00 0x15 0x04 0x01 0x00 0x15 0x05 0x01 0x00 0x15 0x06 0x01 0x00 0x15 0x07 0x01>;
|
|
interrupt-names = "typec-or-rid-detect-change\0typec-vpd-detect\0typec-cc-state-change\0typec-vconn-oc\0typec-vbus-change\0typec-attach-detach\0typec-legacy-cable-detect\0typec-try-snk-src-detect";
|
|
};
|
|
|
|
qcom,misc@1600 {
|
|
reg = <0x1600 0x100>;
|
|
interrupts = <0x00 0x16 0x00 0x01 0x00 0x16 0x01 0x01 0x00 0x16 0x02 0x01 0x00 0x16 0x03 0x01 0x00 0x16 0x04 0x03 0x00 0x16 0x05 0x01 0x00 0x16 0x06 0x01 0x00 0x16 0x07 0x01>;
|
|
interrupt-names = "wdog-snarl\0wdog-bark\0aicl-fail\0aicl-done\0smb-en\0imp-trigger\0temp-change\0temp-change-smb";
|
|
};
|
|
|
|
qcom,sdam@b100 {
|
|
reg = <0xb100 0x100>;
|
|
interrupts = <0x00 0xb1 0x01 0x01>;
|
|
interrupt-names = "sdam-sts";
|
|
};
|
|
|
|
qcom,smb5-vbus {
|
|
regulator-name = "smb5-vbus";
|
|
phandle = <0x9d>;
|
|
};
|
|
|
|
qcom,smb5-vconn {
|
|
regulator-name = "smb5-vconn";
|
|
phandle = <0x9e>;
|
|
};
|
|
};
|
|
|
|
qcom,usb-pdphy@1700 {
|
|
compatible = "qcom,qpnp-pdphy";
|
|
reg = <0x1700 0x100>;
|
|
vdd-pdphy-supply = <0x9c>;
|
|
vbus-supply = <0x9d>;
|
|
vconn-supply = <0x9e>;
|
|
interrupts = <0x00 0x17 0x00 0x01 0x00 0x17 0x01 0x01 0x00 0x17 0x02 0x01 0x00 0x17 0x03 0x01 0x00 0x17 0x04 0x01 0x00 0x17 0x05 0x01 0x00 0x17 0x06 0x01 0x00 0x17 0x07 0x01>;
|
|
interrupt-names = "sig-tx\0sig-rx\0msg-tx\0msg-rx\0msg-tx-failed\0msg-tx-discarded\0msg-rx-discarded\0fr-swap";
|
|
qcom,default-sink-caps = <0x1388 0xbb8 0x2328 0xbb8 0x2ee0 0x8ca>;
|
|
phandle = <0x253>;
|
|
};
|
|
|
|
qpnp,qg {
|
|
compatible = "qcom,qpnp-qg";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
qcom,vbatt-cutoff-mv = <0xc80>;
|
|
qcom,vbatt-low-mv = <0xce4>;
|
|
qcom,vbatt-low-cold-mv = <0xe74>;
|
|
qcom,vbatt-empty-mv = <0xbb8>;
|
|
qcom,vbatt-empty-cold-mv = <0xbb8>;
|
|
qcom,s3-entry-fifo-length = <0x02>;
|
|
qcom,s3-entry-ibat-ua = <0x3a98>;
|
|
qcom,s3-exit-ibat-ua = <0x88b8>;
|
|
qcom,pmic-revid = <0x9a>;
|
|
io-channels = <0x9b 0x4a 0x9b 0x4b>;
|
|
io-channel-names = "batt-therm\0batt-id";
|
|
phandle = <0x2de>;
|
|
qcom,battery-data = <0x4f6>;
|
|
qcom,qg-iterm-ma = <0x64>;
|
|
qcom,hold-soc-while-full;
|
|
qcom,linearize-soc;
|
|
qcom,cl-feedback-on;
|
|
|
|
qcom,qgauge@4800 {
|
|
status = "okay";
|
|
reg = <0x4800 0x100>;
|
|
interrupts = <0x00 0x48 0x00 0x03 0x00 0x48 0x01 0x03 0x00 0x48 0x02 0x01 0x00 0x48 0x03 0x01 0x00 0x48 0x04 0x01>;
|
|
interrupt-names = "qg-batt-missing\0qg-vbat-low\0qg-vbat-empty\0qg-fifo-done\0qg-good-ocv";
|
|
};
|
|
|
|
qcom,qg-sdam@b600 {
|
|
status = "okay";
|
|
reg = <0xb600 0x100>;
|
|
};
|
|
};
|
|
|
|
bcl@1d00 {
|
|
compatible = "qcom,bcl-v5";
|
|
reg = <0x1d00 0x100>;
|
|
interrupts = <0x00 0x1d 0x00 0x00 0x00 0x1d 0x01 0x00 0x00 0x1d 0x02 0x00>;
|
|
interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x55>;
|
|
};
|
|
|
|
bcl-soc {
|
|
compatible = "qcom,msm-bcl-soc";
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x56>;
|
|
};
|
|
|
|
qcom,temp-alarm@2400 {
|
|
compatible = "qcom,spmi-temp-alarm";
|
|
reg = <0x2400 0x100>;
|
|
interrupts = <0x00 0x24 0x00 0x01>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
qcom,temperature-threshold-set = <0x01>;
|
|
phandle = <0x54>;
|
|
};
|
|
|
|
clock-controller@5b00 {
|
|
compatible = "qcom,spmi-clkdiv";
|
|
reg = <0x5b00 0x100>;
|
|
#clock-cells = <0x01>;
|
|
qcom,num-clkdivs = <0x01>;
|
|
clock-output-names = "pm6150_div_clk1";
|
|
clocks = <0x2f 0x00>;
|
|
clock-names = "xo";
|
|
assigned-clocks = <0x9f 0x01>;
|
|
assigned-clock-rates = <0x124f800>;
|
|
phandle = <0x9f>;
|
|
};
|
|
|
|
pinctrl@c000 {
|
|
compatible = "qcom,spmi-gpio";
|
|
reg = <0xc000 0xa00>;
|
|
interrupts = <0x00 0xc0 0x00 0x00 0x00 0xc1 0x00 0x00 0x00 0xc2 0x00 0x00 0x00 0xc3 0x00 0x00 0x00 0xc5 0x00 0x00 0x00 0xc6 0x00 0x00 0x00 0xc7 0x00 0x00>;
|
|
interrupt-names = "pm6150_gpio1\0pm6150_gpio2\0pm6150_gpio3\0pm6150_gpio4\0pm6150_gpio6\0pm6150_gpio7\0pm6150_gpio8";
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
qcom,gpios-disallowed = <0x05 0x09 0x0a>;
|
|
phandle = <0x2df>;
|
|
|
|
afc_switch {
|
|
|
|
gpio1_afc_switch_default {
|
|
pins = "gpio1";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
output-low;
|
|
input-disable;
|
|
phandle = <0x2e0>;
|
|
};
|
|
};
|
|
|
|
wcd934x_mclk {
|
|
|
|
wcd934x_mclk_default {
|
|
pins = "gpio8";
|
|
function = "func1";
|
|
qcom,drive-strength = <0x02>;
|
|
power-source = <0x00>;
|
|
bias-disable;
|
|
output-low;
|
|
phandle = <0x2e1>;
|
|
};
|
|
};
|
|
|
|
smb_stat {
|
|
|
|
smb_stat_default {
|
|
pins = "gpio3";
|
|
function = "normal";
|
|
input-enable;
|
|
bias-pull-up;
|
|
qcom,pull-up-strength = <0x00>;
|
|
power-source = <0x00>;
|
|
phandle = <0x4f7>;
|
|
};
|
|
};
|
|
|
|
tsp_int_dvdd_en {
|
|
pins = "gpio4";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
phandle = <0x542>;
|
|
};
|
|
|
|
detect_conn_pm_setting {
|
|
pins = "gpio8";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
bias-disable;
|
|
input-enable;
|
|
phandle = <0x54a>;
|
|
};
|
|
};
|
|
|
|
qcom,pm6150_rtc {
|
|
compatible = "qcom,qpnp-rtc";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
qcom,qpnp-rtc-write = <0x00>;
|
|
qcom,qpnp-rtc-alarm-pwrup = <0x00>;
|
|
phandle = <0x2e2>;
|
|
|
|
qcom,pm6150_rtc_rw@6000 {
|
|
reg = <0x6000 0x100>;
|
|
};
|
|
|
|
qcom,pm6150_rtc_alarm@6100 {
|
|
reg = <0x6100 0x100>;
|
|
interrupts = <0x00 0x61 0x01 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,pm6150@1 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x01 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
|
|
qcom,vibrator@5300 {
|
|
compatible = "qcom,qpnp-vibrator-ldo";
|
|
reg = <0x5300 0x100>;
|
|
qcom,vib-ldo-volt-uv = <0x325aa0>;
|
|
qcom,disable-overdrive;
|
|
phandle = <0x2e3>;
|
|
};
|
|
};
|
|
|
|
qcom,pm6150l@4 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x04 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
|
|
qcom,revid@100 {
|
|
compatible = "qcom,qpnp-revid";
|
|
reg = <0x100 0x100>;
|
|
phandle = <0xa3>;
|
|
};
|
|
|
|
qcom,power-on@800 {
|
|
compatible = "qcom,qpnp-power-on";
|
|
reg = <0x800 0x100>;
|
|
};
|
|
|
|
qcom,temp-alarm@2400 {
|
|
compatible = "qcom,spmi-temp-alarm";
|
|
reg = <0x2400 0x100>;
|
|
interrupts = <0x04 0x24 0x00 0x01>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
qcom,temperature-threshold-set = <0x01>;
|
|
phandle = <0x57>;
|
|
};
|
|
|
|
bcl@3d00 {
|
|
compatible = "qcom,bcl-v5";
|
|
reg = <0x3d00 0x100>;
|
|
interrupts = <0x04 0x3d 0x00 0x00 0x04 0x3d 0x01 0x00 0x04 0x3d 0x02 0x00>;
|
|
interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x58>;
|
|
};
|
|
|
|
vadc@3100 {
|
|
compatible = "qcom,spmi-adc5";
|
|
reg = <0x3100 0x100>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x04 0x31 0x00 0x01>;
|
|
interrupt-names = "eoc-int-en-set";
|
|
qcom,adc-vdd-reference = <0x753>;
|
|
#io-channel-cells = <0x01>;
|
|
io-channel-ranges;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x550>;
|
|
phandle = <0xa1>;
|
|
|
|
ref_gnd {
|
|
reg = <0x00>;
|
|
label = "ref_gnd";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
vref_1p25 {
|
|
reg = <0x01>;
|
|
label = "vref_1p25";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
die_temp {
|
|
reg = <0x06>;
|
|
label = "die_temp";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
vph_pwr {
|
|
reg = <0x83>;
|
|
label = "vph_pwr";
|
|
qcom,pre-scaling = <0x01 0x03>;
|
|
};
|
|
|
|
rid_adc {
|
|
reg = <0x15>;
|
|
label = "rid_adc";
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
qcom,hw-settle-time = <0x2bc>;
|
|
qcom,decimation = <0x348>;
|
|
qcom,avg-samples = <0x04>;
|
|
};
|
|
|
|
conn_therm {
|
|
reg = <0x4d>;
|
|
label = "conn_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
smb_therm {
|
|
reg = <0x0e>;
|
|
label = "smb_therm";
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
};
|
|
|
|
camera_ftherm {
|
|
reg = <0x4f>;
|
|
label = "camera_ftherm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
status = "disabled";
|
|
};
|
|
|
|
nvm_therm {
|
|
reg = <0x55>;
|
|
label = "nvm_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdm_therm {
|
|
reg = <0x4f>;
|
|
label = "ap_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
qcom,pre-scaling = <0x01 0x01>;
|
|
qcom,decimation = <0x348>;
|
|
qcom,avg-samples = <0x08>;
|
|
};
|
|
};
|
|
|
|
adc_tm@3500 {
|
|
compatible = "qcom,adc-tm5";
|
|
reg = <0x3500 0x100>;
|
|
interrupts = <0x04 0x35 0x00 0x01>;
|
|
interrupt-names = "thr-int-en";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
#thermal-sensor-cells = <0x01>;
|
|
io-channels = <0xa1 0x4d 0xa1 0x4f 0xa1 0x55>;
|
|
phandle = <0x5c>;
|
|
status = "disabled";
|
|
|
|
conn_therm {
|
|
reg = <0x4d>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
};
|
|
|
|
camera_ftherm {
|
|
reg = <0x4f>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
};
|
|
|
|
nvm_therm {
|
|
reg = <0x55>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <0xc8>;
|
|
};
|
|
};
|
|
|
|
clock-controller@5b00 {
|
|
compatible = "qcom,spmi-clkdiv";
|
|
reg = <0x5b00 0x100>;
|
|
#clock-cells = <0x01>;
|
|
qcom,num-clkdivs = <0x01>;
|
|
clock-output-names = "pm6150l_div_clk1";
|
|
clocks = <0x2f 0x00>;
|
|
clock-names = "xo";
|
|
assigned-clocks = <0xa2 0x01>;
|
|
assigned-clock-rates = <0x927c00>;
|
|
phandle = <0xa2>;
|
|
};
|
|
|
|
pinctrl@c000 {
|
|
compatible = "qcom,spmi-gpio";
|
|
reg = <0xc000 0xc00>;
|
|
interrupts = <0x04 0xc0 0x00 0x00 0x04 0xc1 0x00 0x00 0x04 0xc2 0x00 0x00 0x04 0xc3 0x00 0x00 0x04 0xc4 0x00 0x00 0x04 0xc5 0x00 0x00 0x04 0xc7 0x00 0x00 0x04 0xc8 0x00 0x00 0x04 0xc9 0x00 0x00 0x04 0xca 0x00 0x00 0x04 0xcb 0x00 0x00>;
|
|
interrupt-names = "pm6150l_gpio1\0pm6150l_gpio2\0pm6150l_gpio3\0pm6150l_gpio4\0pm6150l_gpio5\0pm6150l_gpio6\0pm6150l_gpio8\0pm6150l_gpio9\0pm6150l_gpio10\0pm6150l_gpio11\0pm6150l_gpio12";
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
phandle = <0x2e4>;
|
|
qcom,gpios-disallowed = <0x07>;
|
|
|
|
rid_adc_irq {
|
|
|
|
rid_adc_irq_default {
|
|
pins = "gpio9";
|
|
function = "normal";
|
|
bias-disable;
|
|
power-source = <0x01>;
|
|
input-enable;
|
|
phandle = <0x2e5>;
|
|
};
|
|
};
|
|
|
|
gpio11_dig_out {
|
|
|
|
gpio11_dig_out_default {
|
|
pins = "gpio11";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
input-disable;
|
|
phandle = <0x2e6>;
|
|
};
|
|
};
|
|
|
|
disp_pins {
|
|
|
|
disp_pins_default {
|
|
pins = "gpio9";
|
|
function = "func1";
|
|
qcom,drive-strength = <0x02>;
|
|
power-source = <0x01>;
|
|
bias-disable;
|
|
output-low;
|
|
phandle = <0x2e7>;
|
|
};
|
|
};
|
|
|
|
nvm_therm {
|
|
|
|
nvm_therm_default {
|
|
pins = "gpio10";
|
|
bias-high-impedance;
|
|
phandle = <0xa0>;
|
|
};
|
|
};
|
|
|
|
key_vol_up {
|
|
|
|
key_vol_up_default {
|
|
pins = "gpio2";
|
|
function = "normal";
|
|
input-enable;
|
|
bias-pull-up;
|
|
power-source = <0x00>;
|
|
phandle = <0x4fb>;
|
|
};
|
|
};
|
|
|
|
grip_int_active {
|
|
pins = "gpio5";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x546>;
|
|
};
|
|
|
|
grip_int_suspend {
|
|
pins = "gpio5";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x547>;
|
|
};
|
|
|
|
grip_sub_int_active {
|
|
pins = "gpio6";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x548>;
|
|
};
|
|
|
|
grip_sub_int_suspend {
|
|
pins = "gpio6";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x549>;
|
|
};
|
|
|
|
cam_sensor_rear4sw_active {
|
|
pins = "gpio11";
|
|
function = "normal";
|
|
power-source = <0x01>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x581>;
|
|
};
|
|
|
|
cam_sensor_rear4sw_suspend {
|
|
pins = "gpio11";
|
|
function = "normal";
|
|
power-souce = <0x01>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x584>;
|
|
};
|
|
|
|
cam_sensor_rear4_pwr_active {
|
|
pins = "gpio12";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x582>;
|
|
};
|
|
|
|
cam_sensor_rear4_pwr_suspend {
|
|
pins = "gpio12";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x585>;
|
|
};
|
|
|
|
cam_sensor_rear4_digital_active {
|
|
pins = "gpio10";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x583>;
|
|
};
|
|
|
|
cam_sensor_rear4_digital_suspend {
|
|
pins = "gpio10";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x586>;
|
|
};
|
|
|
|
dummy_pin {
|
|
|
|
dummy_pin_default {
|
|
pins = "gpio12";
|
|
bias-disable;
|
|
phandle = <0x550>;
|
|
};
|
|
};
|
|
|
|
pwm_out_gpio6 {
|
|
|
|
pwm_out_gpio6_default {
|
|
pins = "gpio6";
|
|
function = "func1";
|
|
bias-disable;
|
|
power-source = <0x00>;
|
|
output-low;
|
|
qcom,drive-strength = <0x03>;
|
|
drive-push-pull;
|
|
phandle = <0x556>;
|
|
};
|
|
};
|
|
|
|
nfc_det_gpio {
|
|
pins = "gpio1";
|
|
function = "normal";
|
|
power-source = <0x00>;
|
|
input-enable;
|
|
bias-disable;
|
|
phandle = <0x55c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,pm6150l@5 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x05 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
|
|
qcom,lcdb@ec00 {
|
|
compatible = "qcom,qpnp-lcdb-regulator";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
reg = <0xec00 0x100>;
|
|
interrupts = <0x05 0xec 0x01 0x01>;
|
|
interrupt-names = "sc-irq";
|
|
qcom,pmic-revid = <0xa3>;
|
|
qcom,voltage-step-ramp;
|
|
status = "disabled";
|
|
phandle = <0x2e8>;
|
|
|
|
ldo {
|
|
label = "ldo";
|
|
regulator-name = "lcdb_ldo";
|
|
regulator-min-microvolt = "\0=\t";
|
|
regulator-max-microvolt = <0x5b8d80>;
|
|
phandle = <0x2e9>;
|
|
};
|
|
|
|
ncp {
|
|
label = "ncp";
|
|
regulator-name = "lcdb_ncp";
|
|
regulator-min-microvolt = "\0=\t";
|
|
regulator-max-microvolt = <0x5b8d80>;
|
|
phandle = <0x2ea>;
|
|
};
|
|
|
|
bst {
|
|
label = "bst";
|
|
regulator-name = "lcdb_bst";
|
|
regulator-min-microvolt = <0x47b760>;
|
|
regulator-max-microvolt = <0x5fbfb8>;
|
|
phandle = <0x2eb>;
|
|
};
|
|
};
|
|
|
|
qcom,leds@d300 {
|
|
compatible = "qcom,s2mu106-fled";
|
|
status = "okay";
|
|
reg = <0x74>;
|
|
label = "flash";
|
|
interrupts = <0x05 0xd3 0x00 0x01 0x05 0xd3 0x03 0x01 0x05 0xd3 0x04 0x01>;
|
|
interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq";
|
|
qcom,hdrm-auto-mode;
|
|
qcom,short-circuit-det;
|
|
qcom,open-circuit-det;
|
|
qcom,vph-droop-det;
|
|
qcom,thermal-derate-en;
|
|
qcom,thermal-derate-current = <0xc8 0x1f4 0x3e8>;
|
|
qcom,isc-delay = <0xc0>;
|
|
qcom,pmic-revid = <0xa3>;
|
|
phandle = <0x2ec>;
|
|
enable = <0x01 0x01>;
|
|
flash-gpio = <0x16c 0x16 0x00>;
|
|
torch-gpio = <0x16c 0x18 0x00>;
|
|
pinctrl-names = "fled_default\0fled_suspend";
|
|
pinctrl-0 = <0x552 0x553>;
|
|
pinctrl-1 = <0x554 0x555>;
|
|
flash_current = <0x578>;
|
|
preflash_current = <0xc8>;
|
|
torch_current = <0x12c>;
|
|
movie_current = <0xc8>;
|
|
factory_current = <0x12c>;
|
|
flashlight_current = <0x19 0x4b 0x64 0x96 0xc8>;
|
|
|
|
qcom,flash_0 {
|
|
label = "flash";
|
|
qcom,led-name = "led:flash_0";
|
|
qcom,max-current = <0x5dc>;
|
|
qcom,default-led-trigger = "flash0_trigger";
|
|
qcom,id = <0x00>;
|
|
qcom,current-ma = <0x3e8>;
|
|
qcom,duration-ms = <0x500>;
|
|
qcom,ires-ua = <0x30d4>;
|
|
qcom,hdrm-voltage-mv = <0x145>;
|
|
qcom,hdrm-vol-hi-lo-win-mv = <0x64>;
|
|
phandle = <0x2ed>;
|
|
};
|
|
|
|
qcom,flash_1 {
|
|
label = "flash";
|
|
qcom,led-name = "led:flash_1";
|
|
qcom,max-current = <0x5dc>;
|
|
qcom,default-led-trigger = "flash1_trigger";
|
|
qcom,id = <0x01>;
|
|
qcom,current-ma = <0x3e8>;
|
|
qcom,duration-ms = <0x500>;
|
|
qcom,ires-ua = <0x30d4>;
|
|
qcom,hdrm-voltage-mv = <0x145>;
|
|
qcom,hdrm-vol-hi-lo-win-mv = <0x64>;
|
|
phandle = <0x2ee>;
|
|
};
|
|
|
|
qcom,flash_2 {
|
|
label = "flash";
|
|
qcom,led-name = "led:flash_2";
|
|
qcom,max-current = <0x2ee>;
|
|
qcom,default-led-trigger = "flash2_trigger";
|
|
qcom,id = <0x02>;
|
|
qcom,current-ma = <0x1f4>;
|
|
qcom,duration-ms = <0x500>;
|
|
qcom,ires-ua = <0x30d4>;
|
|
qcom,hdrm-voltage-mv = <0x145>;
|
|
qcom,hdrm-vol-hi-lo-win-mv = <0x64>;
|
|
status = "disabled";
|
|
phandle = <0x2ef>;
|
|
};
|
|
|
|
qcom,torch_0 {
|
|
label = "torch";
|
|
qcom,led-name = "led:torch_0";
|
|
qcom,max-current = <0x1f4>;
|
|
qcom,default-led-trigger = "torch0_trigger";
|
|
qcom,id = <0x00>;
|
|
qcom,current-ma = <0x12c>;
|
|
qcom,ires-ua = <0x30d4>;
|
|
qcom,hdrm-voltage-mv = <0x145>;
|
|
qcom,hdrm-vol-hi-lo-win-mv = <0x64>;
|
|
phandle = <0x2f0>;
|
|
};
|
|
|
|
qcom,torch_1 {
|
|
label = "torch";
|
|
qcom,led-name = "led:torch_1";
|
|
qcom,max-current = <0x1f4>;
|
|
qcom,default-led-trigger = "torch1_trigger";
|
|
qcom,id = <0x01>;
|
|
qcom,current-ma = <0x12c>;
|
|
qcom,ires-ua = <0x30d4>;
|
|
qcom,hdrm-voltage-mv = <0x145>;
|
|
qcom,hdrm-vol-hi-lo-win-mv = <0x64>;
|
|
phandle = <0x2f1>;
|
|
};
|
|
|
|
qcom,torch_2 {
|
|
label = "torch";
|
|
qcom,led-name = "led:torch_2";
|
|
qcom,max-current = <0x1f4>;
|
|
qcom,default-led-trigger = "torch2_trigger";
|
|
qcom,id = <0x02>;
|
|
qcom,current-ma = <0x12c>;
|
|
qcom,ires-ua = <0x30d4>;
|
|
qcom,hdrm-voltage-mv = <0x145>;
|
|
qcom,hdrm-vol-hi-lo-win-mv = <0x64>;
|
|
status = "disabled";
|
|
phandle = <0x2f2>;
|
|
};
|
|
|
|
qcom,led_switch_0 {
|
|
label = "switch";
|
|
qcom,led-name = "led:switch_0";
|
|
qcom,led-mask = <0x01>;
|
|
qcom,default-led-trigger = "switch0_trigger";
|
|
phandle = <0x2f3>;
|
|
};
|
|
|
|
qcom,led_switch_1 {
|
|
label = "switch";
|
|
qcom,led-name = "led:switch_1";
|
|
qcom,led-mask = <0x02>;
|
|
qcom,default-led-trigger = "switch1_trigger";
|
|
phandle = <0x2f4>;
|
|
};
|
|
|
|
qcom,led_switch_2 {
|
|
label = "switch";
|
|
qcom,led-name = "led:switch_2";
|
|
qcom,led-mask = <0x03>;
|
|
qcom,default-led-trigger = "switch2_trigger";
|
|
phandle = <0x2f5>;
|
|
};
|
|
};
|
|
|
|
qcom,wled@d800 {
|
|
compatible = "qcom,pm6150l-spmi-wled";
|
|
reg = <0xd800 0x100 0xd900 0x100>;
|
|
reg-names = "wled-ctrl-base\0wled-sink-base";
|
|
label = "backlight";
|
|
interrupts = <0x05 0xd8 0x01 0x01 0x05 0xd8 0x04 0x03 0x05 0xd8 0x05 0x03>;
|
|
interrupt-names = "ovp-irq\0pre-flash-irq\0flash-irq";
|
|
qcom,pmic-revid = <0xa3>;
|
|
qcom,auto-calibration;
|
|
status = "disabled";
|
|
phandle = <0x2f6>;
|
|
|
|
qcom,wled-flash {
|
|
label = "flash";
|
|
qcom,default-led-trigger = "wled_flash";
|
|
phandle = <0x2f7>;
|
|
};
|
|
|
|
qcom,wled-torch {
|
|
label = "torch";
|
|
qcom,default-led-trigger = "wled_torch";
|
|
qcom,wled-torch-timer = <0x4b0>;
|
|
phandle = <0x2f8>;
|
|
};
|
|
|
|
qcom,wled-switch {
|
|
label = "switch";
|
|
qcom,default-led-trigger = "wled_switch";
|
|
phandle = <0x2f9>;
|
|
};
|
|
};
|
|
|
|
qcom,pwms@b100 {
|
|
compatible = "qcom,pwm-lpg";
|
|
reg = <0xb100 0x300 0xb000 0x100>;
|
|
reg-names = "lpg-base\0lut-base";
|
|
#pwm-cells = <0x02>;
|
|
qcom,num-lpg-channels = <0x03>;
|
|
qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>;
|
|
phandle = <0xa4>;
|
|
|
|
lpg1 {
|
|
qcom,lpg-chan-id = <0x01>;
|
|
qcom,ramp-step-ms = <0x64>;
|
|
qcom,ramp-pause-hi-count = <0x02>;
|
|
qcom,ramp-pause-lo-count = <0x02>;
|
|
qcom,ramp-low-index = <0x00>;
|
|
qcom,ramp-high-index = <0x14>;
|
|
qcom,ramp-from-low-to-high;
|
|
qcom,ramp-pattern-repeat;
|
|
};
|
|
|
|
lpg2 {
|
|
qcom,lpg-chan-id = <0x02>;
|
|
qcom,ramp-step-ms = <0x64>;
|
|
qcom,ramp-pause-hi-count = <0x02>;
|
|
qcom,ramp-pause-lo-count = <0x02>;
|
|
qcom,ramp-low-index = <0x00>;
|
|
qcom,ramp-high-index = <0x14>;
|
|
qcom,ramp-from-low-to-high;
|
|
qcom,ramp-pattern-repeat;
|
|
};
|
|
|
|
lpg3 {
|
|
qcom,lpg-chan-id = <0x03>;
|
|
qcom,ramp-step-ms = <0x64>;
|
|
qcom,ramp-pause-hi-count = <0x02>;
|
|
qcom,ramp-pause-lo-count = <0x02>;
|
|
qcom,ramp-low-index = <0x00>;
|
|
qcom,ramp-high-index = <0x14>;
|
|
qcom,ramp-from-low-to-high;
|
|
qcom,ramp-pattern-repeat;
|
|
};
|
|
};
|
|
|
|
qcom,pwms@bc00 {
|
|
compatible = "qcom,pwm-lpg";
|
|
reg = <0xbc00 0x200>;
|
|
reg-names = "lpg-base";
|
|
qcom,num-lpg-channels = <0x02>;
|
|
#pwm-cells = <0x02>;
|
|
phandle = <0x2fa>;
|
|
};
|
|
|
|
qcom,leds@d000 {
|
|
compatible = "qcom,tri-led";
|
|
reg = <0xd000 0x100>;
|
|
phandle = <0x2fb>;
|
|
|
|
red {
|
|
label = "red";
|
|
pwms = <0xa4 0x00 0xf4240>;
|
|
led-sources = <0x00>;
|
|
linux,default-trigger = "timer";
|
|
};
|
|
|
|
green {
|
|
label = "green";
|
|
pwms = <0xa4 0x01 0xf4240>;
|
|
led-sources = <0x01>;
|
|
linux,default-trigger = "timer";
|
|
};
|
|
|
|
blue {
|
|
label = "blue";
|
|
pwms = <0xa4 0x02 0xf4240>;
|
|
led-sources = <0x02>;
|
|
linux,default-trigger = "timer";
|
|
};
|
|
};
|
|
|
|
qcom,amoled {
|
|
compatible = "qcom,qpnp-amoled-regulator";
|
|
status = "ok";
|
|
phandle = <0x2fc>;
|
|
|
|
oledb@e000 {
|
|
reg = <0xe000 0x100>;
|
|
reg-names = "oledb_base";
|
|
regulator-name = "oledb";
|
|
regulator-min-microvolt = <0x4b2648>;
|
|
regulator-max-microvolt = <0x7b98a0>;
|
|
qcom,swire-control;
|
|
phandle = <0x2fd>;
|
|
};
|
|
|
|
ab@de00 {
|
|
reg = <0xde00 0x100>;
|
|
reg-names = "ab_base";
|
|
regulator-name = "ab";
|
|
regulator-min-microvolt = <0x4630c0>;
|
|
regulator-max-microvolt = <0x5d1420>;
|
|
qcom,swire-control;
|
|
phandle = <0x2fe>;
|
|
};
|
|
|
|
ibb@dc00 {
|
|
reg = <0xdc00 0x100>;
|
|
reg-names = "ibb_base";
|
|
regulator-name = "ibb";
|
|
regulator-min-microvolt = "\0\f5";
|
|
regulator-max-microvolt = <0x5265c0>;
|
|
qcom,swire-control;
|
|
phandle = <0x2ff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,pm8009@a {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x0a 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
status = "disabled";
|
|
|
|
qcom,revid@100 {
|
|
compatible = "qcom,qpnp-revid";
|
|
reg = <0x100 0x100>;
|
|
};
|
|
|
|
pinctrl@c000 {
|
|
compatible = "qcom,spmi-gpio";
|
|
reg = <0xc000 0x400>;
|
|
interrupts = <0x00 0xc0 0x00 0x00 0x00 0xc1 0x00 0x00 0x00 0xc3 0x00 0x00>;
|
|
interrupt-names = "pm8009_gpio1\0pm8009_gpio2\0pm8009_gpio4";
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
qcom,gpios-disallowed = <0x03>;
|
|
phandle = <0x300>;
|
|
};
|
|
};
|
|
|
|
qcom,pm8009@b {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x0b 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom,turing@8300000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0x8300000 0x100000>;
|
|
vdd_cx-supply = <0x1d>;
|
|
qcom,vdd_cx-uV-uA = <0x181 0x186a0>;
|
|
vdd_mx-supply = <0x1f>;
|
|
qcom,vdd_mx-uV-uA = <0x181 0x186a0>;
|
|
qcom,proxy-reg-names = "vdd_cx\0vdd_mx";
|
|
clocks = <0x2f 0x00>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
qcom,pas-id = <0x12>;
|
|
qcom,proxy-timeout-ms = <0x2710>;
|
|
qcom,smem-id = <0x259>;
|
|
qcom,sysmon-id = <0x07>;
|
|
qcom,ssctl-instance-id = <0x17>;
|
|
qcom,firmware-name = "cdsp";
|
|
memory-region = <0xa5>;
|
|
qcom,signal-aop;
|
|
qcom,complete-ramdump;
|
|
interrupts-extended = <0x01 0x00 0x242 0x01 0xa6 0x00 0x00 0xa6 0x01 0x00 0xa6 0x02 0x00 0xa6 0x03 0x00>;
|
|
interrupt-names = "qcom,wdog\0qcom,err-fatal\0qcom,err-ready\0qcom,proxy-unvote\0qcom,stop-ack";
|
|
qcom,smem-states = <0xa7 0x00>;
|
|
qcom,smem-state-names = "qcom,force-stop";
|
|
mboxes = <0x1c 0x00>;
|
|
mbox-names = "cdsp-pil";
|
|
};
|
|
|
|
qcom,mss@4080000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0x4080000 0x100>;
|
|
clocks = <0x2f 0x00>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
vdd_cx-supply = <0x1d>;
|
|
qcom,vdd_cx-uV-uA = <0x181 0x186a0>;
|
|
vdd_mss-supply = <0xa8>;
|
|
qcom,vdd_mss-uV-uA = <0x181 0x186a0>;
|
|
qcom,proxy-reg-names = "vdd_cx\0vdd_mss";
|
|
qcom,firmware-name = "modem";
|
|
memory-region = <0xa9>;
|
|
qcom,proxy-timeout-ms = <0x2710>;
|
|
qcom,sysmon-id = <0x00>;
|
|
qcom,ssctl-instance-id = <0x12>;
|
|
qcom,pas-id = <0x04>;
|
|
qcom,smem-id = <0x1a5>;
|
|
qcom,signal-aop;
|
|
qcom,minidump-id = <0x03>;
|
|
qcom,aux-minidump-ids = <0x04>;
|
|
qcom,complete-ramdump;
|
|
qcom,msm-bus,name = "pil-modem";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x81 0x200 0x00 0x00 0x81 0x200 0x00 0x6acfc0>;
|
|
interrupts-extended = <0x01 0x00 0x10a 0x01 0xaa 0x00 0x00 0xaa 0x01 0x00 0xaa 0x02 0x00 0xaa 0x03 0x00 0xaa 0x07 0x00>;
|
|
interrupt-names = "qcom,wdog\0qcom,err-fatal\0qcom,err-ready\0qcom,proxy-unvote\0qcom,stop-ack\0qcom,shutdown-ack";
|
|
qcom,smem-states = <0xab 0x00 0xab 0x04 0xab 0x05>;
|
|
qcom,smem-state-names = "qcom,force-stop\0qcom,stop-reason-0\0qcom,stop-reason-1";
|
|
mboxes = <0x1c 0x00>;
|
|
mbox-names = "mss-pil";
|
|
phandle = <0x301>;
|
|
};
|
|
|
|
qcom,venus@aae0000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0xaae0000 0x4000>;
|
|
vdd-supply = <0xac>;
|
|
qcom,proxy-reg-names = "vdd";
|
|
clocks = <0x28 0x0a 0x28 0x07 0x28 0x01>;
|
|
clock-names = "xo\0core\0ahb";
|
|
qcom,proxy-clock-names = "xo\0core\0ahb";
|
|
qcom,core-freq = <0xbebc200>;
|
|
qcom,ahb-freq = <0xbebc200>;
|
|
qcom,pas-id = <0x09>;
|
|
qcom,msm-bus,name = "pil-venus";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x00 0x00 0x3f 0x200 0x00 0x4a380>;
|
|
qcom,proxy-timeout-ms = <0x64>;
|
|
qcom,firmware-name = "venus";
|
|
memory-region = <0xad>;
|
|
};
|
|
|
|
qcom,npu@0x9800000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0x9800000 0x800000>;
|
|
status = "ok";
|
|
qcom,pas-id = <0x17>;
|
|
qcom,firmware-name = "npu";
|
|
memory-region = <0xae>;
|
|
};
|
|
|
|
qcom,icnss@18800000 {
|
|
compatible = "qcom,icnss";
|
|
reg = <0x18800000 0x800000 0xa0000000 0x10000000 0xb0000000 0x10000>;
|
|
reg-names = "membase\0smmu_iova_base\0smmu_iova_ipa";
|
|
iommus = <0x30 0x240 0x01>;
|
|
interrupts = <0x00 0x19e 0x00 0x00 0x19f 0x00 0x00 0x1a0 0x00 0x00 0x1a1 0x00 0x00 0x1a2 0x00 0x00 0x1a3 0x00 0x00 0x1a4 0x00 0x00 0x1a5 0x00 0x00 0x1a6 0x00 0x00 0x1a7 0x00 0x00 0x1a8 0x00 0x00 0x1a9 0x00>;
|
|
qcom,smmu-s1-bypass;
|
|
qcom,wlan-msa-memory = <0x100000>;
|
|
qcom,wlan-msa-fixed-region = <0xaf>;
|
|
vdd-cx-mx-supply = <0xb0>;
|
|
vdd-1.8-xo-supply = <0x34>;
|
|
vdd-1.3-rfa-supply = <0x32>;
|
|
vdd-3.3-ch0-supply = <0x33>;
|
|
qcom,vdd-cx-mx-config = <0x9c400 0x9c400>;
|
|
phandle = <0x302>;
|
|
vdd-3.3-ch1-supply;
|
|
|
|
qcom,smp2p_map_wlan_1_in {
|
|
interrupts-extended = <0xb1 0x00 0x00 0xb1 0x01 0x00>;
|
|
interrupt-names = "qcom,smp2p-force-fatal-error\0qcom,smp2p-early-crash-ind";
|
|
};
|
|
};
|
|
|
|
qcom,msm_gsi {
|
|
compatible = "qcom,msm_gsi";
|
|
};
|
|
|
|
qcom,rmnet-ipa {
|
|
compatible = "qcom,rmnet-ipa3";
|
|
qcom,rmnet-ipa-ssr;
|
|
qcom,ipa-platform-type-msm;
|
|
qcom,ipa-advertise-sg-support;
|
|
qcom,ipa-napi-enable;
|
|
};
|
|
|
|
qcom,ipa@1e00000 {
|
|
compatible = "qcom,ipa";
|
|
reg = <0x1e00000 0x34000 0x1e04000 0x2c000>;
|
|
reg-names = "ipa-base\0gsi-base";
|
|
interrupts = <0x00 0x137 0x00 0x00 0x1b0 0x00>;
|
|
interrupt-names = "ipa-irq\0gsi-irq";
|
|
qcom,ipa-hw-ver = <0x10>;
|
|
qcom,ipa-hw-mode = <0x00>;
|
|
qcom,ee = <0x00>;
|
|
qcom,use-ipa-tethering-bridge;
|
|
qcom,modem-cfg-emb-pipe-flt;
|
|
qcom,ipa-wdi2;
|
|
qcom,ipa-wdi2_over_gsi;
|
|
qcom,ipa-fltrt-not-hashable;
|
|
qcom,use-64-bit-dma-mask;
|
|
qcom,arm-smmu;
|
|
qcom,smmu-fast-map;
|
|
qcom,use-ipa-pm;
|
|
qcom,bandwidth-vote-for-ipa;
|
|
qcom,ipa-endp-delay-wa;
|
|
qcom,msm-bus,name = "ipa";
|
|
qcom,msm-bus,num-cases = <0x05>;
|
|
qcom,msm-bus,num-paths = <0x04>;
|
|
qcom,msm-bus,vectors-KBps = <0x5a 0x200 0x00 0x00 0x5a 0x249 0x00 0x00 0x01 0x2a4 0x00 0x00 0x8f 0x309 0x00 0x00 0x5a 0x200 0x13880 0x71868 0x5a 0x249 0x13880 0x10bda 0x01 0x2a4 0x13880 0x1e 0x8f 0x309 0x00 0x1e 0x5a 0x200 0x13880 0x1e8480 0x5a 0x249 0x13880 0x414c5 0x01 0x2a4 0x13880 0x1ad42 0x8f 0x309 0x00 0x6d 0x5a 0x200 0x324b0 0x3d0900 0x5a 0x249 0x324b0 0xae101 0x01 0x2a4 0x324b0 0x78000 0x8f 0x309 0x00 0x1eb 0x5a 0x200 0x324b0 0x556eb4 0x5a 0x249 0x324b0 0x15eb41 0x01 0x2a4 0x324b0 0x78000 0x8f 0x309 0x00 0x1eb>;
|
|
qcom,bus-vector-names = "MIN\0SVS2\0SVS\0NOMINAL\0TURBO";
|
|
qcom,throughput-threshold = <0x136 0x258 0x3e8>;
|
|
qcom,scaling-exceptions;
|
|
phandle = <0x303>;
|
|
|
|
qcom,smp2p_map_ipa_1_out {
|
|
compatible = "qcom,smp2p-map-ipa-1-out";
|
|
qcom,smem-states = <0xb2 0x00>;
|
|
qcom,smem-state-names = "ipa-smp2p-out";
|
|
};
|
|
|
|
qcom,smp2p_map_ipa_1_in {
|
|
compatible = "qcom,smp2p-map-ipa-1-in";
|
|
interrupts-extended = <0xb3 0x00 0x00>;
|
|
interrupt-names = "ipa-smp2p-in";
|
|
};
|
|
};
|
|
|
|
llcc-pmu@90cc000 {
|
|
compatible = "qcom,qcom-llcc-pmu";
|
|
reg = <0x90cc000 0x300>;
|
|
reg-names = "lagg-base";
|
|
phandle = <0x304>;
|
|
};
|
|
|
|
llcc-bw-opp-table {
|
|
compatible = "operating-points-v2";
|
|
phandle = <0xb4>;
|
|
|
|
opp-300 {
|
|
opp-hz = <0x00 0x11e1>;
|
|
};
|
|
|
|
opp-466 {
|
|
opp-hz = <0x00 0x1bc6>;
|
|
};
|
|
|
|
opp-600 {
|
|
opp-hz = <0x00 0x23c3>;
|
|
};
|
|
|
|
opp-806 {
|
|
opp-hz = <0x00 0x300a>;
|
|
};
|
|
|
|
opp-933 {
|
|
opp-hz = <0x00 0x379c>;
|
|
};
|
|
};
|
|
|
|
qcom,cpu-cpu-llcc-bw {
|
|
compatible = "qcom,devbw";
|
|
governor = "performance";
|
|
qcom,src-dst-ports = <0x01 0x302>;
|
|
qcom,active-only;
|
|
operating-points-v2 = <0xb4>;
|
|
phandle = <0xb5>;
|
|
};
|
|
|
|
qcom,cpu-cpu-llcc-bwmon@90b6300 {
|
|
compatible = "qcom,bimc-bwmon4";
|
|
reg = <0x90b6300 0x300 0x90b6200 0x200>;
|
|
reg-names = "base\0global_base";
|
|
interrupts = <0x00 0x245 0x04>;
|
|
qcom,mport = <0x00>;
|
|
qcom,hw-timer-hz = <0x124f800>;
|
|
qcom,target-dev = <0xb5>;
|
|
qcom,count-unit = <0x10000>;
|
|
phandle = <0x305>;
|
|
};
|
|
|
|
ddr-bw-opp-table {
|
|
compatible = "operating-points-v2";
|
|
phandle = <0xb6>;
|
|
|
|
opp-200 {
|
|
opp-hz = <0x00 0x2fa>;
|
|
};
|
|
|
|
opp-300 {
|
|
opp-hz = <0x00 0x478>;
|
|
};
|
|
|
|
opp-451 {
|
|
opp-hz = <0x00 0x6b8>;
|
|
};
|
|
|
|
opp-547 {
|
|
opp-hz = <0x00 0x826>;
|
|
};
|
|
|
|
opp-681 {
|
|
opp-hz = <0x00 0xa25>;
|
|
};
|
|
|
|
opp-768 {
|
|
opp-hz = <0x00 0xb71>;
|
|
};
|
|
|
|
opp-1017 {
|
|
opp-hz = <0x00 0xf27>;
|
|
};
|
|
|
|
opp-1353 {
|
|
opp-hz = <0x00 0x1429>;
|
|
};
|
|
|
|
opp-1555 {
|
|
opp-hz = <0x00 0x172b>;
|
|
};
|
|
|
|
opp-1804 {
|
|
opp-hz = <0x00 0x1ae1>;
|
|
};
|
|
};
|
|
|
|
qcom,cpu-llcc-ddr-bw {
|
|
compatible = "qcom,devbw";
|
|
governor = "performance";
|
|
qcom,src-dst-ports = <0x81 0x200>;
|
|
qcom,active-only;
|
|
operating-points-v2 = <0xb6>;
|
|
phandle = <0xb7>;
|
|
};
|
|
|
|
qcom,cpu-llcc-ddr-bwmon@90cd000 {
|
|
compatible = "qcom,bimc-bwmon5";
|
|
reg = <0x90cd000 0x1000>;
|
|
reg-names = "base";
|
|
interrupts = <0x00 0x51 0x04>;
|
|
qcom,hw-timer-hz = <0x124f800>;
|
|
qcom,target-dev = <0xb7>;
|
|
qcom,count-unit = <0x10000>;
|
|
phandle = <0x306>;
|
|
};
|
|
|
|
suspendable-ddr-bw-opp-table {
|
|
compatible = "operating-points-v2";
|
|
phandle = <0xbf>;
|
|
|
|
opp-0 {
|
|
opp-hz = <0x00 0x00>;
|
|
};
|
|
|
|
opp-200 {
|
|
opp-hz = <0x00 0x2fa>;
|
|
};
|
|
|
|
opp-300 {
|
|
opp-hz = <0x00 0x478>;
|
|
};
|
|
|
|
opp-451 {
|
|
opp-hz = <0x00 0x6b8>;
|
|
};
|
|
|
|
opp-547 {
|
|
opp-hz = <0x00 0x826>;
|
|
};
|
|
|
|
opp-681 {
|
|
opp-hz = <0x00 0xa25>;
|
|
};
|
|
|
|
opp-768 {
|
|
opp-hz = <0x00 0xb71>;
|
|
};
|
|
|
|
opp-1017 {
|
|
opp-hz = <0x00 0xf27>;
|
|
};
|
|
|
|
opp-1353 {
|
|
opp-hz = <0x00 0x1429>;
|
|
};
|
|
|
|
opp-1555 {
|
|
opp-hz = <0x00 0x172b>;
|
|
};
|
|
|
|
opp-1804 {
|
|
opp-hz = <0x00 0x1ae1>;
|
|
};
|
|
};
|
|
|
|
qcom,cdsp-cdsp-l3-lat {
|
|
compatible = "devfreq-simple-dev";
|
|
clock-names = "devfreq_clk";
|
|
clocks = <0xb8 0x03>;
|
|
governor = "powersave";
|
|
phandle = <0x26>;
|
|
};
|
|
|
|
qcom,cpu0-cpu-l3-lat {
|
|
compatible = "devfreq-simple-dev";
|
|
clock-names = "devfreq_clk";
|
|
clocks = <0xb8 0x00>;
|
|
governor = "performance";
|
|
phandle = <0x24>;
|
|
};
|
|
|
|
qcom,cpu0-cpu-l3-latmon {
|
|
compatible = "qcom,arm-memlat-mon";
|
|
qcom,cpulist = <0x11 0x12 0x13 0x14 0x15 0x16>;
|
|
qcom,target-dev = <0x24>;
|
|
qcom,cachemiss-ev = <0x17>;
|
|
qcom,core-dev-table = <0xbb800 0x11e1a300 0xf8700 0x21301800 0x130b00 0x2dc6c000 0x16d7a8 0x38137800 0x1b8a00 0x56f9a000>;
|
|
phandle = <0x307>;
|
|
};
|
|
|
|
qcom,cpu6-cpu-l3-lat {
|
|
compatible = "devfreq-simple-dev";
|
|
clock-names = "devfreq_clk";
|
|
clocks = <0xb8 0x01>;
|
|
governor = "performance";
|
|
phandle = <0x25>;
|
|
};
|
|
|
|
qcom,cpu6-cpu-l3-latmon {
|
|
compatible = "qcom,arm-memlat-mon";
|
|
qcom,cpulist = <0x17 0x18>;
|
|
qcom,target-dev = <0x25>;
|
|
qcom,cachemiss-ev = <0x17>;
|
|
qcom,core-dev-table = <0x10b170 0x21301800 0x1433e0 0x2dc6c000 0x1a1300 0x46f41000 0x1d9638 0x5265c000 0x253500 0x56f9a000>;
|
|
phandle = <0x308>;
|
|
};
|
|
|
|
qcom,cpu0-cpu-llcc-lat {
|
|
compatible = "qcom,devbw";
|
|
governor = "performance";
|
|
qcom,src-dst-ports = <0x01 0x302>;
|
|
qcom,active-only;
|
|
operating-points-v2 = <0xb4>;
|
|
phandle = <0xb9>;
|
|
};
|
|
|
|
qcom,cpu0-cpu-llcc-latmon {
|
|
compatible = "qcom,arm-memlat-mon";
|
|
qcom,cpulist = <0x11 0x12 0x13 0x14 0x15 0x16>;
|
|
qcom,target-dev = <0xb9>;
|
|
qcom,cachemiss-ev = <0x2a>;
|
|
qcom,core-dev-table = <0x1433e0 0x11e1 0x16d7a8 0x1bc6 0x1b8a00 0x23c3>;
|
|
phandle = <0x309>;
|
|
};
|
|
|
|
qcom,cpu6-cpu-llcc-lat {
|
|
compatible = "qcom,devbw";
|
|
governor = "performance";
|
|
qcom,src-dst-ports = <0x01 0x302>;
|
|
qcom,active-only;
|
|
operating-points-v2 = <0xb4>;
|
|
phandle = <0xba>;
|
|
};
|
|
|
|
qcom,cpu6-cpu-llcc-latmon {
|
|
compatible = "qcom,arm-memlat-mon";
|
|
qcom,cpulist = <0x17 0x18>;
|
|
qcom,target-dev = <0xba>;
|
|
qcom,cachemiss-ev = <0x2a>;
|
|
qcom,core-dev-table = <0xc4c70 0x11e1 0x10b170 0x1bc6 0x1433e0 0x23c3 0x1a1300 0x300a 0x253500 0x379c>;
|
|
phandle = <0x30a>;
|
|
};
|
|
|
|
qcom,cpu0-llcc-ddr-lat {
|
|
compatible = "qcom,devbw";
|
|
governor = "performance";
|
|
qcom,src-dst-ports = <0x81 0x200>;
|
|
qcom,active-only;
|
|
operating-points-v2 = <0xb6>;
|
|
phandle = <0xbb>;
|
|
};
|
|
|
|
qcom,cpu0-llcc-ddr-latmon {
|
|
compatible = "qcom,arm-memlat-mon";
|
|
qcom,cpulist = <0x11 0x12 0x13 0x14 0x15 0x16>;
|
|
qcom,target-dev = <0xbb>;
|
|
qcom,cachemiss-ev = <0x1000>;
|
|
qcom,core-dev-table = <0xbb800 0x478 0xf8700 0x6b8 0x130b00 0x826 0x16d7a8 0xb71 0x1b8a00 0xf27>;
|
|
phandle = <0x30b>;
|
|
};
|
|
|
|
qcom,cpu6-llcc-ddr-lat {
|
|
compatible = "qcom,devbw";
|
|
governor = "performance";
|
|
qcom,src-dst-ports = <0x81 0x200>;
|
|
qcom,active-only;
|
|
operating-points-v2 = <0xb6>;
|
|
phandle = <0xbc>;
|
|
};
|
|
|
|
qcom,cpu6-llcc-ddr-latmon {
|
|
compatible = "qcom,arm-memlat-mon";
|
|
qcom,cpulist = <0x17 0x18>;
|
|
qcom,target-dev = <0xbc>;
|
|
qcom,cachemiss-ev = <0x1000>;
|
|
qcom,core-dev-table = <0xc4c70 0x6b8 0x10b170 0x826 0x1433e0 0xf27 0x1a1300 0x172b 0x253500 0x1ae1>;
|
|
phandle = <0x30c>;
|
|
};
|
|
|
|
qcom,cpu0-cpu-ddr-latfloor {
|
|
compatible = "qcom,devbw";
|
|
governor = "performance";
|
|
qcom,src-dst-ports = <0x81 0x200>;
|
|
qcom,active-only;
|
|
operating-points-v2 = <0xb6>;
|
|
phandle = <0xbd>;
|
|
};
|
|
|
|
qcom,cpu0-computemon {
|
|
compatible = "qcom,arm-cpu-mon";
|
|
qcom,cpulist = <0x11 0x12 0x13 0x14 0x15 0x16>;
|
|
qcom,target-dev = <0xbd>;
|
|
qcom,core-dev-table = <0xbb800 0x478 0x130b00 0x6b8 0x16d7a8 0x826 0x1b8a00 0xb71>;
|
|
phandle = <0x30d>;
|
|
};
|
|
|
|
qcom,cpu6-cpu-ddr-latfloor {
|
|
compatible = "qcom,devbw";
|
|
governor = "performance";
|
|
qcom,src-dst-ports = <0x81 0x200>;
|
|
qcom,active-only;
|
|
operating-points-v2 = <0xb6>;
|
|
phandle = <0xbe>;
|
|
};
|
|
|
|
qcom,cpu6-computemon {
|
|
compatible = "qcom,arm-cpu-mon";
|
|
qcom,cpulist = <0x17 0x18>;
|
|
qcom,target-dev = <0xbe>;
|
|
qcom,core-dev-table = <0x10b170 0x478 0x1433e0 0x826 0x17af48 0xb71 0x1a0fe0 0xf27 0x253500 0x1ae1>;
|
|
phandle = <0x30e>;
|
|
};
|
|
|
|
qcom,npu-npu-ddr-bw {
|
|
compatible = "qcom,devbw";
|
|
governor = "performance";
|
|
qcom,src-dst-ports = <0x9a 0x200>;
|
|
operating-points-v2 = <0xbf>;
|
|
phandle = <0xc0>;
|
|
};
|
|
|
|
qcom,npu-npu-ddr-bwmon@9960300 {
|
|
compatible = "qcom,bimc-bwmon4";
|
|
reg = <0x9960300 0x300 0x9960200 0x200>;
|
|
reg-names = "base\0global_base";
|
|
interrupts = <0x00 0x16d 0x04>;
|
|
qcom,mport = <0x00>;
|
|
qcom,hw-timer-hz = <0x124f800>;
|
|
qcom,target-dev = <0xc0>;
|
|
qcom,count-unit = <0x10000>;
|
|
phandle = <0x30f>;
|
|
};
|
|
|
|
ipa_smmu_ap {
|
|
compatible = "qcom,ipa-smmu-ap-cb";
|
|
qcom,smmu-s1-bypass;
|
|
iommus = <0x30 0x520 0x00>;
|
|
qcom,iova-mapping = <0x20000000 0x40000000>;
|
|
qcom,additional-mapping = <0x146a8000 0x146a8000 0x2000>;
|
|
phandle = <0x310>;
|
|
};
|
|
|
|
ipa_smmu_wlan {
|
|
compatible = "qcom,ipa-smmu-wlan-cb";
|
|
qcom,smmu-s1-bypass;
|
|
iommus = <0x30 0x521 0x00>;
|
|
qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>;
|
|
phandle = <0x311>;
|
|
};
|
|
|
|
ipa_smmu_uc {
|
|
compatible = "qcom,ipa-smmu-uc-cb";
|
|
qcom,smmu-s1-bypass;
|
|
iommus = <0x30 0x522 0x00>;
|
|
qcom,iova-mapping = <0x40400000 0x1fc00000>;
|
|
phandle = <0x312>;
|
|
};
|
|
|
|
qcom,ipa_fws {
|
|
compatible = "qcom,pil-tz-generic";
|
|
qcom,pas-id = <0x0f>;
|
|
qcom,firmware-name = "ipa_fws";
|
|
qcom,pil-force-shutdown;
|
|
memory-region = <0xc1>;
|
|
};
|
|
|
|
keepalive-opp-table {
|
|
compatible = "operating-points-v2";
|
|
phandle = <0xc2>;
|
|
|
|
opp-1 {
|
|
opp-hz = <0x00 0x01>;
|
|
};
|
|
};
|
|
|
|
qcom,snoc_cnoc_keepalive {
|
|
compatible = "qcom,devbw";
|
|
governor = "powersave";
|
|
qcom,src-dst-ports = <0x01 0x273>;
|
|
qcom,active-only;
|
|
status = "ok";
|
|
operating-points-v2 = <0xc2>;
|
|
phandle = <0x313>;
|
|
};
|
|
|
|
qcom,bus_proxy_client {
|
|
compatible = "qcom,bus-proxy-client";
|
|
qcom,msm-bus,name = "bus-proxy-client";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x16 0x200 0x00 0x4c4b40>;
|
|
qcom,msm-bus,active-only;
|
|
status = "ok";
|
|
phandle = <0x314>;
|
|
};
|
|
|
|
demux {
|
|
compatible = "qcom,demux";
|
|
};
|
|
|
|
cx_ipeak@01fed000 {
|
|
compatible = "qcom,cx-ipeak-v2";
|
|
reg = <0x1fed000 0x8008>;
|
|
phandle = <0x19b>;
|
|
};
|
|
|
|
qcom,gdsc@16b004 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "pcie_0_gdsc";
|
|
reg = <0x16b004 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
status = "ok";
|
|
phandle = <0x315>;
|
|
};
|
|
|
|
qcom,gdsc@177004 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "ufs_phy_gdsc";
|
|
reg = <0x177004 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
status = "ok";
|
|
phandle = <0x91>;
|
|
};
|
|
|
|
qcom,gdsc@10f004 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "usb30_prim_gdsc";
|
|
reg = <0x10f004 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
status = "ok";
|
|
phandle = <0x251>;
|
|
};
|
|
|
|
qcom,gdsc@17d030 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";
|
|
reg = <0x17d030 0x04>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <0x1f4>;
|
|
status = "ok";
|
|
phandle = <0x1c3>;
|
|
};
|
|
|
|
qcom,gdsc@17d03c {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";
|
|
reg = <0x17d03c 0x04>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <0x1f4>;
|
|
status = "ok";
|
|
phandle = <0x1c4>;
|
|
};
|
|
|
|
qcom,gdsc@17d034 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";
|
|
reg = <0x17d034 0x04>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <0x1f4>;
|
|
status = "ok";
|
|
phandle = <0x1be>;
|
|
};
|
|
|
|
qcom,gdsc@17d038 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";
|
|
reg = <0x17d038 0x04>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <0x1f4>;
|
|
status = "ok";
|
|
phandle = <0x1bf>;
|
|
};
|
|
|
|
qcom,gdsc@17d040 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
|
|
reg = <0x17d040 0x04>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <0x1f4>;
|
|
status = "ok";
|
|
phandle = <0x1c0>;
|
|
};
|
|
|
|
qcom,gdsc@17d048 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
|
|
reg = <0x17d048 0x04>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <0x1f4>;
|
|
status = "ok";
|
|
phandle = <0x1c1>;
|
|
};
|
|
|
|
qcom,gdsc@17d044 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
|
|
reg = <0x17d044 0x04>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <0x1f4>;
|
|
status = "ok";
|
|
phandle = <0x1c2>;
|
|
};
|
|
|
|
qcom,gdsc@ad07004 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "bps_gdsc";
|
|
reg = <0xad07004 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
status = "ok";
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x0e>;
|
|
qcom,support-hw-trigger;
|
|
phandle = <0x1b3>;
|
|
};
|
|
|
|
qcom,gdsc@ad0a004 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "ife_0_gdsc";
|
|
reg = <0xad0a004 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
status = "ok";
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x0e>;
|
|
phandle = <0x1af>;
|
|
};
|
|
|
|
qcom,gdsc@ad0b004 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "ife_1_gdsc";
|
|
reg = <0xad0b004 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
status = "ok";
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x0e>;
|
|
phandle = <0x1b0>;
|
|
};
|
|
|
|
qcom,gdsc@ad08004 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "ipe_0_gdsc";
|
|
reg = <0xad08004 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
status = "ok";
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x0e>;
|
|
qcom,support-hw-trigger;
|
|
phandle = <0x1b1>;
|
|
};
|
|
|
|
qcom,gdsc@ad09004 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "ipe_1_gdsc";
|
|
reg = <0xad09004 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
status = "ok";
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x0e>;
|
|
qcom,support-hw-trigger;
|
|
phandle = <0x1b2>;
|
|
};
|
|
|
|
qcom,gdsc@ad0c1c4 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "titan_top_gdsc";
|
|
reg = <0xad0c1c4 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
status = "ok";
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x0e>;
|
|
phandle = <0x1a6>;
|
|
};
|
|
|
|
qcom,gdsc@0f03000 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "mdss_core_gdsc";
|
|
reg = <0xaf03000 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
proxy-supply = <0xc3>;
|
|
qcom,proxy-consumer-enable;
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x1c>;
|
|
phandle = <0xc3>;
|
|
};
|
|
|
|
syscon@5091540 {
|
|
compatible = "syscon";
|
|
reg = <0x5091540 0x04>;
|
|
phandle = <0xc4>;
|
|
};
|
|
|
|
syscon@0x5091508 {
|
|
compatible = "syscon";
|
|
reg = <0x5091508 0x04>;
|
|
phandle = <0xc5>;
|
|
};
|
|
|
|
syscon@0x5091008 {
|
|
compatible = "syscon";
|
|
reg = <0x5091008 0x04>;
|
|
phandle = <0xc6>;
|
|
};
|
|
|
|
qcom,gdsc@509106c {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "gpu_cx_gdsc";
|
|
reg = <0x509106c 0x04>;
|
|
hw-ctrl-addr = <0xc4>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <0x1f4>;
|
|
qcom,clk-dis-wait-val = <0x08>;
|
|
status = "ok";
|
|
parent-supply = <0x1d>;
|
|
phandle = <0x1bd>;
|
|
};
|
|
|
|
qcom,gdsc@509100c {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "gpu_gx_gdsc";
|
|
reg = <0x509100c 0x04>;
|
|
qcom,poll-cfg-gdscr;
|
|
domain-addr = <0xc5>;
|
|
sw-reset = <0xc6>;
|
|
status = "ok";
|
|
clock-names = "core_root_clk";
|
|
clocks = <0x2b 0x12>;
|
|
qcom,force-enable-root-clk;
|
|
parent-supply = <0x20>;
|
|
qcom,reset-aon-logic;
|
|
phandle = <0x246>;
|
|
};
|
|
|
|
qcom,gdsc@0b00814 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "mvsc_gdsc";
|
|
reg = <0xab00814 0x04>;
|
|
status = "ok";
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x9b>;
|
|
phandle = <0xac>;
|
|
};
|
|
|
|
qcom,gdsc@ab00874 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "mvs0_gdsc";
|
|
reg = <0xab00874 0x04>;
|
|
status = "ok";
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x9b>;
|
|
qcom,support-hw-trigger;
|
|
phandle = <0x199>;
|
|
};
|
|
|
|
qcom,gdsc@ab008b4 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "mvs1_gdsc";
|
|
reg = <0xab008b4 0x04>;
|
|
status = "ok";
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x9b>;
|
|
qcom,support-hw-trigger;
|
|
phandle = <0x19a>;
|
|
};
|
|
|
|
qcom,gdsc@9911028 {
|
|
compatible = "qcom,gdsc";
|
|
regulator-name = "npu_core_gdsc";
|
|
reg = <0x9911028 0x04>;
|
|
status = "ok";
|
|
clock-names = "ahb_clk";
|
|
clocks = <0x27 0x2f>;
|
|
phandle = <0x23>;
|
|
};
|
|
|
|
ad-hoc-bus {
|
|
compatible = "qcom,msm-bus-device";
|
|
reg = <0x16e0000 0x11080 0x1700000 0x1f080 0x1500000 0x28000 0x9160000 0x3200 0x9680000 0x3e200 0x1380000 0x40000 0x1740000 0x1c100 0x1620000 0x18080 0x1620000 0x40000 0x1620000 0x40000 0x80a8000 0x1400>;
|
|
reg-names = "aggre1_noc-base\0aggre2_noc-base\0config_noc-base\0dc_noc-base\0gem_noc-base\0mc_virt-base\0mmss_noc-base\0system_noc-base\0ipa_virt-base\0camnoc_virt-base\0compute_noc-base";
|
|
mbox-names = "apps_rsc\0disp_rsc";
|
|
mboxes = <0x1b 0x00 0xc7 0x00>;
|
|
phandle = <0x316>;
|
|
|
|
rsc-apps {
|
|
cell-id = <0x1f40>;
|
|
label = "apps_rsc";
|
|
qcom,rsc-dev;
|
|
qcom,req_state = <0x02>;
|
|
phandle = <0xc8>;
|
|
};
|
|
|
|
rsc-disp {
|
|
cell-id = <0x1f41>;
|
|
label = "disp_rsc";
|
|
qcom,rsc-dev;
|
|
qcom,req_state = <0x02>;
|
|
phandle = <0xc9>;
|
|
};
|
|
|
|
bcm-acv {
|
|
cell-id = <0x1b7e>;
|
|
label = "ACV";
|
|
qcom,bcm-name = "ACV";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x14a>;
|
|
};
|
|
|
|
bcm-alc {
|
|
cell-id = <0x1b7f>;
|
|
label = "ALC";
|
|
qcom,bcm-name = "ALC";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x12d>;
|
|
};
|
|
|
|
bcm-mc0 {
|
|
cell-id = <0x1b58>;
|
|
label = "MC0";
|
|
qcom,bcm-name = "MC0";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x149>;
|
|
};
|
|
|
|
bcm-sh0 {
|
|
cell-id = <0x1b5b>;
|
|
label = "SH0";
|
|
qcom,bcm-name = "SH0";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x147>;
|
|
};
|
|
|
|
bcm-mm0 {
|
|
cell-id = <0x1b63>;
|
|
label = "MM0";
|
|
qcom,bcm-name = "MM0";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x14d>;
|
|
};
|
|
|
|
bcm-mm1 {
|
|
cell-id = <0x1b64>;
|
|
label = "MM1";
|
|
qcom,bcm-name = "MM1";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0xd6>;
|
|
};
|
|
|
|
bcm-sh2 {
|
|
cell-id = <0x1b5d>;
|
|
label = "SH2";
|
|
qcom,bcm-name = "SH2";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x145>;
|
|
};
|
|
|
|
bcm-sh3 {
|
|
cell-id = <0x1b5e>;
|
|
label = "SH3";
|
|
qcom,bcm-name = "SH3";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x112>;
|
|
};
|
|
|
|
bcm-mm2 {
|
|
cell-id = <0x1b65>;
|
|
label = "MM2";
|
|
qcom,bcm-name = "MM2";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x11d>;
|
|
};
|
|
|
|
bcm-mm3 {
|
|
cell-id = <0x1b66>;
|
|
label = "MM3";
|
|
qcom,bcm-name = "MM3";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x11e>;
|
|
};
|
|
|
|
bcm-sh5 {
|
|
cell-id = <0x1b60>;
|
|
label = "SH5";
|
|
qcom,bcm-name = "SH5";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x111>;
|
|
};
|
|
|
|
bcm-sn0 {
|
|
cell-id = <0x1b6a>;
|
|
label = "SN0";
|
|
qcom,bcm-name = "SN0";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x152>;
|
|
};
|
|
|
|
bcm-sh8 {
|
|
cell-id = <0x1b8c>;
|
|
label = "SH8";
|
|
qcom,bcm-name = "SH8";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x13c>;
|
|
};
|
|
|
|
bcm-sh10 {
|
|
cell-id = <0x1b8e>;
|
|
label = "SH10";
|
|
qcom,bcm-name = "SH10";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0xd9>;
|
|
};
|
|
|
|
bcm-ce0 {
|
|
cell-id = <0x1b7a>;
|
|
label = "CE0";
|
|
qcom,bcm-name = "CE0";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0xd2>;
|
|
};
|
|
|
|
bcm-ip0 {
|
|
cell-id = <0x1b7b>;
|
|
label = "IP0";
|
|
qcom,bcm-name = "IP0";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x148>;
|
|
};
|
|
|
|
bcm-cn0 {
|
|
cell-id = <0x1b7c>;
|
|
label = "CN0";
|
|
qcom,bcm-name = "CN0";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0xce>;
|
|
};
|
|
|
|
bcm-qup0 {
|
|
cell-id = <0x1b80>;
|
|
label = "QUP0";
|
|
qcom,bcm-name = "QUP0";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0xcd>;
|
|
};
|
|
|
|
bcm-sn1 {
|
|
cell-id = <0x1b6b>;
|
|
label = "SN1";
|
|
qcom,bcm-name = "SN1";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x153>;
|
|
};
|
|
|
|
bcm-sn2 {
|
|
cell-id = <0x1b6c>;
|
|
label = "SN2";
|
|
qcom,bcm-name = "SN2";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x150>;
|
|
};
|
|
|
|
bcm-sn4 {
|
|
cell-id = <0x1b6e>;
|
|
label = "SN4";
|
|
qcom,bcm-name = "SN4";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x154>;
|
|
};
|
|
|
|
bcm-sn9 {
|
|
cell-id = <0x1b73>;
|
|
label = "SN9";
|
|
qcom,bcm-name = "SN9";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x127>;
|
|
};
|
|
|
|
bcm-sn11 {
|
|
cell-id = <0x1b75>;
|
|
label = "SN11";
|
|
qcom,bcm-name = "SN11";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x129>;
|
|
};
|
|
|
|
bcm-sn12 {
|
|
cell-id = <0x1b76>;
|
|
label = "SN12";
|
|
qcom,bcm-name = "SN12";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x12c>;
|
|
};
|
|
|
|
bcm-sn14 {
|
|
cell-id = <0x1b78>;
|
|
label = "SN14";
|
|
qcom,bcm-name = "SN14";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x13a>;
|
|
};
|
|
|
|
bcm-sn15 {
|
|
cell-id = <0x1b79>;
|
|
label = "SN15";
|
|
qcom,bcm-name = "SN15";
|
|
qcom,rscs = <0xc8>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x12a>;
|
|
};
|
|
|
|
bcm-acv_display {
|
|
cell-id = <0x697e>;
|
|
label = "ACV_DISPLAY";
|
|
qcom,bcm-name = "ACV";
|
|
qcom,rscs = <0xc9>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x158>;
|
|
};
|
|
|
|
bcm-alc_display {
|
|
cell-id = <0x697f>;
|
|
label = "ALC_DISPLAY";
|
|
qcom,bcm-name = "ALC";
|
|
qcom,rscs = <0xc9>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x317>;
|
|
};
|
|
|
|
bcm-mc0_display {
|
|
cell-id = <0x6978>;
|
|
label = "MC0_DISPLAY";
|
|
qcom,bcm-name = "MC0";
|
|
qcom,rscs = <0xc9>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x157>;
|
|
};
|
|
|
|
bcm-sh0_display {
|
|
cell-id = <0x6979>;
|
|
label = "SH0_DISPLAY";
|
|
qcom,bcm-name = "SH0";
|
|
qcom,rscs = <0xc9>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x156>;
|
|
};
|
|
|
|
bcm-mm0_display {
|
|
cell-id = <0x697a>;
|
|
label = "MM0_DISPLAY";
|
|
qcom,bcm-name = "MM0";
|
|
qcom,rscs = <0xc9>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x15c>;
|
|
};
|
|
|
|
bcm-mm1_display {
|
|
cell-id = <0x697b>;
|
|
label = "MM1_DISPLAY";
|
|
qcom,bcm-name = "MM1";
|
|
qcom,rscs = <0xc9>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x134>;
|
|
};
|
|
|
|
bcm-mm2_display {
|
|
cell-id = <0x697c>;
|
|
label = "MM2_DISPLAY";
|
|
qcom,bcm-name = "MM2";
|
|
qcom,rscs = <0xc9>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x15a>;
|
|
};
|
|
|
|
bcm-mm3_display {
|
|
cell-id = <0x697d>;
|
|
label = "MM3_DISPLAY";
|
|
qcom,bcm-name = "MM3";
|
|
qcom,rscs = <0xc9>;
|
|
qcom,bcm-dev;
|
|
phandle = <0x136>;
|
|
};
|
|
|
|
fab-aggre1_noc {
|
|
cell-id = <0x1802>;
|
|
label = "fab-aggre1_noc";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "aggre1_noc-base";
|
|
qcom,qos-off = <0x1000>;
|
|
qcom,base-offset = <0x4000>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bus-type = <0x01>;
|
|
clocks;
|
|
phandle = <0xcb>;
|
|
};
|
|
|
|
fab-aggre2_noc {
|
|
cell-id = <0x1803>;
|
|
label = "fab-aggre2_noc";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "aggre2_noc-base";
|
|
qcom,qos-off = <0x1000>;
|
|
qcom,base-offset = <0x5000>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bus-type = <0x01>;
|
|
clocks;
|
|
phandle = <0xd0>;
|
|
};
|
|
|
|
fab-camnoc_virt {
|
|
cell-id = <0x180a>;
|
|
label = "fab-camnoc_virt";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "camnoc_virt-base";
|
|
qcom,qos-off = <0x00>;
|
|
qcom,base-offset = <0x00>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bypass-qos-prg;
|
|
clocks;
|
|
phandle = <0xd5>;
|
|
};
|
|
|
|
fab-compute_noc {
|
|
cell-id = <0x180b>;
|
|
label = "fab-compute_noc";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "compute_noc-base";
|
|
qcom,qos-off = <0x1000>;
|
|
qcom,base-offset = <0x00>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bypass-qos-prg;
|
|
qcom,bus-type = <0x01>;
|
|
clocks;
|
|
phandle = <0xd8>;
|
|
};
|
|
|
|
fab-config_noc {
|
|
cell-id = <0x1400>;
|
|
label = "fab-config_noc";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "config_noc-base";
|
|
qcom,qos-off = <0x00>;
|
|
qcom,base-offset = <0x00>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bypass-qos-prg;
|
|
qcom,bus-type = <0x01>;
|
|
clocks;
|
|
phandle = <0xdb>;
|
|
};
|
|
|
|
fab-dc_noc {
|
|
cell-id = <0x1806>;
|
|
label = "fab-dc_noc";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "dc_noc-base";
|
|
qcom,qos-off = <0x00>;
|
|
qcom,base-offset = <0x00>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bypass-qos-prg;
|
|
qcom,bus-type = <0x01>;
|
|
clocks;
|
|
phandle = <0x10d>;
|
|
};
|
|
|
|
fab-gem_noc {
|
|
cell-id = <0x180c>;
|
|
label = "fab-gem_noc";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "gem_noc-base";
|
|
qcom,qos-off = <0x80>;
|
|
qcom,base-offset = <0x2b000>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bus-type = <0x01>;
|
|
clocks;
|
|
phandle = <0x110>;
|
|
};
|
|
|
|
fab-ipa_virt {
|
|
cell-id = <0x1809>;
|
|
label = "fab-ipa_virt";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "ipa_virt-base";
|
|
qcom,qos-off = <0x00>;
|
|
qcom,base-offset = <0x00>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bypass-qos-prg;
|
|
clocks;
|
|
phandle = <0x116>;
|
|
};
|
|
|
|
fab-mc_virt {
|
|
cell-id = <0x1807>;
|
|
label = "fab-mc_virt";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "mc_virt-base";
|
|
qcom,qos-off = <0x00>;
|
|
qcom,base-offset = <0x00>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bypass-qos-prg;
|
|
clocks;
|
|
phandle = <0x118>;
|
|
};
|
|
|
|
fab-mmss_noc {
|
|
cell-id = <0x800>;
|
|
label = "fab-mmss_noc";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "mmss_noc-base";
|
|
qcom,qos-off = <0x80>;
|
|
qcom,base-offset = <0x9000>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bus-type = <0x01>;
|
|
clocks;
|
|
phandle = <0x11a>;
|
|
};
|
|
|
|
fab-system_noc {
|
|
cell-id = <0x400>;
|
|
label = "fab-system_noc";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "system_noc-base";
|
|
qcom,qos-off = <0x1000>;
|
|
qcom,base-offset = <0xa000>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bus-type = <0x01>;
|
|
clocks;
|
|
phandle = <0x120>;
|
|
};
|
|
|
|
fab-gem_noc_display {
|
|
cell-id = <0x6593>;
|
|
label = "fab-gem_noc_display";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "gem_noc-base";
|
|
qcom,qos-off = <0x80>;
|
|
qcom,base-offset = <0x2b000>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bypass-qos-prg;
|
|
qcom,bus-type = <0x01>;
|
|
clocks;
|
|
phandle = <0x12f>;
|
|
};
|
|
|
|
fab-mc_virt_display {
|
|
cell-id = <0x6590>;
|
|
label = "fab-mc_virt_display";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "mc_virt-base";
|
|
qcom,qos-off = <0x00>;
|
|
qcom,base-offset = <0x00>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bypass-qos-prg;
|
|
clocks;
|
|
phandle = <0x131>;
|
|
};
|
|
|
|
fab-mmss_noc_display {
|
|
cell-id = <0x6592>;
|
|
label = "fab-mmss_noc_display";
|
|
qcom,fab-dev;
|
|
qcom,base-name = "mmss_noc-base";
|
|
qcom,qos-off = <0x80>;
|
|
qcom,base-offset = <0x9000>;
|
|
qcom,sbm-offset = <0x00>;
|
|
qcom,bypass-qos-prg;
|
|
qcom,bus-type = <0x01>;
|
|
clocks;
|
|
phandle = <0x133>;
|
|
};
|
|
|
|
mas-qhm-a1noc-cfg {
|
|
cell-id = <0x79>;
|
|
label = "mas-qhm-a1noc-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0xca>;
|
|
qcom,bus-dev = <0xcb>;
|
|
phandle = <0x13d>;
|
|
};
|
|
|
|
mas-qhm-qup-center {
|
|
cell-id = <0x97>;
|
|
label = "mas-qhm-qup-center";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x05>;
|
|
qcom,connections = <0xcc>;
|
|
qcom,bus-dev = <0xcb>;
|
|
qcom,bcms = <0xcd>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x318>;
|
|
};
|
|
|
|
mas-qhm-tsif {
|
|
cell-id = <0x52>;
|
|
label = "mas-qhm-tsif";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0xcc>;
|
|
qcom,bus-dev = <0xcb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x319>;
|
|
};
|
|
|
|
mas-xm-emmc {
|
|
cell-id = <0x96>;
|
|
label = "mas-xm-emmc";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x03>;
|
|
qcom,connections = <0xcc>;
|
|
qcom,bus-dev = <0xcb>;
|
|
qcom,bcms = <0xce>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x31a>;
|
|
};
|
|
|
|
mas-xm-sdc2 {
|
|
cell-id = <0x51>;
|
|
label = "mas-xm-sdc2";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x01>;
|
|
qcom,connections = <0xcc>;
|
|
qcom,bus-dev = <0xcb>;
|
|
qcom,bcms = <0xce>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x31b>;
|
|
};
|
|
|
|
mas-xm-sdc4 {
|
|
cell-id = <0x50>;
|
|
label = "mas-xm-sdc4";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x02>;
|
|
qcom,connections = <0xcc>;
|
|
qcom,bus-dev = <0xcb>;
|
|
qcom,bcms = <0xce>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x31c>;
|
|
};
|
|
|
|
mas-xm-ufs-mem {
|
|
cell-id = <0x7b>;
|
|
label = "mas-xm-ufs-mem";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x04>;
|
|
qcom,connections = <0xcc>;
|
|
qcom,bus-dev = <0xcb>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x31d>;
|
|
|
|
qcom,node-qos-clks {
|
|
clocks = <0x27 0x09>;
|
|
clock-names = "clk-aggre-ufs-phy-axi-no-rate";
|
|
};
|
|
};
|
|
|
|
mas-qhm-a2noc-cfg {
|
|
cell-id = <0x7c>;
|
|
label = "mas-qhm-a2noc-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0xcf>;
|
|
qcom,bus-dev = <0xd0>;
|
|
phandle = <0x13e>;
|
|
};
|
|
|
|
mas-qhm-qdss-bam {
|
|
cell-id = <0x35>;
|
|
label = "mas-qhm-qdss-bam";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x08>;
|
|
qcom,connections = <0xd1>;
|
|
qcom,bus-dev = <0xd0>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x31e>;
|
|
};
|
|
|
|
mas-qhm-qup-north {
|
|
cell-id = <0x98>;
|
|
label = "mas-qhm-qup-north";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x00>;
|
|
qcom,connections = <0xd1>;
|
|
qcom,bus-dev = <0xd0>;
|
|
qcom,bcms = <0xcd>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x31f>;
|
|
};
|
|
|
|
mas-qnm-cnoc {
|
|
cell-id = <0x76>;
|
|
label = "mas-qnm-cnoc";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x03>;
|
|
qcom,connections = <0xd1>;
|
|
qcom,bus-dev = <0xd0>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
qcom,forwarding;
|
|
phandle = <0x142>;
|
|
};
|
|
|
|
mas-qxm-crypto {
|
|
cell-id = <0x7d>;
|
|
label = "mas-qxm-crypto";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x01>;
|
|
qcom,connections = <0xd1>;
|
|
qcom,bus-dev = <0xd0>;
|
|
qcom,bcms = <0xd2>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
qcom,forwarding;
|
|
phandle = <0x320>;
|
|
};
|
|
|
|
mas-qxm-ipa {
|
|
cell-id = <0x5a>;
|
|
label = "mas-qxm-ipa";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x02>;
|
|
qcom,connections = <0xd1>;
|
|
qcom,bus-dev = <0xd0>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
qcom,forwarding;
|
|
qcom,defer-init-qos;
|
|
qcom,node-qos-bcms = <0x1b7b 0x00 0x01>;
|
|
phandle = <0x321>;
|
|
};
|
|
|
|
mas-xm-pcie3-0 {
|
|
cell-id = <0x2d>;
|
|
label = "mas-xm-pcie3-0";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x0b>;
|
|
qcom,connections = <0xd3>;
|
|
qcom,bus-dev = <0xd0>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x322>;
|
|
};
|
|
|
|
mas-xm-qdss-etr {
|
|
cell-id = <0x3c>;
|
|
label = "mas-xm-qdss-etr";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x09>;
|
|
qcom,connections = <0xd1>;
|
|
qcom,bus-dev = <0xd0>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x323>;
|
|
};
|
|
|
|
mas-xm-usb3-0 {
|
|
cell-id = <0x3d>;
|
|
label = "mas-xm-usb3-0";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x0c>;
|
|
qcom,connections = <0xd1>;
|
|
qcom,bus-dev = <0xd0>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x324>;
|
|
|
|
qcom,node-qos-clks {
|
|
clocks = <0x27 0x0b>;
|
|
clock-names = "clk-aggre-usb3-prim-axi-no-rate";
|
|
};
|
|
};
|
|
|
|
mas-qxm-camnoc-hf0-uncomp {
|
|
cell-id = <0x92>;
|
|
label = "mas-qxm-camnoc-hf0-uncomp";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,connections = <0xd4>;
|
|
qcom,bus-dev = <0xd5>;
|
|
qcom,bcms = <0xd6>;
|
|
phandle = <0x325>;
|
|
};
|
|
|
|
mas-qxm-camnoc-rt-uncomp {
|
|
cell-id = <0xb2>;
|
|
label = "mas-qxm-camnoc-rt-uncomp";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0xd4>;
|
|
qcom,bus-dev = <0xd5>;
|
|
qcom,bcms = <0xd6>;
|
|
phandle = <0x326>;
|
|
};
|
|
|
|
mas-qxm-camnoc-sf-uncomp {
|
|
cell-id = <0x94>;
|
|
label = "mas-qxm-camnoc-sf-uncomp";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0xd4>;
|
|
qcom,bus-dev = <0xd5>;
|
|
qcom,bcms = <0xd6>;
|
|
phandle = <0x327>;
|
|
};
|
|
|
|
mas-qxm-camnoc-nrt-uncomp {
|
|
cell-id = <0xb3>;
|
|
label = "mas-qxm-camnoc-nrt-uncomp";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0xd4>;
|
|
qcom,bus-dev = <0xd5>;
|
|
qcom,bcms = <0xd6>;
|
|
phandle = <0x328>;
|
|
};
|
|
|
|
mas-qnm-npu {
|
|
cell-id = <0x9a>;
|
|
label = "mas-qnm-npu";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x01>;
|
|
qcom,connections = <0xd7>;
|
|
qcom,bus-dev = <0xd8>;
|
|
qcom,bcms = <0xd9>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
phandle = <0x329>;
|
|
};
|
|
|
|
mas-qhm-spdm {
|
|
cell-id = <0x24>;
|
|
label = "mas-qhm-spdm";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0xda>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x32a>;
|
|
};
|
|
|
|
mas-qnm-snoc {
|
|
cell-id = <0x2733>;
|
|
label = "mas-qnm-snoc";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109 0x10a>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x14e>;
|
|
};
|
|
|
|
mas-xm-qdss-dap {
|
|
cell-id = <0x4c>;
|
|
label = "mas-xm-qdss-dap";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xda 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109 0x10a>;
|
|
qcom,bus-dev = <0xdb>;
|
|
phandle = <0x32b>;
|
|
};
|
|
|
|
mas-qhm-cnoc-dc-noc {
|
|
cell-id = <0x7e>;
|
|
label = "mas-qhm-cnoc-dc-noc";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0x10b 0x10c>;
|
|
qcom,bus-dev = <0x10d>;
|
|
phandle = <0x13f>;
|
|
};
|
|
|
|
mas-acm-apps {
|
|
cell-id = <0x01>;
|
|
label = "mas-acm-apps";
|
|
qcom,buswidth = <0x10>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x60 0x62>;
|
|
qcom,connections = <0x10e 0x10f>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,bcms = <0x111>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
phandle = <0x32c>;
|
|
};
|
|
|
|
mas-acm-sys-tcu {
|
|
cell-id = <0x9c>;
|
|
label = "mas-acm-sys-tcu";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x180>;
|
|
qcom,connections = <0x10e 0x10f>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,bcms = <0x112>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x06>;
|
|
phandle = <0x32d>;
|
|
};
|
|
|
|
mas-qhm-gemnoc-cfg {
|
|
cell-id = <0x9d>;
|
|
label = "mas-qhm-gemnoc-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0x113 0x114>;
|
|
qcom,bus-dev = <0x110>;
|
|
phandle = <0x143>;
|
|
};
|
|
|
|
mas-qnm-cmpnoc {
|
|
cell-id = <0x9e>;
|
|
label = "mas-qnm-cmpnoc";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x40>;
|
|
qcom,connections = <0x10e 0x10f>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
phandle = <0x13b>;
|
|
};
|
|
|
|
mas-qnm-mnoc-hf {
|
|
cell-id = <0x84>;
|
|
label = "mas-qnm-mnoc-hf";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,qport = <0x80 0x81>;
|
|
qcom,connections = <0x10e>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x14c>;
|
|
};
|
|
|
|
mas-qnm-mnoc-sf {
|
|
cell-id = <0x85>;
|
|
label = "mas-qnm-mnoc-sf";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x140>;
|
|
qcom,connections = <0x10e 0x10f>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x14b>;
|
|
};
|
|
|
|
mas-qnm-pcie {
|
|
cell-id = <0x9f>;
|
|
label = "mas-qnm-pcie";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0xe0>;
|
|
qcom,connections = <0x10e 0x10f>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
phandle = <0x139>;
|
|
};
|
|
|
|
mas-qnm-snoc-gc {
|
|
cell-id = <0x86>;
|
|
label = "mas-qnm-snoc-gc";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0xc0>;
|
|
qcom,connections = <0x10e>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
phandle = <0x14f>;
|
|
};
|
|
|
|
mas-qnm-snoc-sf {
|
|
cell-id = <0x87>;
|
|
label = "mas-qnm-snoc-sf";
|
|
qcom,buswidth = <0x10>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0xa0>;
|
|
qcom,connections = <0x10e>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
phandle = <0x151>;
|
|
};
|
|
|
|
mas-qxm-gpu {
|
|
cell-id = <0x1a>;
|
|
label = "mas-qxm-gpu";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,qport = <0x120 0x121>;
|
|
qcom,connections = <0x10e 0x10f>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
phandle = <0x32e>;
|
|
};
|
|
|
|
mas-ipa-core-master {
|
|
cell-id = <0x8f>;
|
|
label = "mas-ipa-core-master";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0x115>;
|
|
qcom,bus-dev = <0x116>;
|
|
phandle = <0x32f>;
|
|
};
|
|
|
|
mas-llcc-mc {
|
|
cell-id = <0x81>;
|
|
label = "mas-llcc-mc";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,connections = <0x117>;
|
|
qcom,bus-dev = <0x118>;
|
|
phandle = <0x146>;
|
|
};
|
|
|
|
mas-qhm-mnoc-cfg {
|
|
cell-id = <0x67>;
|
|
label = "mas-qhm-mnoc-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0x119>;
|
|
qcom,bus-dev = <0x11a>;
|
|
phandle = <0x140>;
|
|
};
|
|
|
|
mas-qxm-camnoc-hf {
|
|
cell-id = <0x88>;
|
|
label = "mas-qxm-camnoc-hf";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,qport = <0x20 0x40>;
|
|
qcom,connections = <0x11b>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,bcms = <0xd6>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x330>;
|
|
};
|
|
|
|
mas-qxm-camnoc-nrt {
|
|
cell-id = <0xab>;
|
|
label = "mas-qxm-camnoc-nrt";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x102>;
|
|
qcom,connections = <0x11c>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,bcms = <0x11d>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x331>;
|
|
};
|
|
|
|
mas-qxm-camnoc-rt {
|
|
cell-id = <0xac>;
|
|
label = "mas-qxm-camnoc-rt";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x101>;
|
|
qcom,connections = <0x11b>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,bcms = <0xd6>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x332>;
|
|
};
|
|
|
|
mas-qxm-camnoc-sf {
|
|
cell-id = <0x89>;
|
|
label = "mas-qxm-camnoc-sf";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x00>;
|
|
qcom,connections = <0x11c>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,bcms = <0x11e>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x333>;
|
|
};
|
|
|
|
mas-qxm-mdp0 {
|
|
cell-id = <0x16>;
|
|
label = "mas-qxm-mdp0";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x60>;
|
|
qcom,connections = <0x11b>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,bcms = <0xd6>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x334>;
|
|
};
|
|
|
|
mas-qxm-mdp1 {
|
|
cell-id = <0x17>;
|
|
label = "mas-qxm-mdp1";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x80>;
|
|
qcom,connections = <0x11b>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,bcms = <0xd6>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x335>;
|
|
};
|
|
|
|
mas-qxm-rot {
|
|
cell-id = <0x19>;
|
|
label = "mas-qxm-rot";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0xa0>;
|
|
qcom,connections = <0x11c>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,bcms = <0x11e>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x336>;
|
|
};
|
|
|
|
mas-qxm-venus0 {
|
|
cell-id = <0x3f>;
|
|
label = "mas-qxm-venus0";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0xc0>;
|
|
qcom,connections = <0x11c>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,bcms = <0x11e>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x337>;
|
|
};
|
|
|
|
mas-qxm-venus1 {
|
|
cell-id = <0x40>;
|
|
label = "mas-qxm-venus1";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0xe0>;
|
|
qcom,connections = <0x11c>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,bcms = <0x11e>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x00>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x338>;
|
|
};
|
|
|
|
mas-qxm-venus-arm9 {
|
|
cell-id = <0x8a>;
|
|
label = "mas-qxm-venus-arm9";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x100>;
|
|
qcom,connections = <0x11c>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,bcms = <0x11e>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x05>;
|
|
qcom,forwarding;
|
|
qcom,node-qos-bcms = <0x1b64 0x00 0x01>;
|
|
phandle = <0x339>;
|
|
};
|
|
|
|
mas-qhm-snoc-cfg {
|
|
cell-id = <0x36>;
|
|
label = "mas-qhm-snoc-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0x11f>;
|
|
qcom,bus-dev = <0x120>;
|
|
phandle = <0x141>;
|
|
};
|
|
|
|
mas-qnm-aggre1-noc {
|
|
cell-id = <0x274f>;
|
|
label = "mas-qnm-aggre1-noc";
|
|
qcom,buswidth = <0x10>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0x121 0x122 0x123 0x124 0x125 0x126>;
|
|
qcom,bus-dev = <0x120>;
|
|
qcom,bcms = <0x127>;
|
|
phandle = <0x137>;
|
|
};
|
|
|
|
mas-qnm-aggre2-noc {
|
|
cell-id = <0x2750>;
|
|
label = "mas-qnm-aggre2-noc";
|
|
qcom,buswidth = <0x10>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0x121 0x122 0x123 0x124 0x125 0x128 0x126>;
|
|
qcom,bus-dev = <0x120>;
|
|
qcom,bcms = <0x129>;
|
|
phandle = <0x138>;
|
|
};
|
|
|
|
mas-qnm-gemnoc {
|
|
cell-id = <0xa1>;
|
|
label = "mas-qnm-gemnoc";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,connections = <0x122 0x123 0x124 0x125 0x128 0x126>;
|
|
qcom,bus-dev = <0x120>;
|
|
qcom,bcms = <0x12a>;
|
|
phandle = <0x144>;
|
|
};
|
|
|
|
mas-qxm-pimem {
|
|
cell-id = <0x8d>;
|
|
label = "mas-qxm-pimem";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x03>;
|
|
qcom,connections = <0x12b 0x123>;
|
|
qcom,bus-dev = <0x120>;
|
|
qcom,bcms = <0x12c>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
qcom,forwarding;
|
|
phandle = <0x33a>;
|
|
};
|
|
|
|
mas-xm-gic {
|
|
cell-id = <0x95>;
|
|
label = "mas-xm-gic";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x00>;
|
|
qcom,connections = <0x12b 0x123>;
|
|
qcom,bus-dev = <0x120>;
|
|
qcom,bcms = <0x12c>;
|
|
qcom,ap-owned;
|
|
qcom,prio = <0x02>;
|
|
qcom,forwarding;
|
|
phandle = <0x33b>;
|
|
};
|
|
|
|
mas-alc {
|
|
cell-id = <0x90>;
|
|
label = "mas-alc";
|
|
qcom,buswidth = <0x01>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x118>;
|
|
qcom,bcms = <0x12d>;
|
|
phandle = <0x33c>;
|
|
};
|
|
|
|
mas-qnm-mnoc-hf_display {
|
|
cell-id = <0x4e21>;
|
|
label = "mas-qnm-mnoc-hf_display";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,qport = <0x80 0x81>;
|
|
qcom,connections = <0x12e>;
|
|
qcom,bus-dev = <0x12f>;
|
|
phandle = <0x15b>;
|
|
};
|
|
|
|
mas-qnm-mnoc-sf_display {
|
|
cell-id = <0x4e22>;
|
|
label = "mas-qnm-mnoc-sf_display";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x140>;
|
|
qcom,connections = <0x12e>;
|
|
qcom,bus-dev = <0x12f>;
|
|
phandle = <0x159>;
|
|
};
|
|
|
|
mas-llcc-mc_display {
|
|
cell-id = <0x4e20>;
|
|
label = "mas-llcc-mc_display";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,connections = <0x130>;
|
|
qcom,bus-dev = <0x131>;
|
|
phandle = <0x155>;
|
|
};
|
|
|
|
mas-qxm-mdp0_display {
|
|
cell-id = <0x4e23>;
|
|
label = "mas-qxm-mdp0_display";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x60>;
|
|
qcom,connections = <0x132>;
|
|
qcom,bus-dev = <0x133>;
|
|
qcom,bcms = <0x134>;
|
|
phandle = <0x33d>;
|
|
};
|
|
|
|
mas-qxm-mdp1_display {
|
|
cell-id = <0x4e24>;
|
|
label = "mas-qxm-mdp1_display";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0x80>;
|
|
qcom,connections = <0x132>;
|
|
qcom,bus-dev = <0x133>;
|
|
qcom,bcms = <0x134>;
|
|
phandle = <0x33e>;
|
|
};
|
|
|
|
mas-qxm-rot_display {
|
|
cell-id = <0x4e25>;
|
|
label = "mas-qxm-rot_display";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,qport = <0xa0>;
|
|
qcom,connections = <0x135>;
|
|
qcom,bus-dev = <0x133>;
|
|
qcom,bcms = <0x136>;
|
|
phandle = <0x33f>;
|
|
};
|
|
|
|
slv-qns-a1noc-snoc {
|
|
cell-id = <0x274e>;
|
|
label = "slv-qns-a1noc-snoc";
|
|
qcom,buswidth = <0x10>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xcb>;
|
|
qcom,connections = <0x137>;
|
|
qcom,bcms = <0x127>;
|
|
phandle = <0xcc>;
|
|
};
|
|
|
|
slv-srvc-aggre1-noc {
|
|
cell-id = <0x2e8>;
|
|
label = "slv-srvc-aggre1-noc";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xcb>;
|
|
phandle = <0xca>;
|
|
};
|
|
|
|
slv-qns-a2noc-snoc {
|
|
cell-id = <0x2751>;
|
|
label = "slv-qns-a2noc-snoc";
|
|
qcom,buswidth = <0x10>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xd0>;
|
|
qcom,connections = <0x138>;
|
|
qcom,bcms = <0x129>;
|
|
phandle = <0xd1>;
|
|
};
|
|
|
|
slv-qns-pcie-gemnoc {
|
|
cell-id = <0x2755>;
|
|
label = "slv-qns-pcie-gemnoc";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xd0>;
|
|
qcom,connections = <0x139>;
|
|
qcom,bcms = <0x13a>;
|
|
phandle = <0xd3>;
|
|
};
|
|
|
|
slv-srvc-aggre2-noc {
|
|
cell-id = <0x2ea>;
|
|
label = "slv-srvc-aggre2-noc";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xd0>;
|
|
phandle = <0xcf>;
|
|
};
|
|
|
|
slv-qns-camnoc-uncomp {
|
|
cell-id = <0x30a>;
|
|
label = "slv-qns-camnoc-uncomp";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xd5>;
|
|
phandle = <0xd4>;
|
|
};
|
|
|
|
slv-qns-cdsp-gemnoc {
|
|
cell-id = <0x275c>;
|
|
label = "slv-qns-cdsp-gemnoc";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xd8>;
|
|
qcom,connections = <0x13b>;
|
|
qcom,bcms = <0x13c>;
|
|
phandle = <0xd7>;
|
|
};
|
|
|
|
slv-qhs-a1-noc-cfg {
|
|
cell-id = <0x2af>;
|
|
label = "slv-qhs-a1-noc-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,connections = <0x13d>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x100>;
|
|
};
|
|
|
|
slv-qhs-a2-noc-cfg {
|
|
cell-id = <0x2b0>;
|
|
label = "slv-qhs-a2-noc-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,connections = <0x13e>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xe6>;
|
|
};
|
|
|
|
slv-qhs-ahb2phy-north {
|
|
cell-id = <0x327>;
|
|
label = "slv-qhs-ahb2phy-north";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xef>;
|
|
};
|
|
|
|
slv-qhs-ahb2phy-south {
|
|
cell-id = <0x30b>;
|
|
label = "slv-qhs-ahb2phy-south";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xf8>;
|
|
};
|
|
|
|
slv-qhs-ahb2phy-west {
|
|
cell-id = <0x319>;
|
|
label = "slv-qhs-ahb2phy-west";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xfa>;
|
|
};
|
|
|
|
slv-qhs-aop {
|
|
cell-id = <0x2eb>;
|
|
label = "slv-qhs-aop";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xf6>;
|
|
};
|
|
|
|
slv-qhs-aoss {
|
|
cell-id = <0x2ec>;
|
|
label = "slv-qhs-aoss";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x101>;
|
|
};
|
|
|
|
slv-qhs-camera-cfg {
|
|
cell-id = <0x24d>;
|
|
label = "slv-qhs-camera-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
qcom,disable-ports = <0x46 0x47>;
|
|
phandle = <0xdd>;
|
|
};
|
|
|
|
slv-qhs-camera-nrt-thrott-cfg {
|
|
cell-id = <0x328>;
|
|
label = "slv-qhs-camera-nrt-throttle-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xe5>;
|
|
};
|
|
|
|
slv-qhs-camera-rt-throttle-cfg {
|
|
cell-id = <0x329>;
|
|
label = "slv-qhs-camera-rt-throttle-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xe8>;
|
|
};
|
|
|
|
slv-qhs-clk-ctl {
|
|
cell-id = <0x26c>;
|
|
label = "slv-qhs-clk-ctl";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xf5>;
|
|
};
|
|
|
|
slv-qhs-compute-dsp-cfg {
|
|
cell-id = <0x2ed>;
|
|
label = "slv-qhs-compute-dsp-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xf4>;
|
|
};
|
|
|
|
slv-qhs-cpr-cx {
|
|
cell-id = <0x28b>;
|
|
label = "slv-qhs-cpr-cx";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xfe>;
|
|
};
|
|
|
|
slv-qhs-cpr-mx {
|
|
cell-id = <0x28c>;
|
|
label = "slv-qhs-cpr-mx";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x109>;
|
|
};
|
|
|
|
slv-qhs-crypto0-cfg {
|
|
cell-id = <0x271>;
|
|
label = "slv-qhs-crypto0-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x106>;
|
|
};
|
|
|
|
slv-qhs-ddrss-cfg {
|
|
cell-id = <0x2ee>;
|
|
label = "slv-qhs-ddrss-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,connections = <0x13f>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xee>;
|
|
};
|
|
|
|
slv-qhs-display-cfg {
|
|
cell-id = <0x24e>;
|
|
label = "slv-qhs-display-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
qcom,disable-ports = <0x48 0x49>;
|
|
phandle = <0xe9>;
|
|
};
|
|
|
|
slv-qhs-display-throttle-cfg {
|
|
cell-id = <0x2bc>;
|
|
label = "slv-qhs-display-throttle-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xeb>;
|
|
};
|
|
|
|
slv-qhs-emmc-cfg {
|
|
cell-id = <0x326>;
|
|
label = "slv-qhs-emmc-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x104>;
|
|
};
|
|
|
|
slv-qhs-glm {
|
|
cell-id = <0x2d6>;
|
|
label = "slv-qhs-glm";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xe3>;
|
|
};
|
|
|
|
slv-qhs-gpuss-cfg {
|
|
cell-id = <0x256>;
|
|
label = "slv-qhs-gpuss-cfg";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xf1>;
|
|
};
|
|
|
|
slv-qhs-imem-cfg {
|
|
cell-id = <0x273>;
|
|
label = "slv-qhs-imem-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x10a>;
|
|
};
|
|
|
|
slv-qhs-ipa {
|
|
cell-id = <0x2a4>;
|
|
label = "slv-qhs-ipa";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xfd>;
|
|
};
|
|
|
|
slv-qhs-mnoc-cfg {
|
|
cell-id = <0x280>;
|
|
label = "slv-qhs-mnoc-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,connections = <0x140>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xe0>;
|
|
};
|
|
|
|
slv-qhs-pcie-cfg {
|
|
cell-id = <0x28d>;
|
|
label = "slv-qhs-pcie-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xea>;
|
|
};
|
|
|
|
slv-qhs-pdm {
|
|
cell-id = <0x267>;
|
|
label = "slv-qhs-pdm";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xe4>;
|
|
};
|
|
|
|
slv-qhs-pimem-cfg {
|
|
cell-id = <0x2a9>;
|
|
label = "slv-qhs-pimem-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x107>;
|
|
};
|
|
|
|
slv-qhs-prng {
|
|
cell-id = <0x26a>;
|
|
label = "slv-qhs-prng";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x102>;
|
|
};
|
|
|
|
slv-qhs-qdss-cfg {
|
|
cell-id = <0x27b>;
|
|
label = "slv-qhs-qdss-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xe7>;
|
|
};
|
|
|
|
slv-qhs-qupv3-center {
|
|
cell-id = <0x313>;
|
|
label = "slv-qhs-qupv3-center";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xe2>;
|
|
};
|
|
|
|
slv-qhs-qupv3-north {
|
|
cell-id = <0x312>;
|
|
label = "slv-qhs-qupv3-north";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xf7>;
|
|
};
|
|
|
|
slv-qhs-sdc2 {
|
|
cell-id = <0x260>;
|
|
label = "slv-qhs-sdc2";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xdf>;
|
|
};
|
|
|
|
slv-qhs-sdc4 {
|
|
cell-id = <0x261>;
|
|
label = "slv-qhs-sdc4";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xde>;
|
|
};
|
|
|
|
slv-qhs-snoc-cfg {
|
|
cell-id = <0x282>;
|
|
label = "slv-qhs-snoc-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,connections = <0x141>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xf0>;
|
|
};
|
|
|
|
slv-qhs-spdm {
|
|
cell-id = <0x279>;
|
|
label = "slv-qhs-spdm";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x105>;
|
|
};
|
|
|
|
slv-qhs-tcsr {
|
|
cell-id = <0x26f>;
|
|
label = "slv-qhs-tcsr";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xec>;
|
|
};
|
|
|
|
slv-qhs-tlmm-north {
|
|
cell-id = <0x2db>;
|
|
label = "slv-qhs-tlmm-north";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x108>;
|
|
};
|
|
|
|
slv-qhs-tlmm-south {
|
|
cell-id = <0x2f3>;
|
|
label = "slv-qhs-tlmm-south";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xdc>;
|
|
};
|
|
|
|
slv-qhs-tlmm-west {
|
|
cell-id = <0x2dc>;
|
|
label = "slv-qhs-tlmm-west";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xff>;
|
|
};
|
|
|
|
slv-qhs-tsif {
|
|
cell-id = <0x23f>;
|
|
label = "slv-qhs-tsif";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xf3>;
|
|
};
|
|
|
|
slv-qhs-ufs-mem-cfg {
|
|
cell-id = <0x2f5>;
|
|
label = "slv-qhs-ufs-mem-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xe1>;
|
|
};
|
|
|
|
slv-qhs-usb3-0 {
|
|
cell-id = <0x247>;
|
|
label = "slv-qhs-usb3-0";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xfb>;
|
|
};
|
|
|
|
slv-qhs-venus-cfg {
|
|
cell-id = <0x254>;
|
|
label = "slv-qhs-venus-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
qcom,disable-ports = <0x4b 0x4c>;
|
|
phandle = <0xf2>;
|
|
};
|
|
|
|
slv-qhs-venus-cvp-throttle-cfg {
|
|
cell-id = <0x32a>;
|
|
label = "slv-qhs-venus-cvp-throttle-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xed>;
|
|
};
|
|
|
|
slv-qhs-venus-throttle-cfg {
|
|
cell-id = <0x2b8>;
|
|
label = "slv-qhs-venus-throttle-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xfc>;
|
|
};
|
|
|
|
slv-qhs-vsense-ctrl-cfg {
|
|
cell-id = <0x2f6>;
|
|
label = "slv-qhs-vsense-ctrl-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0x103>;
|
|
};
|
|
|
|
slv-qns-cnoc-a2noc {
|
|
cell-id = <0x2d5>;
|
|
label = "slv-qns-cnoc-a2noc";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,connections = <0x142>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xda>;
|
|
};
|
|
|
|
slv-srvc-cnoc {
|
|
cell-id = <0x286>;
|
|
label = "slv-srvc-cnoc";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0xdb>;
|
|
qcom,bcms = <0xce>;
|
|
phandle = <0xf9>;
|
|
};
|
|
|
|
slv-qhs-gemnoc {
|
|
cell-id = <0x314>;
|
|
label = "slv-qhs-gemnoc";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x10d>;
|
|
qcom,connections = <0x143>;
|
|
phandle = <0x10c>;
|
|
};
|
|
|
|
slv-qhs-llcc {
|
|
cell-id = <0x2f8>;
|
|
label = "slv-qhs-llcc";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x10d>;
|
|
phandle = <0x10b>;
|
|
};
|
|
|
|
slv-qhs-mdsp-ms-mpu-cfg {
|
|
cell-id = <0x2fd>;
|
|
label = "slv-qhs-mdsp-ms-mpu-cfg";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x110>;
|
|
phandle = <0x114>;
|
|
};
|
|
|
|
slv-qns-gem-noc-snoc {
|
|
cell-id = <0x2757>;
|
|
label = "slv-qns-gem-noc-snoc";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,connections = <0x144>;
|
|
qcom,bcms = <0x145>;
|
|
phandle = <0x10f>;
|
|
};
|
|
|
|
slv-qns-llcc {
|
|
cell-id = <0x302>;
|
|
label = "slv-qns-llcc";
|
|
qcom,buswidth = <0x10>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,bus-dev = <0x110>;
|
|
qcom,connections = <0x146>;
|
|
qcom,bcms = <0x147>;
|
|
phandle = <0x10e>;
|
|
};
|
|
|
|
slv-srvc-gemnoc {
|
|
cell-id = <0x316>;
|
|
label = "slv-srvc-gemnoc";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x110>;
|
|
phandle = <0x113>;
|
|
};
|
|
|
|
slv-ipa-core-slave {
|
|
cell-id = <0x309>;
|
|
label = "slv-ipa-core-slave";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x116>;
|
|
qcom,bcms = <0x148>;
|
|
phandle = <0x115>;
|
|
};
|
|
|
|
slv-ebi {
|
|
cell-id = <0x200>;
|
|
label = "slv-ebi";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,bus-dev = <0x118>;
|
|
qcom,bcms = <0x149 0x14a>;
|
|
phandle = <0x117>;
|
|
};
|
|
|
|
slv-qns2-mem-noc {
|
|
cell-id = <0x304>;
|
|
label = "slv-qns2-mem-noc";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,connections = <0x14b>;
|
|
qcom,bcms = <0x11d>;
|
|
phandle = <0x11c>;
|
|
};
|
|
|
|
slv-qns-mem-noc-hf {
|
|
cell-id = <0x305>;
|
|
label = "slv-qns-mem-noc-hf";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,bus-dev = <0x11a>;
|
|
qcom,connections = <0x14c>;
|
|
qcom,bcms = <0x14d>;
|
|
phandle = <0x11b>;
|
|
};
|
|
|
|
slv-srvc-mnoc {
|
|
cell-id = <0x25b>;
|
|
label = "slv-srvc-mnoc";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x11a>;
|
|
phandle = <0x119>;
|
|
};
|
|
|
|
slv-qhs-apss {
|
|
cell-id = <0x2a1>;
|
|
label = "slv-qhs-apss";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x120>;
|
|
phandle = <0x124>;
|
|
};
|
|
|
|
slv-qns-cnoc {
|
|
cell-id = <0x2734>;
|
|
label = "slv-qns-cnoc";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x120>;
|
|
qcom,connections = <0x14e>;
|
|
phandle = <0x125>;
|
|
};
|
|
|
|
slv-qns-gemnoc-gc {
|
|
cell-id = <0x2758>;
|
|
label = "slv-qns-gemnoc-gc";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x120>;
|
|
qcom,connections = <0x14f>;
|
|
qcom,bcms = <0x150>;
|
|
phandle = <0x12b>;
|
|
};
|
|
|
|
slv-qns-gemnoc-sf {
|
|
cell-id = <0x2759>;
|
|
label = "slv-qns-gemnoc-sf";
|
|
qcom,buswidth = <0x10>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x120>;
|
|
qcom,connections = <0x151>;
|
|
qcom,bcms = <0x152>;
|
|
phandle = <0x121>;
|
|
};
|
|
|
|
slv-qxs-imem {
|
|
cell-id = <0x249>;
|
|
label = "slv-qxs-imem";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x120>;
|
|
qcom,bcms = <0x153>;
|
|
phandle = <0x123>;
|
|
};
|
|
|
|
slv-qxs-pimem {
|
|
cell-id = <0x2c8>;
|
|
label = "slv-qxs-pimem";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x120>;
|
|
qcom,bcms = <0x154>;
|
|
phandle = <0x122>;
|
|
};
|
|
|
|
slv-srvc-snoc {
|
|
cell-id = <0x24b>;
|
|
label = "slv-srvc-snoc";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x120>;
|
|
phandle = <0x11f>;
|
|
};
|
|
|
|
slv-xs-qdss-stm {
|
|
cell-id = <0x24c>;
|
|
label = "slv-xs-qdss-stm";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x120>;
|
|
phandle = <0x126>;
|
|
};
|
|
|
|
slv-xs-sys-tcu-cfg {
|
|
cell-id = <0x2a0>;
|
|
label = "slv-xs-sys-tcu-cfg";
|
|
qcom,buswidth = <0x08>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x120>;
|
|
phandle = <0x128>;
|
|
};
|
|
|
|
slv-qns-llcc_display {
|
|
cell-id = <0x5021>;
|
|
label = "slv-qns-llcc_display";
|
|
qcom,buswidth = <0x10>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,bus-dev = <0x12f>;
|
|
qcom,connections = <0x155>;
|
|
qcom,bcms = <0x156>;
|
|
phandle = <0x12e>;
|
|
};
|
|
|
|
slv-ebi_display {
|
|
cell-id = <0x5020>;
|
|
label = "slv-ebi_display";
|
|
qcom,buswidth = <0x04>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,bus-dev = <0x131>;
|
|
qcom,bcms = <0x157 0x158>;
|
|
phandle = <0x130>;
|
|
};
|
|
|
|
slv-qns2-mem-noc_display {
|
|
cell-id = <0x5022>;
|
|
label = "slv-qns2-mem-noc_display";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x01>;
|
|
qcom,bus-dev = <0x133>;
|
|
qcom,connections = <0x159>;
|
|
qcom,bcms = <0x15a>;
|
|
phandle = <0x135>;
|
|
};
|
|
|
|
slv-qns-mem-noc-hf_display {
|
|
cell-id = <0x5023>;
|
|
label = "slv-qns-mem-noc-hf_display";
|
|
qcom,buswidth = <0x20>;
|
|
qcom,agg-ports = <0x02>;
|
|
qcom,bus-dev = <0x133>;
|
|
qcom,connections = <0x15b>;
|
|
qcom,bcms = <0x15c>;
|
|
phandle = <0x132>;
|
|
};
|
|
};
|
|
|
|
qcom,qupv3_0_geni_se@0x8c0000 {
|
|
compatible = "qcom,qupv3-geni-se";
|
|
reg = <0x8c0000 0x2000>;
|
|
qcom,bus-mas-id = <0x97>;
|
|
qcom,bus-slv-id = <0x200>;
|
|
qcom,iommu-s1-bypass;
|
|
phandle = <0x160>;
|
|
|
|
qcom,iommu_qupv3_0_geni_se_cb {
|
|
compatible = "qcom,qupv3-geni-se-cb";
|
|
iommus = <0x30 0x203 0x00>;
|
|
phandle = <0x340>;
|
|
};
|
|
};
|
|
|
|
i2c@0x880000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x880000 0x4000>;
|
|
interrupts = <0x00 0x259 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x44 0x27 0x67 0x27 0x68>;
|
|
dmas = <0x15d 0x00 0x00 0x03 0x40 0x00 0x15d 0x01 0x00 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x534>;
|
|
pinctrl-1 = <0x535>;
|
|
qcom,wrapper-core = <0x160>;
|
|
status = "ok";
|
|
phandle = <0x341>;
|
|
qcom,clk-freq-out = <0x186a0>;
|
|
|
|
tas2562@4c {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "ti,tas2562";
|
|
reg = <0x4c>;
|
|
ti,left-channel = <0x4c>;
|
|
ti,channels = <0x01>;
|
|
ti,asi-format = <0x00>;
|
|
ti,reset-gpio = <0x16c 0x08 0x00>;
|
|
ti,irq-gpio = <0x16c 0x59 0x00>;
|
|
ti,port_id = <0x1002>;
|
|
ti,iv-width = <0x0c>;
|
|
ti,vbat-mon = <0x01>;
|
|
status = "ok";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x536 0x537>;
|
|
phandle = <0x5b5>;
|
|
};
|
|
};
|
|
|
|
i2c@0x884000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x884000 0x4000>;
|
|
interrupts = <0x00 0x25a 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x46 0x27 0x67 0x27 0x68>;
|
|
dmas = <0x15d 0x00 0x01 0x03 0x40 0x00 0x15d 0x01 0x01 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x161>;
|
|
pinctrl-1 = <0x162>;
|
|
qcom,wrapper-core = <0x160>;
|
|
status = "disabled";
|
|
phandle = <0x342>;
|
|
};
|
|
|
|
i2c@0x888000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x888000 0x4000>;
|
|
interrupts = <0x00 0x25b 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x48 0x27 0x67 0x27 0x68>;
|
|
dmas = <0x15d 0x00 0x02 0x03 0x40 0x00 0x15d 0x01 0x02 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x163>;
|
|
pinctrl-1 = <0x55a>;
|
|
qcom,wrapper-core = <0x160>;
|
|
status = "okay";
|
|
phandle = <0x343>;
|
|
qcom,clk-freq-out = <0xf4240>;
|
|
|
|
nq@28 {
|
|
compatible = "qcom,nq-nci";
|
|
reg = <0x28>;
|
|
qcom,nq-irq = <0x16c 0x25 0x00>;
|
|
qcom,nq-ven = <0x16c 0x0c 0x00>;
|
|
qcom,nq-firm = <0x16c 0x24 0x00>;
|
|
qcom,nq-clkreq = <0x16c 0x1f 0x00>;
|
|
qcom,nq-esepwr = <0x16c 0x5e 0x00>;
|
|
interrupt-parent = <0x16c>;
|
|
interrupts = <0x25 0x00>;
|
|
interrupt-names = "nfc_irq";
|
|
pinctrl-names = "nfc_active\0nfc_suspend";
|
|
pinctrl-0 = <0x39b 0x39d 0x39f>;
|
|
pinctrl-1 = <0x39c 0x39e 0x3a0>;
|
|
};
|
|
|
|
pn547@2B {
|
|
compatible = "pn547";
|
|
reg = <0x2b>;
|
|
interrupt-parent = <0x16c>;
|
|
interrupts = <0x25 0x00>;
|
|
pn547,irq-gpio = <0x16c 0x25 0x00>;
|
|
pn547,ven-gpio = <0x16c 0x0c 0x00>;
|
|
pn547,firm-gpio = <0x16c 0x24 0x00>;
|
|
pn547,clk_req-gpio = <0x16c 0x1f 0x00>;
|
|
pn547,pwr_req = <0x16c 0x5e 0x00>;
|
|
pn547,pvdd-gpio = <0x16c 0x41 0x00>;
|
|
pn547,clk_req_wake;
|
|
};
|
|
};
|
|
|
|
i2c@0x88c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x88c000 0x4000>;
|
|
interrupts = <0x00 0x25c 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x4a 0x27 0x67 0x27 0x68>;
|
|
dmas = <0x15d 0x00 0x03 0x03 0x40 0x00 0x15d 0x01 0x03 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x165>;
|
|
pinctrl-1 = <0x166>;
|
|
qcom,wrapper-core = <0x160>;
|
|
status = "disabled";
|
|
phandle = <0x344>;
|
|
};
|
|
|
|
i2c@0x890000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x890000 0x4000>;
|
|
interrupts = <0x00 0x25d 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x4c 0x27 0x67 0x27 0x68>;
|
|
dmas = <0x15d 0x00 0x04 0x03 0x40 0x00 0x15d 0x01 0x04 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x167>;
|
|
pinctrl-1 = <0x168>;
|
|
qcom,wrapper-core = <0x160>;
|
|
status = "disabled";
|
|
phandle = <0x345>;
|
|
};
|
|
|
|
qcom,qup_uart@0x88c000 {
|
|
compatible = "qcom,msm-geni-serial-hs";
|
|
reg = <0x88c000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x4a 0x27 0x67 0x27 0x68>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x169 0x16a 0x16b>;
|
|
pinctrl-1 = <0x169 0x16a 0x16b>;
|
|
interrupts-extended = <0x01 0x00 0x25c 0x00 0x16c 0x29 0x00>;
|
|
status = "ok";
|
|
qcom,wakeup-byte = <0xfd>;
|
|
qcom,wrapper-core = <0x160>;
|
|
phandle = <0x346>;
|
|
};
|
|
|
|
qcom,qup_uart@0x890000 {
|
|
compatible = "qcom,msm-geni-serial-hs";
|
|
reg = <0x890000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x4c 0x27 0x67 0x27 0x68>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x16d 0x16e 0x16f>;
|
|
pinctrl-1 = <0x16d 0x16e 0x16f>;
|
|
interrupts-extended = <0x01 0x00 0x25d 0x00 0x16c 0x38 0x00>;
|
|
status = "disabled";
|
|
qcom,wakeup-byte = <0xfd>;
|
|
qcom,wrapper-core = <0x160>;
|
|
phandle = <0x347>;
|
|
};
|
|
|
|
spi@0x880000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x880000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x44 0x27 0x67 0x27 0x68>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x170>;
|
|
pinctrl-1 = <0x171>;
|
|
interrupts = <0x00 0x259 0x00>;
|
|
spi-max-frequency = <0x2faf080>;
|
|
qcom,wrapper-core = <0x160>;
|
|
dmas = <0x15d 0x00 0x00 0x01 0x40 0x00 0x15d 0x01 0x00 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x348>;
|
|
};
|
|
|
|
spi@0x884000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x884000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x46 0x27 0x67 0x27 0x68>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x172>;
|
|
pinctrl-1 = <0x55b>;
|
|
interrupts = <0x00 0x25a 0x00>;
|
|
spi-max-frequency = <0x124f800>;
|
|
qcom,wrapper-core = <0x160>;
|
|
dmas = <0x15d 0x00 0x01 0x01 0x40 0x00 0x15d 0x01 0x01 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "okay";
|
|
phandle = <0x349>;
|
|
|
|
ese_spi@0 {
|
|
compatible = "p61";
|
|
reg = <0x00>;
|
|
spi-max-frequency = <0xf42400>;
|
|
p61-ap_vendor = "qualcomm";
|
|
p61-spi_node = <0x349>;
|
|
ese-det-gpio = <0x2e4 0x01 0x00>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x55c>;
|
|
};
|
|
};
|
|
|
|
spi@0x88c000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x88c000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x4a 0x27 0x67 0x27 0x68>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x174>;
|
|
pinctrl-1 = <0x175>;
|
|
interrupts = <0x00 0x25c 0x00>;
|
|
spi-max-frequency = <0x2faf080>;
|
|
qcom,wrapper-core = <0x160>;
|
|
dmas = <0x15d 0x00 0x03 0x01 0x40 0x00 0x15d 0x01 0x03 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x34a>;
|
|
};
|
|
|
|
spi@0x890000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x890000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x4c 0x27 0x67 0x27 0x68>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x176>;
|
|
pinctrl-1 = <0x177>;
|
|
interrupts = <0x00 0x25d 0x00>;
|
|
spi-max-frequency = <0x2faf080>;
|
|
qcom,wrapper-core = <0x160>;
|
|
dmas = <0x15d 0x00 0x04 0x01 0x40 0x00 0x15d 0x01 0x04 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x34b>;
|
|
};
|
|
|
|
qcom,qupv3_1_geni_se@0xac0000 {
|
|
compatible = "qcom,qupv3-geni-se";
|
|
reg = <0xac0000 0x2000>;
|
|
qcom,bus-mas-id = <0x98>;
|
|
qcom,bus-slv-id = <0x200>;
|
|
qcom,iommu-s1-bypass;
|
|
phandle = <0x17a>;
|
|
|
|
qcom,iommu_qupv3_1_geni_se_cb {
|
|
compatible = "qcom,qupv3-geni-se-cb";
|
|
iommus = <0x30 0x4c3 0x00>;
|
|
phandle = <0x34c>;
|
|
};
|
|
};
|
|
|
|
qcom,qup_uart@0xa88000 {
|
|
compatible = "qcom,msm-geni-console";
|
|
reg = <0xa88000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x5b 0x27 0x69 0x27 0x6a>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x178>;
|
|
pinctrl-1 = <0x179>;
|
|
interrupts = <0x00 0x163 0x00>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
status = "ok";
|
|
phandle = <0x34d>;
|
|
};
|
|
|
|
i2c@0xa80000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa80000 0x4000>;
|
|
interrupts = <0x00 0x161 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x57 0x27 0x69 0x27 0x6a>;
|
|
dmas = <0x17b 0x00 0x00 0x03 0x40 0x00 0x17b 0x01 0x00 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x17c>;
|
|
pinctrl-1 = <0x17d>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
status = "disabled";
|
|
phandle = <0x34e>;
|
|
};
|
|
|
|
i2c@0xa84000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa84000 0x4000>;
|
|
interrupts = <0x00 0x162 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x59 0x27 0x69 0x27 0x6a>;
|
|
dmas = <0x17b 0x00 0x01 0x03 0x40 0x00 0x17b 0x01 0x01 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x17e>;
|
|
pinctrl-1 = <0x17f>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
status = "ok";
|
|
phandle = <0x34f>;
|
|
qcom,i2c-touch-active = "st,fts";
|
|
|
|
st_fts@49 {
|
|
compatible = "st,fts";
|
|
reg = <0x49>;
|
|
interrupt-parent = <0x16c>;
|
|
interrupts = <0x09 0x2008>;
|
|
vdd-supply = <0x31>;
|
|
avdd-supply = <0x3f8>;
|
|
pinctrl-names = "pmx_ts_active\0pmx_ts_suspend\0pmx_ts_release";
|
|
pinctrl-0 = <0x3e1>;
|
|
pinctrl-1 = <0x3e2 0x3e3>;
|
|
pinctrl-2 = <0x3e4>;
|
|
st,irq-gpio = <0x16c 0x09 0x2008>;
|
|
st,reset-gpio = <0x16c 0x08 0x00>;
|
|
st,regulator_dvdd = "vdd";
|
|
st,regulator_avdd = "avdd";
|
|
st,x-flip;
|
|
st,y-flip;
|
|
};
|
|
|
|
synaptics_dsx@20 {
|
|
compatible = "synaptics,dsx-i2c";
|
|
reg = <0x20>;
|
|
interrupt-parent = <0x16c>;
|
|
interrupts = <0x09 0x2008>;
|
|
vdd-supply = <0x31>;
|
|
avdd-supply = <0x3f8>;
|
|
pinctrl-names = "pmx_ts_active\0pmx_ts_suspend\0pmx_ts_release";
|
|
pinctrl-0 = <0x3e1>;
|
|
pinctrl-1 = <0x3e2 0x3e3>;
|
|
pinctrl-2 = <0x3e4>;
|
|
synaptics,pwr-reg-name = "avdd";
|
|
synaptics,bus-reg-name = "vdd";
|
|
synaptics,ub-i2c-addr = <0x20>;
|
|
synaptics,max-y-for-2d = <0x86f>;
|
|
synaptics,irq-gpio = <0x16c 0x09 0x2008>;
|
|
synaptics,reset-gpio = <0x16c 0x08 0x00>;
|
|
synaptics,irq-on-state = <0x00>;
|
|
synaptics,power-delay-ms = <0xc8>;
|
|
synaptics,reset-delay-ms = <0xc8>;
|
|
synaptics,reset-on-state = <0x00>;
|
|
synaptics,reset-active-ms = <0x14>;
|
|
};
|
|
|
|
touchscreen@50 {
|
|
compatible = "imagis,ist40xx-ts";
|
|
reg = <0x50>;
|
|
imagis,irq-gpio = <0x16c 0x09 0x00>;
|
|
imagis,regulator_avdd = "tsp_ldo_en";
|
|
imagis,fw-bin = <0x01>;
|
|
imagis,octa-hw = <0x01>;
|
|
imagis,area-size = <0x3f 0x7e 0x3c>;
|
|
imagis,ic-version = "ist40xx";
|
|
imagis,project-name = "a70s";
|
|
imagis,tclm_level = <0x01>;
|
|
imagis,afe_base = <0x00>;
|
|
imagis,factory_item_version = <0x01>;
|
|
imagis,cm_spec = <0x12c 0x898 0x2b>;
|
|
enable_fpcb_noise_test;
|
|
enable_settings_aot;
|
|
support_fod;
|
|
status = "disabled";
|
|
};
|
|
|
|
mms_ts@48 {
|
|
compatible = "melfas,mms_ts";
|
|
reg = <0x48>;
|
|
pinctrl-names = "on_state\0off_state";
|
|
pinctrl-0 = <0x540>;
|
|
pinctrl-1 = <0x541>;
|
|
melfas,irq-gpio = <0x16c 0x09 0x00>;
|
|
melfas,scl-gpio = <0x16c 0x07 0x00>;
|
|
melfas,sda-gpio = <0x16c 0x06 0x00>;
|
|
melfas,vdd_en = "tsp_ldo_en";
|
|
melfas,area-size = <0x85 0x10a 0x155>;
|
|
melfas,max_x_y = <0xfff 0xfff>;
|
|
melfas,display_resolution = <0x438 0x960>;
|
|
melfas,node_info = <0x10 0x22 0x00>;
|
|
melfas,fod_info = <0x10 0x0e 0x1c>;
|
|
melfas,event_info = <0x08 0x0c>;
|
|
melfas,support_lpm = "true";
|
|
melfas,fw_name = "tsp_melfas/mss100_a70s.bin";
|
|
melfas,ss_touch_num = <0x01>;
|
|
support_ear_detect_mode;
|
|
enable_settings_aot;
|
|
support_fod;
|
|
support_open_short_test;
|
|
melfas,regulator_boot_on;
|
|
status = "disabled";
|
|
};
|
|
|
|
touchscreen@48 {
|
|
status = "ok";
|
|
compatible = "sec,sec_ts";
|
|
reg = <0x48>;
|
|
interrupt-parent = <0x16c>;
|
|
interrupts = <0x09 0x00>;
|
|
pinctrl-names = "default\0on_state\0off_state";
|
|
pinctrl-0 = <0x540 0x542>;
|
|
pinctrl-1 = <0x540 0x542>;
|
|
pinctrl-2 = <0x540>;
|
|
sec,irq_gpio = <0x16c 0x09 0x2008>;
|
|
sec,dvdd_gpio = <0x2df 0x04 0x00>;
|
|
sec,irq_type = <0x2008>;
|
|
sec,max_coords = <0x1000 0x1000>;
|
|
sec,regulator_avdd = "tsp_ldo_avdd";
|
|
sec,regulator_boot_on;
|
|
sec,firmware_name = "tsp_sec/y771_a71_1l.bin\0tsp_sec/y771_a71.bin";
|
|
sec,project_name = "A71\0A715";
|
|
sec,tclm_level = <0x02>;
|
|
sec,afe_base = <0x107>;
|
|
support_dex_mode;
|
|
sec,i2c-burstmax = <0xffff>;
|
|
sec,ss_touch_num = <0x01>;
|
|
enable_settings_aot;
|
|
sec,area-size = <0x84 0x10a 0x155>;
|
|
support_ear_detect_mode;
|
|
sync-reportrate-120 = "Y";
|
|
support_fod;
|
|
support_fod_gesture;
|
|
support_open_short_test;
|
|
support_mis_calibration_test;
|
|
sec,bringup = <0x03>;
|
|
};
|
|
};
|
|
|
|
i2c@0xa88000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa88000 0x4000>;
|
|
interrupts = <0x00 0x163 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x5b 0x27 0x69 0x27 0x6a>;
|
|
dmas = <0x17b 0x00 0x02 0x03 0x40 0x00 0x17b 0x01 0x02 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x180>;
|
|
pinctrl-1 = <0x181>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
status = "disabled";
|
|
phandle = <0x350>;
|
|
};
|
|
|
|
i2c@0xa8c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
interrupts = <0x00 0x164 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x5d 0x27 0x69 0x27 0x6a>;
|
|
dmas = <0x17b 0x00 0x03 0x03 0x40 0x00 0x17b 0x01 0x03 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x182>;
|
|
pinctrl-1 = <0x183>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
status = "ok";
|
|
phandle = <0x351>;
|
|
|
|
fsa4480@43 {
|
|
compatible = "qcom,fsa4480-i2c";
|
|
reg = <0x43>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x184>;
|
|
phandle = <0x29b>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
i2c@0xa90000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa90000 0x4000>;
|
|
interrupts = <0x00 0x165 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x5f 0x27 0x69 0x27 0x6a>;
|
|
dmas = <0x17b 0x00 0x04 0x03 0x40 0x00 0x17b 0x01 0x04 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x185>;
|
|
pinctrl-1 = <0x186>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
status = "disabled";
|
|
phandle = <0x352>;
|
|
};
|
|
|
|
i2c@0xa94000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa94000 0x4000>;
|
|
interrupts = <0x00 0x166 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x61 0x27 0x69 0x27 0x6a>;
|
|
dmas = <0x17b 0x00 0x05 0x03 0x40 0x00 0x17b 0x01 0x05 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x187>;
|
|
pinctrl-1 = <0x188>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
status = "disabled";
|
|
phandle = <0x353>;
|
|
};
|
|
|
|
qcom,qup_uart@0xa90000 {
|
|
compatible = "qcom,msm-geni-serial-hs";
|
|
reg = <0xa90000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x4c 0x27 0x69 0x27 0x6a>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x189 0x18a 0x18b>;
|
|
pinctrl-1 = <0x189 0x18a 0x18b>;
|
|
interrupts-extended = <0x01 0x00 0x165 0x00 0x16c 0x71 0x00>;
|
|
status = "disabled";
|
|
qcom,wakeup-byte = <0xfd>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
phandle = <0x354>;
|
|
};
|
|
|
|
qcom,qup_uart@0xa94000 {
|
|
compatible = "qcom,msm-geni-serial-hs";
|
|
reg = <0xa94000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x61 0x27 0x69 0x27 0x6a>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x18c 0x18d 0x18e>;
|
|
pinctrl-1 = <0x18c 0x18d 0x18e>;
|
|
interrupts-extended = <0x01 0x00 0x166 0x00 0x16c 0x5c 0x00>;
|
|
status = "disabled";
|
|
qcom,wakeup-byte = <0xfd>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
phandle = <0x355>;
|
|
};
|
|
|
|
spi@0xa80000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0xa80000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x57 0x27 0x69 0x27 0x6a>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x18f>;
|
|
pinctrl-1 = <0x190>;
|
|
interrupts = <0x00 0x161 0x00>;
|
|
spi-max-frequency = <0x2faf080>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
dmas = <0x17b 0x00 0x00 0x01 0x40 0x00 0x17b 0x01 0x00 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "okay";
|
|
phandle = <0x5bd>;
|
|
|
|
etspi-spi@0 {
|
|
compatible = "etspi,et7xx";
|
|
reg = <0x00>;
|
|
spi-max-frequency = <0x2faf080>;
|
|
etspi-min_cpufreq_limit = <0x211b00>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x559>;
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
etspi-regulator = "pm6150l_l7";
|
|
etspi-sleepPin = <0x16c 0x3a 0x00>;
|
|
etspi-chipid = "ET713";
|
|
etspi-modelinfo = "A715";
|
|
etspi-position = "14.42,0.00,9.10,9.10,14.80,14.80,12.00,12.00,5.00";
|
|
etspi-rb = "555,-1,-1";
|
|
};
|
|
};
|
|
|
|
spi@0xa84000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0xa84000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x59 0x27 0x69 0x27 0x6a>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x191>;
|
|
pinctrl-1 = <0x192>;
|
|
interrupts = <0x00 0x162 0x00>;
|
|
spi-max-frequency = <0x2faf080>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
dmas = <0x17b 0x00 0x01 0x01 0x40 0x00 0x17b 0x01 0x01 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x357>;
|
|
};
|
|
|
|
spi@0xa88000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0xa88000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x5b 0x27 0x69 0x27 0x6a>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x193>;
|
|
pinctrl-1 = <0x194>;
|
|
interrupts = <0x00 0x163 0x00>;
|
|
spi-max-frequency = <0x2faf080>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
dmas = <0x17b 0x00 0x02 0x01 0x40 0x00 0x17b 0x01 0x02 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x358>;
|
|
};
|
|
|
|
spi@0xa90000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0xa90000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x5f 0x27 0x69 0x27 0x6a>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x195>;
|
|
pinctrl-1 = <0x196>;
|
|
interrupts = <0x00 0x165 0x00>;
|
|
spi-max-frequency = <0x2faf080>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
dmas = <0x17b 0x00 0x04 0x01 0x40 0x00 0x17b 0x01 0x04 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x359>;
|
|
};
|
|
|
|
spi@0xa94000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0xa94000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x61 0x27 0x69 0x27 0x6a>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x197>;
|
|
pinctrl-1 = <0x198>;
|
|
interrupts = <0x00 0x166 0x00>;
|
|
spi-max-frequency = <0x2faf080>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
dmas = <0x17b 0x00 0x05 0x01 0x40 0x00 0x17b 0x01 0x05 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x35a>;
|
|
};
|
|
|
|
qcom,vidc0 {
|
|
compatible = "qcom,msm-vidc\0qcom,sdmmagpie-vidc";
|
|
status = "ok";
|
|
sku-index = <0x00>;
|
|
reg = <0xaa00000 0x200000>;
|
|
interrupts = <0x00 0xae 0x04>;
|
|
iris-ctl-supply = <0xac>;
|
|
vcodec-supply = <0x199>;
|
|
cvp-supply = <0x19a>;
|
|
clock-names = "video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk";
|
|
clocks = <0x28 0x08 0x28 0x03 0x28 0x05 0x28 0x07 0x28 0x04 0x28 0x06 0x28 0x09>;
|
|
qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk";
|
|
qcom,clock-configs = <0x00 0x00 0x00 0x01 0x01 0x01 0x00>;
|
|
qcom,allowed-clock-rates = <0xe4e1c00 0x14257880 0x15c17540>;
|
|
qcom,cx-ipeak-data = <0x19b 0x05>;
|
|
qcom,clock-freq-threshold = <0x1fc4ef40>;
|
|
phandle = <0x35b>;
|
|
|
|
bus_cnoc {
|
|
compatible = "qcom,msm-vidc,bus";
|
|
label = "cnoc";
|
|
qcom,bus-master = <0x01>;
|
|
qcom,bus-slave = <0x254>;
|
|
qcom,bus-governor = "performance";
|
|
qcom,bus-range-kbps = <0x3e8 0x3e8>;
|
|
};
|
|
|
|
venus_bus_ddr {
|
|
compatible = "qcom,msm-vidc,bus";
|
|
label = "venus-ddr";
|
|
qcom,bus-master = <0x3f>;
|
|
qcom,bus-slave = <0x200>;
|
|
qcom,bus-governor = "msm-vidc-ddr";
|
|
qcom,bus-range-kbps = <0x3e8 0x63af88>;
|
|
};
|
|
|
|
arm9_bus_ddr {
|
|
compatible = "qcom,msm-vidc,bus";
|
|
label = "venus-arm9-ddr";
|
|
qcom,bus-master = <0x3f>;
|
|
qcom,bus-slave = <0x200>;
|
|
qcom,bus-governor = "performance";
|
|
qcom,bus-range-kbps = <0x3e8 0x3e8>;
|
|
};
|
|
|
|
non_secure_cb {
|
|
compatible = "qcom,msm-vidc,context-bank";
|
|
label = "venus_ns";
|
|
iommus = <0x30 0x1080 0x60>;
|
|
buffer-types = <0xfff>;
|
|
virtual-addr-pool = <0x25800000 0xba800000>;
|
|
};
|
|
|
|
secure_non_pixel_cb {
|
|
compatible = "qcom,msm-vidc,context-bank";
|
|
label = "venus_sec_non_pixel";
|
|
iommus = <0x30 0x1084 0x60>;
|
|
buffer-types = <0x480>;
|
|
virtual-addr-pool = <0x1000000 0x24800000>;
|
|
qcom,secure-context-bank;
|
|
};
|
|
|
|
secure_bitstream_cb {
|
|
compatible = "qcom,msm-vidc,context-bank";
|
|
label = "venus_sec_bitstream";
|
|
iommus = <0x30 0x1081 0x04>;
|
|
buffer-types = <0x241>;
|
|
virtual-addr-pool = <0x500000 0xdfb00000>;
|
|
qcom,secure-context-bank;
|
|
};
|
|
|
|
secure_pixel_cb {
|
|
compatible = "qcom,msm-vidc,context-bank";
|
|
label = "venus_sec_pixel";
|
|
iommus = <0x30 0x1083 0x20>;
|
|
buffer-types = <0x106>;
|
|
virtual-addr-pool = <0x500000 0xdfb00000>;
|
|
qcom,secure-context-bank;
|
|
};
|
|
|
|
qcom,msm-vidc,mem_cdsp {
|
|
compatible = "qcom,msm-vidc,mem-cdsp";
|
|
memory-region = <0x19c>;
|
|
};
|
|
};
|
|
|
|
qcom,vidc1 {
|
|
compatible = "qcom,msm-vidc\0qcom,sdmmagpie-vidc";
|
|
status = "ok";
|
|
sku-index = <0x01>;
|
|
reg = <0xaa00000 0x200000>;
|
|
interrupts = <0x00 0xae 0x04>;
|
|
iris-ctl-supply = <0xac>;
|
|
vcodec-supply = <0x199>;
|
|
cvp-supply = <0x19a>;
|
|
clock-names = "video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk";
|
|
clocks = <0x28 0x08 0x28 0x03 0x28 0x05 0x28 0x07 0x28 0x04 0x28 0x06 0x28 0x09>;
|
|
qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi\0video_cc_mvs0_ctl_axi\0video_cc_mvs1_ctl_axi\0core_clk\0vcodec_clk\0cvp_clk\0iface_clk";
|
|
qcom,clock-configs = <0x00 0x00 0x00 0x01 0x01 0x01 0x00>;
|
|
qcom,allowed-clock-rates = <0xbebc200>;
|
|
phandle = <0x35c>;
|
|
|
|
bus_cnoc {
|
|
compatible = "qcom,msm-vidc,bus";
|
|
label = "cnoc";
|
|
qcom,bus-master = <0x01>;
|
|
qcom,bus-slave = <0x254>;
|
|
qcom,bus-governor = "performance";
|
|
qcom,bus-range-kbps = <0x3e8 0x3e8>;
|
|
};
|
|
|
|
venus_bus_ddr {
|
|
compatible = "qcom,msm-vidc,bus";
|
|
label = "venus-ddr";
|
|
qcom,bus-master = <0x3f>;
|
|
qcom,bus-slave = <0x200>;
|
|
qcom,bus-governor = "msm-vidc-ddr";
|
|
qcom,bus-range-kbps = <0x3e8 0x63af88>;
|
|
};
|
|
|
|
arm9_bus_ddr {
|
|
compatible = "qcom,msm-vidc,bus";
|
|
label = "venus-arm9-ddr";
|
|
qcom,bus-master = <0x3f>;
|
|
qcom,bus-slave = <0x200>;
|
|
qcom,bus-governor = "performance";
|
|
qcom,bus-range-kbps = <0x3e8 0x3e8>;
|
|
};
|
|
|
|
non_secure_cb {
|
|
compatible = "qcom,msm-vidc,context-bank";
|
|
label = "venus_ns";
|
|
iommus = <0x30 0x1080 0x60>;
|
|
buffer-types = <0xfff>;
|
|
virtual-addr-pool = <0x25800000 0xba800000>;
|
|
};
|
|
|
|
secure_non_pixel_cb {
|
|
compatible = "qcom,msm-vidc,context-bank";
|
|
label = "venus_sec_non_pixel";
|
|
iommus = <0x30 0x1084 0x60>;
|
|
buffer-types = <0x480>;
|
|
virtual-addr-pool = <0x1000000 0x24800000>;
|
|
qcom,secure-context-bank;
|
|
};
|
|
|
|
secure_bitstream_cb {
|
|
compatible = "qcom,msm-vidc,context-bank";
|
|
label = "venus_sec_bitstream";
|
|
iommus = <0x30 0x1081 0x04>;
|
|
buffer-types = <0x241>;
|
|
virtual-addr-pool = <0x500000 0xdfb00000>;
|
|
qcom,secure-context-bank;
|
|
};
|
|
|
|
secure_pixel_cb {
|
|
compatible = "qcom,msm-vidc,context-bank";
|
|
label = "venus_sec_pixel";
|
|
iommus = <0x30 0x1083 0x20>;
|
|
buffer-types = <0x106>;
|
|
virtual-addr-pool = <0x500000 0xdfb00000>;
|
|
qcom,secure-context-bank;
|
|
};
|
|
|
|
qcom,msm-vidc,mem_cdsp {
|
|
compatible = "qcom,msm-vidc,mem-cdsp";
|
|
memory-region = <0x19c>;
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_pll@ae94a00 {
|
|
compatible = "qcom,mdss_dsi_pll_10nm";
|
|
label = "MDSS DSI 0 PLL";
|
|
cell-index = <0x00>;
|
|
#clock-cells = <0x01>;
|
|
reg = <0xae94a00 0x1e0 0xae94400 0x800 0xaf03000 0x08 0xae94200 0x100>;
|
|
reg-names = "pll_base\0phy_base\0gdsc_base\0dynamic_pll_base";
|
|
clocks = <0x2a 0x01>;
|
|
clock-names = "iface_clk";
|
|
clock-rate = <0x00>;
|
|
memory-region = <0x19d>;
|
|
gdsc-supply = <0xc3>;
|
|
phandle = <0x35d>;
|
|
|
|
qcom,platform-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,platform-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "gdsc";
|
|
qcom,supply-min-voltage = <0x00>;
|
|
qcom,supply-max-voltage = <0x00>;
|
|
qcom,supply-enable-load = <0x00>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_pll@ae96a00 {
|
|
compatible = "qcom,mdss_dsi_pll_10nm";
|
|
label = "MDSS DSI 1 PLL";
|
|
cell-index = <0x01>;
|
|
#clock-cells = <0x01>;
|
|
reg = <0xae96a00 0x1e0 0xae96400 0x800 0xaf03000 0x08 0xae96200 0x100>;
|
|
reg-names = "pll_base\0phy_base\0gdsc_base\0dynamic_pll_base";
|
|
clocks = <0x2a 0x01>;
|
|
clock-names = "iface_clk";
|
|
clock-rate = <0x00>;
|
|
gdsc-supply = <0xc3>;
|
|
phandle = <0x35e>;
|
|
|
|
qcom,platform-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,platform-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "gdsc";
|
|
qcom,supply-min-voltage = <0x00>;
|
|
qcom,supply-max-voltage = <0x00>;
|
|
qcom,supply-enable-load = <0x00>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dp_pll@ae90000 {
|
|
compatible = "qcom,mdss_dp_pll_10nm";
|
|
label = "MDSS DP PLL";
|
|
cell-index = <0x00>;
|
|
#clock-cells = <0x01>;
|
|
reg = <0x88ea000 0x200 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf03000 0x08>;
|
|
reg-names = "pll_base\0phy_base\0ln_tx0_base\0ln_tx1_base\0gdsc_base";
|
|
gdsc-supply = <0xc3>;
|
|
clocks = <0x2a 0x01 0x2f 0x00 0x27 0x92 0x27 0x97 0x27 0x96>;
|
|
clock-names = "iface_clk\0ref_clk_src\0ref_clk\0cfg_ahb_clk\0pipe_clk";
|
|
clock-rate = <0x00>;
|
|
phandle = <0x1a2>;
|
|
|
|
qcom,platform-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,platform-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "gdsc";
|
|
qcom,supply-min-voltage = <0x00>;
|
|
qcom,supply-max-voltage = <0x00>;
|
|
qcom,supply-enable-load = <0x00>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_mdp@ae00000 {
|
|
compatible = "qcom,sde-kms";
|
|
reg = <0xae00000 0x84208 0xaeb0000 0x2008 0xaeac000 0x214>;
|
|
reg-names = "mdp_phys\0vbif_phys\0regdma_phys";
|
|
clocks = <0x27 0x1c 0x27 0x1f 0x27 0x20 0x2a 0x01 0x2a 0x1a 0x2a 0x26 0x2a 0x1c 0x2a 0x22>;
|
|
clock-names = "gcc_iface\0gcc_bus\0gcc_nrt_bus\0iface_clk\0core_clk\0vsync_clk\0lut_clk\0rot_clk";
|
|
clock-rate = <0x00 0x00 0x00 0x00 0x11e1a300 0x124f800 0xbebc200 0xbebc200>;
|
|
clock-max-rate = <0x00 0x00 0x00 0x00 0x19a14780 0x124f800 0x19a14780 0x19a14780>;
|
|
qcom,dss-cx-ipeak = <0x19b 0x04>;
|
|
interrupts = <0x00 0x53 0x00>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x01>;
|
|
iommus = <0x30 0x800 0x440>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
#power-domain-cells = <0x00>;
|
|
qcom,sde-off = <0x1000>;
|
|
qcom,sde-len = <0x45c>;
|
|
qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600 0x2800 0x2a00>;
|
|
qcom,sde-ctl-size = <0x1e0>;
|
|
qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none";
|
|
qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x00 0x00>;
|
|
qcom,sde-mixer-size = <0x320>;
|
|
qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none";
|
|
qcom,sde-mixer-cwb-pref = "none\0none\0cwb\0cwb\0none\0none";
|
|
qcom,sde-dspp-top-off = <0x1300>;
|
|
qcom,sde-dspp-top-size = <0x80>;
|
|
qcom,sde-dspp-off = <0x55000 0x57000>;
|
|
qcom,sde-dspp-size = <0x1800>;
|
|
qcom,sde-dest-scaler-top-off = <0x61000>;
|
|
qcom,sde-dest-scaler-top-size = <0x1c>;
|
|
qcom,sde-dest-scaler-off = <0x800 0x1000>;
|
|
qcom,sde-dest-scaler-size = <0xa0>;
|
|
qcom,sde-wb-off = <0x66000>;
|
|
qcom,sde-wb-size = <0x2c8>;
|
|
qcom,sde-wb-xin-id = <0x06>;
|
|
qcom,sde-wb-id = <0x02>;
|
|
qcom,sde-wb-clk-ctrl = <0x3b8 0x18>;
|
|
qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000 0x6c800>;
|
|
qcom,sde-intf-size = <0x2b8>;
|
|
qcom,sde-intf-type = "dp\0dsi\0dsi\0dp";
|
|
qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>;
|
|
qcom,sde-pp-slave = <0x00 0x00 0x00 0x00>;
|
|
qcom,sde-pp-size = <0xd4>;
|
|
qcom,sde-pp-merge-3d-id = <0x00 0x00 0x01 0x01>;
|
|
qcom,sde-merge-3d-off = "\0\b@\0\0\bA";
|
|
qcom,sde-merge-3d-size = <0x100>;
|
|
qcom,sde-te2-off = <0x2000 0x2000 0x00 0x00>;
|
|
qcom,sde-cdm-off = <0x7a200>;
|
|
qcom,sde-cdm-size = <0x224>;
|
|
qcom,sde-dsc-off = <0x81000 0x81400>;
|
|
qcom,sde-dsc-size = <0x140>;
|
|
qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>;
|
|
qcom,sde-dither-version = <0x10000>;
|
|
qcom,sde-dither-size = <0x20>;
|
|
qcom,sde-sspp-type = "vig\0vig\0dma\0dma\0dma";
|
|
qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>;
|
|
qcom,sde-sspp-src-size = <0x1f0>;
|
|
qcom,sde-sspp-xin-id = <0x00 0x04 0x01 0x05 0x09>;
|
|
qcom,sde-sspp-excl-rect = <0x01 0x01 0x01 0x01 0x01>;
|
|
qcom,sde-sspp-smart-dma-priority = <0x04 0x05 0x01 0x02 0x03>;
|
|
qcom,sde-smart-dma-rev = "smart_dma_v2p5";
|
|
qcom,sde-mixer-pair-mask = <0x02 0x01 0x04 0x03 0x00 0x00>;
|
|
qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>;
|
|
qcom,sde-max-per-pipe-bw-kbps = <0x3567e0 0x3567e0 0x3567e0 0x3567e0 0x3567e0>;
|
|
qcom,sde-sspp-clk-ctrl = <0x2ac 0x00 0x2b4 0x00 0x2ac 0x08 0x2b4 0x08 0x2bc 0x08>;
|
|
qcom,sde-sspp-csc-off = <0x1a00>;
|
|
qcom,sde-csc-type = "csc-10bit";
|
|
qcom,sde-qseed-type = "qseedv3lite";
|
|
qcom,sde-sspp-qseed-off = <0xa00>;
|
|
qcom,sde-mixer-linewidth = <0xa00>;
|
|
qcom,sde-sspp-linewidth = <0xb40>;
|
|
qcom,sde-wb-linewidth = <0x1000>;
|
|
qcom,sde-mixer-blendstages = <0x0b>;
|
|
qcom,sde-highest-bank-bit = <0x01>;
|
|
qcom,sde-ubwc-version = <0x200>;
|
|
qcom,sde-panic-per-pipe;
|
|
qcom,sde-has-cdp;
|
|
qcom,sde-has-src-split;
|
|
qcom,sde-pipe-order-version = <0x01>;
|
|
qcom,sde-has-dim-layer;
|
|
qcom,sde-has-idle-pc;
|
|
qcom,sde-has-dest-scaler;
|
|
qcom,sde-max-dest-scaler-input-linewidth = <0x800>;
|
|
qcom,sde-max-dest-scaler-output-linewidth = <0xa00>;
|
|
qcom,sde-max-bw-low-kbps = <0x6c5660>;
|
|
qcom,sde-max-bw-high-kbps = <0x6c5660>;
|
|
qcom,sde-min-core-ib-kbps = <0x249f00>;
|
|
qcom,sde-min-llcc-ib-kbps = "\0\f5";
|
|
qcom,sde-min-dram-ib-kbps = "\0\f5";
|
|
qcom,sde-dram-channels = <0x02>;
|
|
qcom,sde-num-nrt-paths = <0x00>;
|
|
qcom,sde-dspp-ad-version = <0x40000>;
|
|
qcom,sde-dspp-ad-off = <0x28000 0x27000>;
|
|
qcom,sde-vbif-off = <0x00>;
|
|
qcom,sde-vbif-size = <0x1040>;
|
|
qcom,sde-vbif-id = <0x00>;
|
|
qcom,sde-vbif-memtype-0 = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>;
|
|
qcom,sde-vbif-memtype-1 = <0x03 0x03 0x03 0x03 0x03 0x03>;
|
|
qcom,sde-vbif-qos-rt-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06>;
|
|
qcom,sde-vbif-qos-nrt-remap = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>;
|
|
qcom,sde-danger-lut = <0x0f 0xffff 0x00 0x00 0xffff>;
|
|
qcom,sde-safe-lut-linear = <0x00 0xfff8>;
|
|
qcom,sde-safe-lut-macrotile = <0x00 0xf000>;
|
|
qcom,sde-safe-lut-macrotile-qseed = <0x00 0xf000>;
|
|
qcom,sde-safe-lut-nrt = <0x00 0xffff>;
|
|
qcom,sde-safe-lut-cwb = <0x00 0xffff>;
|
|
qcom,sde-qos-lut-linear = <0x00 0x112222 0x22223357>;
|
|
qcom,sde-qos-lut-macrotile = <0x00 0x112233 0x44556677>;
|
|
qcom,sde-qos-lut-macrotile-qseed = <0x00 0x112233 0x66777777>;
|
|
qcom,sde-qos-lut-nrt = <0x00 0x00 0x00>;
|
|
qcom,sde-qos-lut-cwb = <0x00 0x75300000 0x00>;
|
|
qcom,sde-cdp-setting = <0x01 0x01 0x01 0x00>;
|
|
qcom,sde-qos-cpu-mask = <0x03>;
|
|
qcom,sde-qos-cpu-dma-latency = <0x12c>;
|
|
qcom,sde-reg-dma-off = <0x00>;
|
|
qcom,sde-reg-dma-version = <0x10001>;
|
|
qcom,sde-reg-dma-trigger-off = <0x119c>;
|
|
qcom,sde-secure-sid-mask = <0x4400801>;
|
|
phandle = <0x19e>;
|
|
#cooling-cells = <0x02>;
|
|
connectors = <0x360 0x4f1 0x4f2 0x36a 0x4f3>;
|
|
|
|
qcom,sde-sspp-vig-blocks {
|
|
qcom,sde-vig-csc-off = <0x1a00>;
|
|
qcom,sde-vig-qseed-off = <0xa00>;
|
|
qcom,sde-vig-qseed-size = <0xa0>;
|
|
qcom,sde-vig-gamut = <0x1d00 0x50000>;
|
|
qcom,sde-vig-igc = <0x1d00 0x50000>;
|
|
qcom,sde-vig-inverse-pma;
|
|
};
|
|
|
|
qcom,sde-sspp-dma-blocks {
|
|
|
|
dgm@0 {
|
|
qcom,sde-dma-igc = <0x400 0x50000>;
|
|
qcom,sde-dma-gc = <0x600 0x50000>;
|
|
qcom,sde-dma-inverse-pma;
|
|
qcom,sde-dma-csc-off = <0x200>;
|
|
};
|
|
|
|
dgm@1 {
|
|
qcom,sde-dma-igc = <0x1400 0x50000>;
|
|
qcom,sde-dma-gc = <0x600 0x50000>;
|
|
qcom,sde-dma-inverse-pma;
|
|
qcom,sde-dma-csc-off = <0x1200>;
|
|
};
|
|
};
|
|
|
|
qcom,sde-dspp-blocks {
|
|
qcom,sde-dspp-igc = <0x00 0x30001>;
|
|
qcom,sde-dspp-hsic = <0x800 0x10007>;
|
|
qcom,sde-dspp-memcolor = <0x880 0x10007>;
|
|
qcom,sde-dspp-hist = <0x800 0x10007>;
|
|
qcom,sde-dspp-sixzone = <0x900 0x10007>;
|
|
qcom,sde-dspp-vlut = <0xa00 0x10008>;
|
|
qcom,sde-dspp-gamut = <0x1000 0x40001>;
|
|
qcom,sde-dspp-pcc = <0x1700 0x40000>;
|
|
qcom,sde-dspp-gc = <0x17c0 0x10008>;
|
|
qcom,sde-dspp-dither = <0x82c 0x10007>;
|
|
};
|
|
|
|
qcom,smmu_sde_sec_cb {
|
|
compatible = "qcom,smmu_sde_sec";
|
|
iommus = <0x30 0x801 0x440>;
|
|
phandle = <0x35f>;
|
|
};
|
|
|
|
qcom,sde-data-bus {
|
|
qcom,msm-bus,name = "mdss_sde";
|
|
qcom,msm-bus,num-cases = <0x03>;
|
|
qcom,msm-bus,num-paths = <0x02>;
|
|
qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x17 0x200 0x00 0x00 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800>;
|
|
};
|
|
|
|
qcom,sde-reg-bus {
|
|
qcom,msm-bus,name = "mdss_reg";
|
|
qcom,msm-bus,num-cases = <0x04>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00 0x01 0x24e 0x00 0x249f0 0x01 0x24e 0x00 0x493e0>;
|
|
};
|
|
|
|
qcom,mdss_dsi_sim_video {
|
|
qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-panel-hdr-enabled;
|
|
qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;
|
|
qcom,mdss-dsi-panel-mode-switch;
|
|
qcom,mdss-dsi-panel-peak-brightness = <0x401640>;
|
|
qcom,mdss-dsi-panel-blackness-level = <0xc9e>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-t-clk-post = <0x0d>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x2d>;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>;
|
|
qcom,panel-ack-disabled;
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-wd;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
phandle = <0x4cf>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-video-mode;
|
|
qcom,mdss-dsi-panel-width = <0x280>;
|
|
qcom,mdss-dsi-panel-height = <0x1e0>;
|
|
qcom,mdss-dsi-h-front-porch = <0x08>;
|
|
qcom,mdss-dsi-h-back-porch = <0x08>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x08>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x06>;
|
|
qcom,mdss-dsi-v-front-porch = <0x06>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-timings = <0x00 0x00 0x00>;
|
|
qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00];
|
|
qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,cmd-to-video-mode-post-switch-commands = [32 01 00 00 00 00 02 00 00];
|
|
qcom,cmd-to-video-mode-post-switch-commands-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5020400>;
|
|
qcom,display-topology = <0x01 0x00 0x01 0x02 0x00 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
|
|
timing@1 {
|
|
qcom,mdss-dsi-cmd-mode;
|
|
qcom,mdss-dsi-panel-width = <0x280>;
|
|
qcom,mdss-dsi-panel-height = <0x1e0>;
|
|
qcom,mdss-dsi-h-front-porch = <0x08>;
|
|
qcom,mdss-dsi-h-back-porch = <0x08>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x08>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x06>;
|
|
qcom,mdss-dsi-v-front-porch = <0x06>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-timings = <0x00 0x00 0x00>;
|
|
qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00];
|
|
qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,video-to-cmd-mode-post-switch-commands = [32 01 00 00 00 00 02 00 00];
|
|
qcom,video-to-cmd-mode-post-switch-commands-state = "dsi_lp_mode";
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sim_cmd {
|
|
qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-t-clk-post = <0x0c>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x29>;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-wd;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,mdss-dsi-panel-hdr-enabled;
|
|
qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;
|
|
qcom,mdss-dsi-panel-peak-brightness = <0x401640>;
|
|
qcom,mdss-dsi-panel-blackness-level = <0xc9e>;
|
|
qcom,panel-ack-disabled;
|
|
qcom,ulps-enabled;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
phandle = <0x4d1>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x5a0>;
|
|
qcom,mdss-dsi-panel-height = <0xa00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x78>;
|
|
qcom,mdss-dsi-h-back-porch = <0x64>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x28>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x64>;
|
|
qcom,mdss-dsi-v-front-porch = <0x64>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x28>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>;
|
|
qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x28>;
|
|
qcom,mdss-dsc-slice-width = <0x2d0>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4020400>;
|
|
qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>;
|
|
qcom,default-topology-index = <0x01>;
|
|
qcom,panel-roi-alignment = <0x2d0 0x28 0x2d0 0x28 0x2d0 0x28>;
|
|
qcom,partial-update-enabled = "single_roi";
|
|
};
|
|
|
|
timing@1 {
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-h-front-porch = <0x78>;
|
|
qcom,mdss-dsi-h-back-porch = <0x1cc>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x28>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x64>;
|
|
qcom,mdss-dsi-v-front-porch = <0x2e4>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x28>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>;
|
|
qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x28>;
|
|
qcom,mdss-dsc-slice-width = <0x21c>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4020400>;
|
|
qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>;
|
|
qcom,default-topology-index = <0x01>;
|
|
qcom,panel-roi-alignment = <0x21c 0x28 0x21c 0x28 0x21c 0x28>;
|
|
qcom,partial-update-enabled = "single_roi";
|
|
};
|
|
|
|
timing@2 {
|
|
qcom,mdss-dsi-panel-width = <0x2d0>;
|
|
qcom,mdss-dsi-panel-height = <0x500>;
|
|
qcom,mdss-dsi-h-front-porch = <0x64>;
|
|
qcom,mdss-dsi-h-back-porch = <0x348>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x28>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x64>;
|
|
qcom,mdss-dsi-v-front-porch = <0x564>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x28>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>;
|
|
qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x28>;
|
|
qcom,mdss-dsc-slice-width = <0x168>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4020400>;
|
|
qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>;
|
|
qcom,default-topology-index = <0x01>;
|
|
qcom,panel-roi-alignment = <0x168 0x28 0x168 0x28 0x168 0x28>;
|
|
qcom,partial-update-enabled = "single_roi";
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sim_dsc_375_cmd {
|
|
qcom,mdss-dsi-panel-name = "Simulator cmd mode DSC 3.75:1 dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,adjust-timer-wakeup-ms = <0x01>;
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-wd;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,panel-ack-disabled;
|
|
qcom,mdss-dsi-t-clk-post = <0x0d>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x2d>;
|
|
qcom,ulps-enabled;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
phandle = <0x4d3>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-width = <0x5a0>;
|
|
qcom,mdss-dsi-panel-height = <0xa00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x64>;
|
|
qcom,mdss-dsi-h-back-porch = <0x20>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x10>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x08>;
|
|
qcom,mdss-dsi-v-front-porch = <0x0a>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2723115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>;
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x10>;
|
|
qcom,mdss-dsc-slice-width = <0x2d0>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x02>;
|
|
qcom,mdss-dsc-bit-per-component = <0x0a>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4020400>;
|
|
qcom,display-topology = <0x01 0x01 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
|
|
timing@1 {
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-h-front-porch = <0x00>;
|
|
qcom,mdss-dsi-h-back-porch = <0x00>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x00>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x00>;
|
|
qcom,mdss-dsi-v-front-porch = <0x00>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x00>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>;
|
|
qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x10>;
|
|
qcom,mdss-dsc-slice-width = <0x21c>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x02>;
|
|
qcom,mdss-dsc-bit-per-component = <0x0a>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x150505 0x201f0505 0x3020400>;
|
|
qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_dual_sim_video {
|
|
qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-panel-broadcast-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0xc8 0x01 0x14>;
|
|
qcom,panel-ack-disabled;
|
|
qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>;
|
|
qcom,mdss-dsi-t-clk-post = <0x0d>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x2d>;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
phandle = <0x4d0>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x500>;
|
|
qcom,mdss-dsi-panel-height = <0x5a0>;
|
|
qcom,mdss-dsi-h-front-porch = <0x78>;
|
|
qcom,mdss-dsi-h-back-porch = <0x2c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x10>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x04>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];
|
|
qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];
|
|
qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5020400>;
|
|
qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_dual_sim_cmd {
|
|
qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,cmd-sync-wait-broadcast;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>;
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-wd;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,panel-ack-disabled;
|
|
qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>;
|
|
qcom,mdss-dsi-t-clk-post = <0x0d>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x2d>;
|
|
qcom,ulps-enabled;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
phandle = <0x4d2>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x21c>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-h-front-porch = <0x1c>;
|
|
qcom,mdss-dsi-h-back-porch = <0x04>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0c>;
|
|
qcom,mdss-dsi-v-front-porch = <0x0c>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x78>;
|
|
qcom,mdss-dsi-on-command = <0x5010000 0x129>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];
|
|
qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];
|
|
qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x240909 0x26240909 0x6020400>;
|
|
qcom,display-topology = <0x02 0x00 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
|
|
timing@1 {
|
|
qcom,mdss-dsi-panel-width = <0x500>;
|
|
qcom,mdss-dsi-panel-height = <0x5a0>;
|
|
qcom,mdss-dsi-h-front-porch = <0x78>;
|
|
qcom,mdss-dsi-h-back-porch = <0x2c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x10>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x04>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = <0x5010000 0x129>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];
|
|
qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];
|
|
qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5020400>;
|
|
qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
|
|
timing@2 {
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0xf00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x1e>;
|
|
qcom,mdss-dsi-h-back-porch = <0x64>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x07>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x01>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x28>;
|
|
qcom,mdss-dsi-on-command = <0x5010000 0x129>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];
|
|
qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];
|
|
qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4020400>;
|
|
qcom,display-topology = <0x02 0x00 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_dual_sim_dsc_375_cmd {
|
|
qcom,mdss-dsi-panel-name = "Sim dual cmd mode DSC 3.75:1 dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,cmd-sync-wait-broadcast;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>;
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-wd;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,panel-ack-disabled;
|
|
qcom,mdss-dsi-t-clk-post = <0x0d>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x2d>;
|
|
qcom,ulps-enabled;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
phandle = <0x4d4>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0xf00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x1e>;
|
|
qcom,mdss-dsi-h-back-porch = <0x64>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x07>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x01>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x20>;
|
|
qcom,mdss-dsc-slice-width = <0x438>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x0a>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5020400>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
|
|
timing@1 {
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-width = <0x2d0>;
|
|
qcom,mdss-dsi-panel-height = <0xa00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x64>;
|
|
qcom,mdss-dsi-h-back-porch = <0x20>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x10>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x07>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x01>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x10>;
|
|
qcom,mdss-dsc-slice-width = <0x2d0>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x0a>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4020400>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sw43404_amoled_wqhd_video {
|
|
qcom,mdss-dsi-panel-name = "sw43404 amoled video mode dsi boe panel with DSC";
|
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
|
qcom,mdss-dsi-panel-physical-type = "oled";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,adjust-timer-wakeup-ms = <0x01>;
|
|
qcom,mdss-dsi-panel-hdr-enabled;
|
|
qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;
|
|
qcom,mdss-dsi-panel-peak-brightness = <0x401640>;
|
|
qcom,mdss-dsi-panel-blackness-level = <0xc9e>;
|
|
qcom,mdss-dsi-t-clk-post = <0x0a>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x21>;
|
|
qcom,esd-check-enabled;
|
|
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
|
qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;
|
|
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-status-read-length = <0x01>;
|
|
qcom,dsi-supported-dfps-list = <0x3c 0x39 0x37>;
|
|
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
|
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";
|
|
qcom,panel-supply-entries = <0x4cb>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0x3ff>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
phandle = <0x4cc>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x5a0>;
|
|
qcom,mdss-dsi-panel-height = <0xb40>;
|
|
qcom,mdss-dsi-h-front-porch = <0x0a>;
|
|
qcom,mdss-dsi-h-back-porch = <0x0a>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x0c>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0a>;
|
|
qcom,mdss-dsi-v-front-porch = <0x0a>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x01>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 39 01 00 00 00 00 06 b2 00 5d 04 80 49 15 01 00 00 00 00 02 3d 10 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 55 08 39 01 00 00 00 00 09 f8 00 08 10 08 2d 00 00 2d 39 01 00 00 3c 00 03 51 00 00 05 01 00 00 50 00 02 11 00 39 01 00 00 00 00 03 b0 34 04 39 01 00 00 00 00 05 c1 00 00 00 46 39 01 00 00 00 00 03 b0 a5 00 0a 01 00 00 00 00 80 11 00 00 89 30 80 0b 40 05 a0 02 d0 02 d0 02 d0 02 00 02 68 00 20 4e a8 00 0a 00 0c 00 23 00 1c 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05 01 00 00 78 00 02 29 00];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x2d0>;
|
|
qcom,mdss-dsc-slice-width = <0x2d0>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x02>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x130504 0x1f1e0505 0x3020400>;
|
|
qcom,display-topology = <0x02 0x02 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sw43404_amoled_wqhd_cmd {
|
|
qcom,mdss-dsi-panel-name = "sw43404 amoled cmd mode dsi boe panel with DSC";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-panel-physical-type = "oled";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,mdss-dsi-panel-hdr-enabled;
|
|
qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;
|
|
qcom,mdss-dsi-panel-peak-brightness = <0x401640>;
|
|
qcom,mdss-dsi-panel-blackness-level = <0xc9e>;
|
|
qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>;
|
|
qcom,ulps-enabled;
|
|
qcom,mdss-dsi-t-clk-post = <0x0a>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x21>;
|
|
qcom,esd-check-enabled;
|
|
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
|
qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;
|
|
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-status-read-length = <0x01>;
|
|
qcom,panel-supply-entries = <0x4cb>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0x3ff>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
phandle = <0x4cd>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-width = <0x5a0>;
|
|
qcom,mdss-dsi-panel-height = <0xb40>;
|
|
qcom,mdss-dsi-h-front-porch = <0x3c>;
|
|
qcom,mdss-dsi-h-back-porch = <0x1e>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x0c>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x08>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x01>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-jitter = <0x07 0x01>;
|
|
qcom,mdss-dsi-on-command = <0x39010000 0x3b0 0xa5003901 0x00 0x35c4200 0x7010000 0x201 0xa0100 0x80 0x11000089 0x30800b40 0x5a005a0 0x2d002d0 0x2000268 0x209adb 0xa000c 0x12000e 0x180010f0 0x30c2000 0x60b0b33 0xe1c2a38 0x46546269 0x7077797b 0x7d7e0102 0x1000940 0x9be19fc 0x19fa19f8 0x1a381a78 0x1ab62af6 0x2b342b74 0x3b746bf4 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x39010000 0x3b0 0xa5003901 0x00 0x9f80008 0x10082d00 0x2d1501 0x00 0x2550805 0x100001e 0x21100 0x39010000 0x3b0 0xa5001501 0x00 0x2e01839 0x1000000 0xcc000 0x536f5150 0x51344f5a 0x33190501 0x7800 0x2350005 0x100003c 0x22900>;
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 5a 01];
|
|
qcom,mdss-dsi-qsync-on-commands-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 5a 00];
|
|
qcom,mdss-dsi-qsync-off-commands-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-lp1-command = [05 01 00 00 00 00 02 39 00];
|
|
qcom,mdss-dsi-lp1-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-nolp-command = [05 01 00 00 00 00 02 38 00];
|
|
qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0xb4>;
|
|
qcom,mdss-dsc-slice-width = <0x2d0>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x130504 0x1f1e0505 0x3020400>;
|
|
qcom,mdss-mdp-transfer-time-us = <0x32c8>;
|
|
qcom,display-topology = <0x02 0x02 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
qcom,partial-update-enabled = "single_roi";
|
|
qcom,panel-roi-alignment = <0x2d0 0xb4 0xb4 0xb4 0x5a0 0xb4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sw43404_fhd_plus_cmd {
|
|
qcom,mdss-dsi-panel-name = "sw43404 amoled boe fhd+ panel with DSC";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-panel-physical-type = "oled";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,mdss-pan-physical-width-dimension = <0x44>;
|
|
qcom,mdss-pan-physical-height-dimension = <0x8a>;
|
|
qcom,mdss-dsi-panel-hdr-enabled;
|
|
qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>;
|
|
qcom,mdss-dsi-panel-peak-brightness = <0x401640>;
|
|
qcom,mdss-dsi-panel-blackness-level = <0xc9e>;
|
|
qcom,ulps-enabled;
|
|
qcom,mdss-dsi-t-clk-post = <0x09>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x1b>;
|
|
qcom,esd-check-enabled;
|
|
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
|
qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;
|
|
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-status-read-length = <0x01>;
|
|
qcom,panel-supply-entries = <0x4cb>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0x3ff>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
qcom,platform-reset-gpio = <0x2e4 0x09 0x00>;
|
|
phandle = <0x4ce>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0x870>;
|
|
qcom,mdss-dsi-h-front-porch = <0xa0>;
|
|
qcom,mdss-dsi-h-back-porch = <0x48>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x10>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x08>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x01>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-jitter = <0x03 0x01>;
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 0a 01 00 00 00 00 80 11 00 00 89 30 80 08 70 04 38 02 1c 02 1c 02 1c 02 00 02 0e 00 20 34 29 00 07 00 0c 00 2e 00 31 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 03 b0 a5 00 15 01 00 00 00 00 02 5e 10 39 01 00 00 00 00 06 b9 bf 11 40 00 30 39 01 00 00 00 00 09 f8 00 08 10 08 2d 00 00 2d 15 01 00 00 00 00 02 55 08 05 01 00 00 1e 00 02 11 00 15 01 00 00 78 00 02 3d 01 39 01 00 00 00 00 03 b0 a5 00 05 01 00 00 78 00 02 35 00 05 01 00 00 3c 00 02 29 00];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x10e>;
|
|
qcom,mdss-dsc-slice-width = <0x21c>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0xf0303 0x1e1d0404 0x2030400>;
|
|
qcom,mdss-dsi-panel-clockrate = <0x15228c00>;
|
|
qcom,display-topology = <0x01 0x01 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
qcom,partial-update-enabled = "single_roi";
|
|
qcom,panel-roi-alignment = <0x21c 0x10e 0x10e 0x10e 0x438 0x10e>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sharp_wqhd_video {
|
|
qcom,mdss-dsi-panel-name = "Dual Sharp wqhd video mode dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x14>;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,mdss-pan-physical-width-dimension = <0x44>;
|
|
qcom,mdss-pan-physical-height-dimension = <0x79>;
|
|
qcom,adjust-timer-wakeup-ms = <0x01>;
|
|
qcom,mdss-dsi-t-clk-post = <0x0c>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x21>;
|
|
qcom,esd-check-enabled;
|
|
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
|
qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;
|
|
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-status-read-length = <0x01>;
|
|
qcom,dsi-supported-dfps-list = <0x3c 0x39 0x37>;
|
|
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
|
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";
|
|
qcom,dsi-dyn-clk-enable;
|
|
qcom,dsi-dyn-clk-list = <0x1fdf1000 0x1fbd1100 0x1f9b1200 0x1f571400 0x1f791300>;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
qcom,platform-en-gpio = <0x2e4 0x04 0x00>;
|
|
qcom,platform-bklight-en-gpio = <0x2e4 0x05 0x00>;
|
|
phandle = <0x4d5>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x2d0>;
|
|
qcom,mdss-dsi-panel-height = <0xa00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x1e>;
|
|
qcom,mdss-dsi-h-back-porch = <0x64>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x08>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x01>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 10 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 15 01 00 00 00 00 02 90 01 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 58 01 15 01 00 00 00 00 02 c9 00 15 01 00 00 00 00 02 c0 15 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x2e080a 0x1218080b 0x9030400>;
|
|
qcom,display-topology = <0x02 0x00 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sharp_wqhd_cmd {
|
|
qcom,mdss-dsi-panel-name = "Dual Sharp WQHD cmd mode dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x14>;
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,dcs-cmd-by-left;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,mdss-pan-physical-width-dimension = <0x44>;
|
|
qcom,mdss-pan-physical-height-dimension = <0x79>;
|
|
qcom,adjust-timer-wakeup-ms = <0x01>;
|
|
qcom,ulps-enabled;
|
|
qcom,mdss-dsi-t-clk-post = <0x0c>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x21>;
|
|
qcom,esd-check-enabled;
|
|
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
|
qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;
|
|
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-status-read-length = <0x01>;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
qcom,platform-reset-gpio = <0x2e4 0x09 0x00>;
|
|
qcom,platform-en-gpio = <0x2e4 0x04 0x00>;
|
|
qcom,platform-bklight-en-gpio = <0x2e4 0x05 0x00>;
|
|
phandle = <0x4d6>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x2d0>;
|
|
qcom,mdss-dsi-panel-height = <0xa00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x1e>;
|
|
qcom,mdss-dsi-h-back-porch = <0x64>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x08>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x01>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 15 01 00 00 00 00 02 90 01 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 58 01 15 01 00 00 00 00 02 c9 00 15 01 00 00 00 00 02 c0 15 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x2e080a 0x1218080b 0x9030400>;
|
|
qcom,display-topology = <0x02 0x00 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
qcom,partial-update-enabled = "single_roi";
|
|
qcom,panel-roi-alignment = <0x2d0 0xa0 0xa0 0xa0 0x5a0 0xa0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_rm69298_truly_amoled_video {
|
|
qcom,mdss-dsi-panel-name = "rm69298 amoled fhd+ video mode dsi truly panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-lp11-init;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,mdss-dsi-t-clk-post = <0x0d>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x30>;
|
|
qcom,dsi-supported-dfps-list = <0x3c 0x39 0x35>;
|
|
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
|
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
|
qcom,panel-supply-entries = <0x4cb>;
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0xff>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
qcom,platform-reset-gpio = <0x2e4 0x09 0x00>;
|
|
phandle = <0x4d7>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0x870>;
|
|
qcom,mdss-dsi-h-front-porch = <0x1e>;
|
|
qcom,mdss-dsi-h-back-porch = <0x28>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x0a>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x10>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 fe 40 15 01 00 00 00 00 02 0a 15 15 01 00 00 00 00 02 0b cc 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 80 15 01 00 00 00 00 02 0f 87 15 01 00 00 00 00 02 05 08 15 01 00 00 00 00 02 06 08 15 01 00 00 00 00 02 08 08 15 01 00 00 00 00 02 09 08 15 01 00 00 00 00 02 16 15 15 01 00 00 00 00 02 20 8d 15 01 00 00 00 00 02 21 8d 15 01 00 00 00 00 02 24 55 15 01 00 00 00 00 02 26 55 15 01 00 00 00 00 02 28 55 15 01 00 00 00 00 02 2a 55 15 01 00 00 00 00 02 2d 28 15 01 00 00 00 00 02 2f 28 15 01 00 00 00 00 02 30 1e 15 01 00 00 00 00 02 31 1e 15 01 00 00 00 00 02 37 80 15 01 00 00 00 00 02 38 40 15 01 00 00 00 00 02 39 90 15 01 00 00 00 00 02 46 43 15 01 00 00 00 00 02 47 43 15 01 00 00 00 00 02 64 02 15 01 00 00 00 00 02 6f 02 15 01 00 00 00 00 02 74 2f 15 01 00 00 00 00 02 80 16 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 fe a0 15 01 00 00 00 00 02 2b 22 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 2f 35 15 01 00 00 00 00 02 fe 60 15 01 00 00 00 00 02 00 ac 15 01 00 00 00 00 02 01 0f 15 01 00 00 00 00 02 02 ff 15 01 00 00 00 00 02 03 05 15 01 00 00 00 00 02 04 00 15 01 00 00 00 00 02 05 06 15 01 00 00 00 00 02 06 00 15 01 00 00 00 00 02 07 00 15 01 00 00 00 00 02 09 c0 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 02 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0e 00 15 01 00 00 00 00 02 0e 04 15 01 00 00 00 00 02 0f 0e 15 01 00 00 00 00 02 10 a2 15 01 00 00 00 00 02 12 c0 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 14 02 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 17 05 15 01 00 00 00 00 02 18 0e 15 01 00 00 00 00 02 19 a2 15 01 00 00 00 00 02 1b c0 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 04 15 01 00 00 00 00 02 1e 01 15 01 00 00 00 00 02 1f 00 15 01 00 00 00 00 02 20 04 15 01 00 00 00 00 02 21 24 15 01 00 00 00 00 02 22 99 15 01 00 00 00 00 02 24 c0 15 01 00 00 00 00 02 25 00 15 01 00 00 00 00 02 26 04 15 01 00 00 00 00 02 27 01 15 01 00 00 00 00 02 28 00 15 01 00 00 00 00 02 29 06 15 01 00 00 00 00 02 2a 24 15 01 00 00 00 00 02 2b 99 15 01 00 00 00 00 02 83 ca 15 01 00 00 00 00 02 84 0f 15 01 00 00 00 00 02 85 ff 15 01 00 00 00 00 02 86 0a 15 01 00 00 00 00 02 87 00 15 01 00 00 00 00 02 88 08 15 01 00 00 00 00 02 89 00 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 8b 80 15 01 00 00 00 00 02 c7 1f 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 c9 01 15 01 00 00 00 00 02 ca 1f 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 1f 15 01 00 00 00 00 02 cd 1f 15 01 00 00 00 00 02 ce 1f 15 01 00 00 00 00 02 cf 1f 15 01 00 00 00 00 02 d0 1f 15 01 00 00 00 00 02 d1 1f 15 01 00 00 00 00 02 d2 1f 15 01 00 00 00 00 02 d3 1f 15 01 00 00 00 00 02 d4 1f 15 01 00 00 00 00 02 d5 1f 15 01 00 00 00 00 02 d6 1f 15 01 00 00 00 00 02 d7 1f 15 01 00 00 00 00 02 d8 1f 15 01 00 00 00 00 02 d9 1f 15 01 00 00 00 00 02 da 1f 15 01 00 00 00 00 02 db 1f 15 01 00 00 00 00 02 dc 00 15 01 00 00 00 00 02 dd 0e 15 01 00 00 00 00 02 de 1f 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 04 15 01 00 00 00 00 02 e1 1f 15 01 00 00 00 00 02 e2 01 15 01 00 00 00 00 02 e3 02 15 01 00 00 00 00 02 e4 1f 15 01 00 00 00 00 02 e5 1f 15 01 00 00 00 00 02 e6 1f 15 01 00 00 00 00 02 e7 1f 15 01 00 00 00 00 02 e8 1f 15 01 00 00 00 00 02 e9 1f 15 01 00 00 00 00 02 ea 1f 15 01 00 00 00 00 02 eb 1f 15 01 00 00 00 00 02 ec 1f 15 01 00 00 00 00 02 ed 1f 15 01 00 00 00 00 02 ee 1f 15 01 00 00 00 00 02 ef 03 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 c6 15 15 01 00 00 00 00 02 c9 9e 15 01 00 00 00 00 02 cb 3f 15 01 00 00 00 00 02 d1 0f 15 01 00 00 00 00 02 d3 15 15 01 00 00 00 00 02 d4 15 15 01 00 00 00 00 02 d5 00 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 a9 40 15 01 00 00 00 00 02 cb 05 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 5a ff 15 01 00 00 00 00 02 5c ff 15 01 00 00 00 00 02 5d 0a 15 01 00 00 00 00 02 7d 31 15 01 00 00 00 00 02 7e 4a 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 49 05 15 01 00 00 00 00 02 4a 2e 15 01 00 00 00 00 02 4b 58 15 01 00 00 00 00 02 4c 77 15 01 00 00 00 00 02 4d a1 15 01 00 00 00 00 02 4e de 15 01 00 00 00 00 02 4f 2c 15 01 00 00 00 00 02 50 97 15 01 00 00 00 00 02 51 2a 15 01 00 00 00 00 02 ad ec 15 01 00 00 00 00 02 ae 80 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 50 15 01 00 00 00 00 02 b1 3a 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 56 91 15 01 00 00 00 00 02 58 04 15 01 00 00 00 00 02 59 24 15 01 00 00 00 00 02 5a 05 15 01 00 00 00 00 02 5b c6 15 01 00 00 00 00 02 5c 05 15 01 00 00 00 00 02 5d 66 15 01 00 00 00 00 02 5e 06 15 01 00 00 00 00 02 5f 17 15 01 00 00 00 00 02 60 07 15 01 00 00 00 00 02 61 cf 15 01 00 00 00 00 02 62 07 15 01 00 00 00 00 02 63 98 15 01 00 00 00 00 02 64 08 15 01 00 00 00 00 02 65 65 15 01 00 00 00 00 02 66 09 15 01 00 00 00 00 02 67 37 15 01 00 00 00 00 02 68 0a 15 01 00 00 00 00 02 6b 02 15 01 00 00 00 00 02 6c 0c 15 01 00 00 00 00 02 71 02 15 01 00 00 00 00 02 72 0f 15 01 00 00 00 00 02 73 93 15 01 00 00 00 00 02 74 0f 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 98 cf 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 b4 31 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 aa 03 15 01 00 00 00 00 02 09 13 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 01 41 15 01 00 00 00 00 02 02 00 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 04 ff 15 01 00 00 00 00 02 05 00 15 01 00 00 00 00 02 06 c0 15 01 00 00 00 00 02 07 40 15 01 00 00 00 00 02 08 20 15 01 00 00 00 00 02 19 e0 15 01 00 00 00 00 02 1a 40 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 80 15 01 00 00 00 00 02 60 40 15 01 00 00 00 00 02 61 40 15 01 00 00 00 00 02 62 40 15 01 00 00 00 00 02 63 40 15 01 00 00 00 00 02 64 40 15 01 00 00 00 00 02 65 40 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 02 15 01 00 00 00 00 02 75 10 15 01 00 00 00 00 02 76 14 15 01 00 00 00 00 02 77 1c 15 01 00 00 00 00 02 78 20 15 01 00 00 00 00 02 79 0a 15 01 00 00 00 00 02 7a 00 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c 00 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e 00 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 81 00 15 01 00 00 00 00 02 82 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 84 00 15 01 00 00 00 00 02 85 00 15 01 00 00 00 00 02 86 20 15 01 00 00 00 00 02 87 0a 15 01 00 00 00 00 02 88 02 15 01 00 00 00 00 02 89 2b 15 01 00 00 00 00 02 8a 14 15 01 00 00 00 00 02 8b 01 15 01 00 00 00 00 02 8c 00 15 01 00 00 00 00 02 8d 00 15 01 00 00 00 00 02 8e 00 15 01 00 00 00 00 02 8f 00 15 01 00 00 00 00 02 90 00 15 01 00 00 00 00 02 91 00 15 01 00 00 00 00 02 92 00 15 01 00 00 00 00 02 93 00 15 01 00 00 00 00 02 94 00 15 01 00 00 00 00 02 95 00 15 01 00 00 00 00 02 96 00 15 01 00 00 00 00 02 b2 40 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 b8 d0 15 01 00 00 00 00 02 b9 06 15 01 00 00 00 00 02 ba 00 15 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 05 51 00 00 ff ff 15 01 00 00 00 00 02 c2 09 05 01 00 00 96 00 01 11 05 01 00 00 32 00 01 29];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1f0808 0x24220808 0x5020400>;
|
|
qcom,display-topology = <0x01 0x00 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_rm69298_truly_amoled_cmd {
|
|
qcom,mdss-dsi-panel-name = "rm69298 amoled fhd+ cmd mode dsi truly panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-lp11-init;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,mdss-dsi-t-clk-post = <0x0d>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x30>;
|
|
qcom,panel-supply-entries = <0x4cb>;
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0xff>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
qcom,platform-reset-gpio = <0x2e4 0x09 0x00>;
|
|
phandle = <0x4d8>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0x870>;
|
|
qcom,mdss-dsi-h-front-porch = <0x1e>;
|
|
qcom,mdss-dsi-h-back-porch = <0x28>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x0a>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x10>;
|
|
qcom,mdss-dsi-v-front-porch = <0x08>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 fe 40 15 01 00 00 00 00 02 0a 15 15 01 00 00 00 00 02 0b cc 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 80 15 01 00 00 00 00 02 0f 87 15 01 00 00 00 00 02 05 08 15 01 00 00 00 00 02 06 08 15 01 00 00 00 00 02 08 08 15 01 00 00 00 00 02 09 08 15 01 00 00 00 00 02 16 15 15 01 00 00 00 00 02 20 8d 15 01 00 00 00 00 02 21 8d 15 01 00 00 00 00 02 24 55 15 01 00 00 00 00 02 26 55 15 01 00 00 00 00 02 28 55 15 01 00 00 00 00 02 2a 55 15 01 00 00 00 00 02 2d 28 15 01 00 00 00 00 02 2f 28 15 01 00 00 00 00 02 30 1e 15 01 00 00 00 00 02 31 1e 15 01 00 00 00 00 02 37 80 15 01 00 00 00 00 02 38 40 15 01 00 00 00 00 02 39 90 15 01 00 00 00 00 02 46 43 15 01 00 00 00 00 02 47 43 15 01 00 00 00 00 02 64 02 15 01 00 00 00 00 02 6f 02 15 01 00 00 00 00 02 74 2f 15 01 00 00 00 00 02 80 16 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 fe a0 15 01 00 00 00 00 02 2b 22 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 2f 35 15 01 00 00 00 00 02 fe 60 15 01 00 00 00 00 02 00 ac 15 01 00 00 00 00 02 01 0f 15 01 00 00 00 00 02 02 ff 15 01 00 00 00 00 02 03 05 15 01 00 00 00 00 02 04 00 15 01 00 00 00 00 02 05 06 15 01 00 00 00 00 02 06 00 15 01 00 00 00 00 02 07 00 15 01 00 00 00 00 02 09 c0 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 02 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0e 00 15 01 00 00 00 00 02 0e 04 15 01 00 00 00 00 02 0f 0e 15 01 00 00 00 00 02 10 a2 15 01 00 00 00 00 02 12 c0 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 14 02 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 16 00 15 01 00 00 00 00 02 17 05 15 01 00 00 00 00 02 18 0e 15 01 00 00 00 00 02 19 a2 15 01 00 00 00 00 02 1b c0 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 04 15 01 00 00 00 00 02 1e 01 15 01 00 00 00 00 02 1f 00 15 01 00 00 00 00 02 20 04 15 01 00 00 00 00 02 21 24 15 01 00 00 00 00 02 22 99 15 01 00 00 00 00 02 24 c0 15 01 00 00 00 00 02 25 00 15 01 00 00 00 00 02 26 04 15 01 00 00 00 00 02 27 01 15 01 00 00 00 00 02 28 00 15 01 00 00 00 00 02 29 06 15 01 00 00 00 00 02 2a 24 15 01 00 00 00 00 02 2b 99 15 01 00 00 00 00 02 83 ca 15 01 00 00 00 00 02 84 0f 15 01 00 00 00 00 02 85 ff 15 01 00 00 00 00 02 86 0a 15 01 00 00 00 00 02 87 00 15 01 00 00 00 00 02 88 08 15 01 00 00 00 00 02 89 00 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 8b 80 15 01 00 00 00 00 02 c7 1f 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 c9 01 15 01 00 00 00 00 02 ca 1f 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 1f 15 01 00 00 00 00 02 cd 1f 15 01 00 00 00 00 02 ce 1f 15 01 00 00 00 00 02 cf 1f 15 01 00 00 00 00 02 d0 1f 15 01 00 00 00 00 02 d1 1f 15 01 00 00 00 00 02 d2 1f 15 01 00 00 00 00 02 d3 1f 15 01 00 00 00 00 02 d4 1f 15 01 00 00 00 00 02 d5 1f 15 01 00 00 00 00 02 d6 1f 15 01 00 00 00 00 02 d7 1f 15 01 00 00 00 00 02 d8 1f 15 01 00 00 00 00 02 d9 1f 15 01 00 00 00 00 02 da 1f 15 01 00 00 00 00 02 db 1f 15 01 00 00 00 00 02 dc 00 15 01 00 00 00 00 02 dd 0e 15 01 00 00 00 00 02 de 1f 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 04 15 01 00 00 00 00 02 e1 1f 15 01 00 00 00 00 02 e2 01 15 01 00 00 00 00 02 e3 02 15 01 00 00 00 00 02 e4 1f 15 01 00 00 00 00 02 e5 1f 15 01 00 00 00 00 02 e6 1f 15 01 00 00 00 00 02 e7 1f 15 01 00 00 00 00 02 e8 1f 15 01 00 00 00 00 02 e9 1f 15 01 00 00 00 00 02 ea 1f 15 01 00 00 00 00 02 eb 1f 15 01 00 00 00 00 02 ec 1f 15 01 00 00 00 00 02 ed 1f 15 01 00 00 00 00 02 ee 1f 15 01 00 00 00 00 02 ef 03 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 c6 15 15 01 00 00 00 00 02 c9 9e 15 01 00 00 00 00 02 cb 3f 15 01 00 00 00 00 02 d1 0f 15 01 00 00 00 00 02 d3 15 15 01 00 00 00 00 02 d4 15 15 01 00 00 00 00 02 d5 00 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 fe e0 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 a9 40 15 01 00 00 00 00 02 cb 05 15 01 00 00 00 00 02 fe 70 15 01 00 00 00 00 02 5a ff 15 01 00 00 00 00 02 5c ff 15 01 00 00 00 00 02 5d 0a 15 01 00 00 00 00 02 7d 31 15 01 00 00 00 00 02 7e 4a 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 49 05 15 01 00 00 00 00 02 4a 2e 15 01 00 00 00 00 02 4b 58 15 01 00 00 00 00 02 4c 77 15 01 00 00 00 00 02 4d a1 15 01 00 00 00 00 02 4e de 15 01 00 00 00 00 02 4f 2c 15 01 00 00 00 00 02 50 97 15 01 00 00 00 00 02 51 2a 15 01 00 00 00 00 02 ad ec 15 01 00 00 00 00 02 ae 80 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 50 15 01 00 00 00 00 02 b1 3a 15 01 00 00 00 00 02 fe 90 15 01 00 00 00 00 02 56 91 15 01 00 00 00 00 02 58 04 15 01 00 00 00 00 02 59 24 15 01 00 00 00 00 02 5a 05 15 01 00 00 00 00 02 5b c6 15 01 00 00 00 00 02 5c 05 15 01 00 00 00 00 02 5d 66 15 01 00 00 00 00 02 5e 06 15 01 00 00 00 00 02 5f 17 15 01 00 00 00 00 02 60 07 15 01 00 00 00 00 02 61 cf 15 01 00 00 00 00 02 62 07 15 01 00 00 00 00 02 63 98 15 01 00 00 00 00 02 64 08 15 01 00 00 00 00 02 65 65 15 01 00 00 00 00 02 66 09 15 01 00 00 00 00 02 67 37 15 01 00 00 00 00 02 68 0a 15 01 00 00 00 00 02 6b 02 15 01 00 00 00 00 02 6c 0c 15 01 00 00 00 00 02 71 02 15 01 00 00 00 00 02 72 0f 15 01 00 00 00 00 02 73 93 15 01 00 00 00 00 02 74 0f 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 98 cf 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 b4 31 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 aa 03 15 01 00 00 00 00 02 09 13 15 01 00 00 00 00 02 fe 20 15 01 00 00 00 00 02 01 41 15 01 00 00 00 00 02 02 00 15 01 00 00 00 00 02 03 00 15 01 00 00 00 00 02 04 ff 15 01 00 00 00 00 02 05 00 15 01 00 00 00 00 02 06 c0 15 01 00 00 00 00 02 07 40 15 01 00 00 00 00 02 08 20 15 01 00 00 00 00 02 19 e0 15 01 00 00 00 00 02 1a 40 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 80 15 01 00 00 00 00 02 60 40 15 01 00 00 00 00 02 61 40 15 01 00 00 00 00 02 62 40 15 01 00 00 00 00 02 63 40 15 01 00 00 00 00 02 64 40 15 01 00 00 00 00 02 65 40 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 02 15 01 00 00 00 00 02 75 10 15 01 00 00 00 00 02 76 14 15 01 00 00 00 00 02 77 1c 15 01 00 00 00 00 02 78 20 15 01 00 00 00 00 02 79 0a 15 01 00 00 00 00 02 7a 00 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c 00 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e 00 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 81 00 15 01 00 00 00 00 02 82 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 84 00 15 01 00 00 00 00 02 85 00 15 01 00 00 00 00 02 86 20 15 01 00 00 00 00 02 87 0a 15 01 00 00 00 00 02 88 02 15 01 00 00 00 00 02 89 2b 15 01 00 00 00 00 02 8a 14 15 01 00 00 00 00 02 8b 01 15 01 00 00 00 00 02 8c 00 15 01 00 00 00 00 02 8d 00 15 01 00 00 00 00 02 8e 00 15 01 00 00 00 00 02 8f 00 15 01 00 00 00 00 02 90 00 15 01 00 00 00 00 02 91 00 15 01 00 00 00 00 02 92 00 15 01 00 00 00 00 02 93 00 15 01 00 00 00 00 02 94 00 15 01 00 00 00 00 02 95 00 15 01 00 00 00 00 02 96 00 15 01 00 00 00 00 02 b2 40 15 01 00 00 00 00 02 b7 42 15 01 00 00 00 00 02 b8 d0 15 01 00 00 00 00 02 b9 06 15 01 00 00 00 00 02 ba 00 15 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 05 51 00 00 ff ff 15 01 00 00 00 00 02 c2 08 15 01 00 00 00 00 02 35 00 05 01 00 00 96 00 01 11 05 01 00 00 32 00 01 29];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1f0808 0x24220808 0x5020400>;
|
|
qcom,display-topology = <0x01 0x00 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_rm69299_visionox_amoled_video {
|
|
qcom,mdss-dsi-panel-name = "rm69299 amoled fhd+ video mode dsi visionox panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
|
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-lp11-init;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,mdss-dsi-t-clk-post = <0x0e>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x31>;
|
|
qcom,panel-supply-entries = <0x4cb>;
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0xff>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
qcom,platform-reset-gpio = <0x2e4 0x09 0x00>;
|
|
phandle = <0x4db>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0x8c8>;
|
|
qcom,mdss-dsi-h-front-porch = <0x1a>;
|
|
qcom,mdss-dsi-h-back-porch = <0x24>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x04>;
|
|
qcom,mdss-dsi-v-front-porch = <0x38>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 c2 08 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 51 ff 05 01 00 00 96 00 02 11 00 05 01 00 00 32 00 02 29 00];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x200808 0x24230808 0x5020400>;
|
|
qcom,display-topology = <0x01 0x00 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_nt35695b_truly_fhd_video {
|
|
qcom,mdss-dsi-panel-name = "nt35695b truly fhd video mode dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,mdss-dsi-post-init-delay = <0x01>;
|
|
qcom,esd-check-enabled;
|
|
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
|
qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;
|
|
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-status-read-length = <0x01>;
|
|
qcom,dsi-supported-dfps-list = <0x3c 0x37 0x30>;
|
|
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
|
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
|
qcom,mdss-dsi-t-clk-post = <0x07>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x1c>;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,panel-sec-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,platform-reset-gpio = <0x2e4 0x0b 0x00>;
|
|
qcom,platform-sec-reset-gpio = <0x2e4 0x0b 0x00>;
|
|
qcom,platform-en-gpio = <0x2e4 0x04 0x00>;
|
|
qcom,platform-bklight-en-gpio = <0x2e4 0x05 0x00>;
|
|
phandle = <0x4d9>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-h-front-porch = <0x78>;
|
|
qcom,mdss-dsi-h-back-porch = <0x3c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x0c>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x02>;
|
|
qcom,mdss-dsi-v-front-porch = <0x0c>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 03 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x130504 0x1f1e0505 0x3020400>;
|
|
qcom,display-topology = <0x01 0x00 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_nt35695b_truly_fhd_cmd {
|
|
qcom,mdss-dsi-panel-name = "nt35695b truly fhd command mode dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,mdss-dsi-post-init-delay = <0x01>;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,ulps-enabled;
|
|
qcom,esd-check-enabled;
|
|
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
|
qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>;
|
|
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-on-check-value = <0x9c>;
|
|
qcom,mdss-dsi-panel-status-read-length = <0x01>;
|
|
qcom,mdss-dsi-t-clk-post = <0x07>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x1c>;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,panel-sec-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,platform-reset-gpio = <0x2e4 0x0b 0x00>;
|
|
qcom,platform-sec-reset-gpio = <0x2e4 0x0b 0x00>;
|
|
qcom,platform-en-gpio = <0x2e4 0x04 0x00>;
|
|
qcom,platform-bklight-en-gpio = <0x2e4 0x05 0x00>;
|
|
qcom,platform-te-gpio = <0x16c 0x0b 0x00>;
|
|
phandle = <0x4da>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-h-front-porch = <0x78>;
|
|
qcom,mdss-dsi-h-back-porch = <0x3c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x0c>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x02>;
|
|
qcom,mdss-dsi-v-front-porch = <0x0c>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-h-sync-pulse = <0x00>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-panel-phy-timings = <0x130504 0x1f1e0505 0x3020400>;
|
|
qcom,display-topology = <0x01 0x00 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sharp_qsync_wqhd_cmd {
|
|
qcom,mdss-dsi-panel-name = "Sharp 2k cmd mode qsync dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-pan-physical-width-dimension = <0x4a>;
|
|
qcom,mdss-pan-physical-height-dimension = <0x86>;
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,adjust-timer-wakeup-ms = <0x01>;
|
|
qcom,mdss-dsi-panel-hdr-enabled;
|
|
qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>;
|
|
qcom,mdss-dsi-panel-peak-brightness = <0x626b50>;
|
|
qcom,mdss-dsi-panel-blackness-level = <0x1361>;
|
|
qcom,mdss-dsi-t-clk-post = <0x0b>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x24>;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
qcom,platform-reset-gpio = <0x2e4 0x09 0x00>;
|
|
qcom,platform-en-gpio = <0x2e4 0x04 0x00>;
|
|
qcom,platform-bklight-en-gpio = <0x2e4 0x05 0x00>;
|
|
phandle = <0x4dc>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x2d0>;
|
|
qcom,mdss-dsi-panel-height = <0xa00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x14>;
|
|
qcom,mdss-dsi-h-back-porch = <0x0c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x08>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0e>;
|
|
qcom,mdss-dsi-v-front-porch = <0x10>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-jitter = <0x03 0x01>;
|
|
qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01];
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x08>;
|
|
qcom,mdss-dsc-slice-width = <0x2d0>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0xb0302 0x1d1c0303 0x1020400>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
|
|
timing@1 {
|
|
qcom,mdss-dsi-panel-width = <0x21c>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-h-front-porch = <0x14>;
|
|
qcom,mdss-dsi-h-back-porch = <0x0c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x08>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0e>;
|
|
qcom,mdss-dsi-v-front-porch = <0x10>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-jitter = <0x03 0x01>;
|
|
qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01];
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x08>;
|
|
qcom,mdss-dsc-slice-width = <0x21c>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0xa0102 0x1b1b0202 0x20400>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
|
|
timing@2 {
|
|
qcom,mdss-dsi-panel-width = <0x2d0>;
|
|
qcom,mdss-dsi-panel-height = <0xa00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x14>;
|
|
qcom,mdss-dsi-h-back-porch = <0x0c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x08>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0e>;
|
|
qcom,mdss-dsi-v-front-porch = <0x10>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-panel-framerate = <0x5a>;
|
|
qcom,mdss-dsi-panel-jitter = <0x03 0x01>;
|
|
qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 02];
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x08>;
|
|
qcom,mdss-dsc-slice-width = <0x2d0>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x110404 0x1e1e0404 0x2020400>;
|
|
qcom,mdss-mdp-transfer-time-us = <0x2134>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
|
|
timing@3 {
|
|
qcom,mdss-dsi-panel-width = <0x2d0>;
|
|
qcom,mdss-dsi-panel-height = <0xa00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x14>;
|
|
qcom,mdss-dsi-h-back-porch = <0x0c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x08>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0e>;
|
|
qcom,mdss-dsi-v-front-porch = <0x10>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-panel-framerate = <0x78>;
|
|
qcom,mdss-dsi-panel-jitter = <0x03 0x01>;
|
|
qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 03];
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x08>;
|
|
qcom,mdss-dsc-slice-width = <0x2d0>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x160605 0x201f0606 0x3020400>;
|
|
qcom,mdss-mdp-transfer-time-us = <0x16a8>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sharp_qsync_wqhd_video {
|
|
qcom,mdss-dsi-panel-name = "Sharp 2k video mode qsync dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
|
qcom,dsi-ctrl-num = <0x00 0x01>;
|
|
qcom,dsi-phy-num = <0x00 0x01>;
|
|
qcom,dsi-select-clocks = "src_byte_clk0\0src_pixel_clk0";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-pan-physical-width-dimension = <0x4a>;
|
|
qcom,mdss-pan-physical-height-dimension = <0x86>;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,adjust-timer-wakeup-ms = <0x01>;
|
|
qcom,mdss-dsi-panel-hdr-enabled;
|
|
qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>;
|
|
qcom,mdss-dsi-panel-peak-brightness = <0x626b50>;
|
|
qcom,mdss-dsi-panel-blackness-level = <0x1361>;
|
|
qcom,mdss-dsi-t-clk-post = <0x0a>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x1e>;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,platform-reset-gpio = <0x2e4 0x09 0x00>;
|
|
qcom,platform-en-gpio = <0x2e4 0x04 0x00>;
|
|
qcom,platform-bklight-en-gpio = <0x2e4 0x05 0x00>;
|
|
phandle = <0x4dd>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x2d0>;
|
|
qcom,mdss-dsi-panel-height = <0xa00>;
|
|
qcom,mdss-dsi-h-front-porch = <0x14>;
|
|
qcom,mdss-dsi-h-back-porch = <0x0c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x08>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0e>;
|
|
qcom,mdss-dsi-v-front-porch = <0x7d8>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = <0x39010000 0x2ff 0xd0390100 0x02 0x75403901 0x1000 0x2f14039 0x1000000 0x2ff10 0x39010000 0x1000062c 0x1020408 0x10390100 0x02 0xffd03901 0x00 0x2750039 0x1000010 0x2f100 0x39010000 0x2ff 0x10390100 0x02 0xfb013901 0x00 0x2ba0339 0x1000000 0x2bc08 0x39010000 0x2c0 0x83390100 0x11 0xc1892800 0x8020002 0x6800d500 0xa0db709 0x89390100 0x03 0xc210f039 0x1000000 0x2d500 0x39010000 0x2d6 0x390100 0x02 0xde003901 0x00 0x2e10039 0x1000000 0x2e501 0x39010000 0x2bb 0x3390100 0x02 0xf6703901 0x00 0x2f78039 0x1000000 0x5be00 0x10001039 0x1000000 0x23500 0x39010000 0x244 0x390100 0x02 0xff203901 0x00 0x2fb0139 0x1000000 0x28702 0x39010000 0x25d 0x390100 0x02 0x5e143901 0x00 0x25feb39 0x1000000 0x2ff26 0x39010000 0x2fb 0x1390100 0x02 0x60003901 0x00 0x2620139 0x1000000 0x24000 0x39010000 0x2ff 0x28390100 0x02 0xfb013901 0x00 0x2910239 0x1000000 0x2ffe0 0x39010000 0x2fb 0x1390100 0x02 0x48813901 0x00 0x28e0939 0x1000000 0x2fff0 0x39010000 0x2fb 0x1390100 0x02 0x33203901 0x00 0x2343539 0x1000000 0x2ff10 0x5010000 0x78000111 0x5010000 0x78000129>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x08>;
|
|
qcom,mdss-dsc-slice-width = <0x2d0>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x120404 0x1e1e0404 0x2020400>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sharp_qsync_fhd_video {
|
|
qcom,mdss-dsi-panel-name = "Sharp fhd video mode qsync dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-pan-physical-width-dimension = <0x4a>;
|
|
qcom,mdss-pan-physical-height-dimension = <0x86>;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,adjust-timer-wakeup-ms = <0x01>;
|
|
qcom,mdss-dsi-panel-hdr-enabled;
|
|
qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>;
|
|
qcom,mdss-dsi-panel-peak-brightness = <0x626b50>;
|
|
qcom,mdss-dsi-panel-blackness-level = <0x1361>;
|
|
qcom,mdss-dsi-t-clk-post = <0x0a>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x20>;
|
|
qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>;
|
|
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
|
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
|
qcom,mdss-dsi-min-refresh-rate = <0x3c>;
|
|
qcom,mdss-dsi-max-refresh-rate = <0x78>;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,platform-reset-gpio = <0x2e4 0x09 0x00>;
|
|
qcom,platform-en-gpio = <0x2e4 0x04 0x00>;
|
|
qcom,platform-bklight-en-gpio = <0x2e4 0x05 0x00>;
|
|
phandle = <0x4de>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x21c>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-h-front-porch = <0x7c>;
|
|
qcom,mdss-dsi-h-back-porch = <0x14>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x14>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0e>;
|
|
qcom,mdss-dsi-v-front-porch = <0x7b0>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-on-command = <0x39010000 0x2ff 0xd0390100 0x02 0x75403901 0x1000 0x2f14039 0x1000000 0x2ff10 0x39010000 0x1000062c 0x1020408 0x10390100 0x02 0xffd03901 0x00 0x2750039 0x1000010 0x2f100 0x39010000 0x2ff 0x10390100 0x02 0xfb013901 0x00 0x2ba0339 0x1000000 0x2bc08 0x39010000 0x2c0 0x85390100 0x11 0xc1892800 0x8020002 0xe00bb00 0x70db70c 0xb7390100 0x03 0xc210f039 0x1000000 0x2d500 0x39010000 0x2d6 0x390100 0x02 0xde003901 0x00 0x2e10039 0x1000000 0x2e501 0x39010000 0x2bb 0x3390100 0x02 0xf6703901 0x00 0x2f78039 0x1000000 0x5be00 0x10001039 0x1000000 0x23500 0x39010000 0x244 0x390100 0x02 0xff203901 0x00 0x2fb0139 0x1000000 0x28702 0x39010000 0x25d 0x390100 0x02 0x5e143901 0x00 0x25feb39 0x1000000 0x2ff26 0x39010000 0x2fb 0x1390100 0x02 0x60003901 0x00 0x2620139 0x1000000 0x24000 0x39010000 0x2ff 0x28390100 0x02 0xfb013901 0x00 0x2910239 0x1000000 0x2ffe0 0x39010000 0x2fb 0x1390100 0x02 0x48813901 0x00 0x28e0939 0x1000000 0x2fff0 0x39010000 0x2fb 0x1390100 0x02 0x33203901 0x00 0x2343539 0x1000000 0x2ff10 0x5010000 0x78000111 0x5010000 0x78000129>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x08>;
|
|
qcom,mdss-dsc-slice-width = <0x21c>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x130404 0x1f1f0405 0x3020400>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_sharp_qsync_fhd_cmd {
|
|
qcom,mdss-dsi-panel-name = "Sharp fhd cmd mode qsync dsi panel";
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-pan-physical-width-dimension = <0x4a>;
|
|
qcom,mdss-pan-physical-height-dimension = <0x86>;
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-te-check-enable;
|
|
qcom,mdss-dsi-te-using-te-pin;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
qcom,adjust-timer-wakeup-ms = <0x01>;
|
|
qcom,mdss-dsi-panel-hdr-enabled;
|
|
qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>;
|
|
qcom,mdss-dsi-panel-peak-brightness = <0x626b50>;
|
|
qcom,mdss-dsi-panel-blackness-level = <0x1361>;
|
|
qcom,mdss-dsi-t-clk-post = <0x09>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x12>;
|
|
qcom,panel-supply-entries = <0x4ca>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0xfff>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
qcom,platform-reset-gpio = <0x2e4 0x09 0x00>;
|
|
qcom,platform-en-gpio = <0x2e4 0x04 0x00>;
|
|
qcom,platform-bklight-en-gpio = <0x2e4 0x05 0x00>;
|
|
phandle = <0x4df>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
timing@0 {
|
|
qcom,mdss-dsi-panel-width = <0x21c>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-h-front-porch = <0x14>;
|
|
qcom,mdss-dsi-h-back-porch = <0x0c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x08>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0e>;
|
|
qcom,mdss-dsi-v-front-porch = <0x10>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-jitter = <0x03 0x01>;
|
|
qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01];
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x08>;
|
|
qcom,mdss-dsc-slice-width = <0x21c>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0xa0102 0x1b1b0202 0x20400>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
|
|
timing@1 {
|
|
qcom,mdss-dsi-panel-width = <0x21c>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-h-front-porch = <0x14>;
|
|
qcom,mdss-dsi-h-back-porch = <0x0c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x08>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0e>;
|
|
qcom,mdss-dsi-v-front-porch = <0x10>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-panel-framerate = <0x5a>;
|
|
qcom,mdss-dsi-panel-jitter = <0x03 0x01>;
|
|
qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 02];
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x08>;
|
|
qcom,mdss-dsc-slice-width = <0x21c>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0xc0202 0x1d1c0303 0x1020400>;
|
|
qcom,mdss-mdp-transfer-time-us = <0x2134>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
|
|
timing@2 {
|
|
qcom,mdss-dsi-panel-width = <0x21c>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-h-front-porch = <0x14>;
|
|
qcom,mdss-dsi-h-back-porch = <0x0c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x08>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-back-porch = <0x0e>;
|
|
qcom,mdss-dsi-v-front-porch = <0x10>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-panel-framerate = <0x78>;
|
|
qcom,mdss-dsi-panel-jitter = <0x03 0x01>;
|
|
qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 03];
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29];
|
|
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
|
qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10];
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
qcom,compression-mode = "dsc";
|
|
qcom,mdss-dsc-slice-height = <0x08>;
|
|
qcom,mdss-dsc-slice-width = <0x21c>;
|
|
qcom,mdss-dsc-slice-per-pkt = <0x01>;
|
|
qcom,mdss-dsc-bit-per-component = <0x08>;
|
|
qcom,mdss-dsc-bit-per-pixel = <0x08>;
|
|
qcom,mdss-dsc-block-prediction-enable;
|
|
qcom,mdss-dsi-panel-phy-timings = <0xf0303 0x1e1d0404 0x2020400>;
|
|
qcom,mdss-mdp-transfer-time-us = <0x16a8>;
|
|
qcom,display-topology = <0x02 0x02 0x02>;
|
|
qcom,default-topology-index = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ss_dsi_panel_S6E3FA9_AMB667UM06_FHD {
|
|
qcom,mdss-dsi-panel-name = "ss_dsi_panel_S6E3FA9_AMB667UM06_FHD";
|
|
label = "ss_dsi_panel_S6E3FA9_AMB667UM06_FHD";
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x79>;
|
|
qcom,mdss-dsi-h-back-porch = <0x7a>;
|
|
qcom,mdss-dsi-h-front-porch = <0x78>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-v-back-porch = <0x10>;
|
|
qcom,mdss-dsi-v-front-porch = <0xf8>;
|
|
qcom,mdss-dsi-h-left-border = <0x00>;
|
|
qcom,mdss-dsi-h-right-border = <0x00>;
|
|
qcom,mdss-dsi-v-top-border = <0x00>;
|
|
qcom,mdss-dsi-v-bottom-border = <0x00>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-clockrate = <0x47868c00>;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x270a0a 0x27250a0b 0x7020400>;
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-bl-min-level = <0x01>;
|
|
qcom,mdss-dsi-bl-max-level = <0x1a9>;
|
|
qcom,mdss-brightness-max-level = <0x1a9>;
|
|
qcom,mdss-brightness-default-level = <0xff>;
|
|
qcom,mdss-dsi-interleave-mode = <0x00>;
|
|
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
|
qcom,mdss-dsi-te-pin-select = <0x01>;
|
|
qcom,mdss-dsi-te-dcs-command = <0x01>;
|
|
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
|
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
|
qcom,mdss-dsi-pixel-packing = "loose";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
|
qcom,mdss-dsi-t-clk-pre = <0x3b>;
|
|
qcom,mdss-dsi-t-clk-post = <0x0f>;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-pan-physical-width-dimension = <0x46>;
|
|
qcom,mdss-pan-physical-height-dimension = <0x9b>;
|
|
samsung,mdss-dsi-off-reset-delay-us = <0x3e8>;
|
|
qcom,mdss-dsi-reset-sequence = <0x00 0x0a 0x01 0x0a>;
|
|
qcom,mdss-dsi-rx-eot-ignore;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
samsung,panel-vendor = "SDC";
|
|
samsung,disp-model = "AMB667UM06";
|
|
samsung,panel-lpm-enable;
|
|
samsung,support_factory_panel_swap;
|
|
samsung,support_dynamic_mipi_clk;
|
|
samsung,support_poc_driver;
|
|
samsung,poc_image_size = <0x4fe4e>;
|
|
samsung,poc_enable_tx_cmds_revA = <0x29000000 0x3f0 0x5a5a2901 0x00 0x3f1f1a2>;
|
|
samsung,poc_disable_tx_cmds_revA = <0x29000000 0x3f0 0xa5a52901 0x00 0x3f1a5a5>;
|
|
samsung,poc_erase_delay_us = <0x61a80>;
|
|
samsung,poc_erase_sector_addr_idx = <0x04 0x05 0x06>;
|
|
samsung,poc_pre_erase_sector_tx_cmds_revA = <0x29000000 0x3f0 0x5a5a2901 0x00 0x3f1f1a2 0x29000000 0x2c0 0x2290100 0x10004 0x71030000 0x29000000 0xac1 0x600 0x00 0x290100 0x10002 0xc0032900 0x00 0xac10000 0x1000200 0x80000029 0x100000a 0x2c003>;
|
|
samsung,poc_erase_sector_tx_cmds_revA = <0x29010000 0xac1 0x600 0x00 0x290100 0x10002 0xc0032901 0x00 0xac10000 0x20000000 0xc0000029 0x1000000 0x2c003>;
|
|
samsung,poc_post_erase_sector_tx_cmds_revA = [29 01 00 00 00 00 02 c0 00 29 00 00 00 00 00 03 f0 a5 a5 29 01 00 00 00 00 03 f1 a5 a5];
|
|
samsung,poc_write_delay_us = <0x3e8>;
|
|
samsung,poc_write_loop_cnt = <0x100>;
|
|
samsung,poc_write_data_size = <0x100>;
|
|
samsung,poc_write_addr_idx = <0x04 0x05 0x06>;
|
|
samsung,poc_pre_write_tx_cmds_revA = <0x29000000 0x2c0 0x2290100 0x10004 0x71030000 0x29000000 0xac1 0x600 0x00 0x290100 0x10002 0xc0032900 0x00 0xac10000 0x1000200 0x80000029 0x100000a 0x2c003>;
|
|
samsung,poc_write_loop_start_tx_cmds_revA = [29 01 00 00 00 00 0a c1 00 00 06 00 00 00 00 00 00 29 01 00 00 01 00 02 c0 03];
|
|
samsung,poc_write_loop_data_add_tx_cmds_revA = [29 01 00 00 00 00 0a c1 00 00 32 00 00 00 c2 00 00 29 01 00 00 04 00 02 c0 03];
|
|
samsung,poc_write_loop_256byte_tx_cmds_revA = <0x29010000 0x3b0 0x6c2901 0x00 0x816c0000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x2901 0x00 0x3b0806c 0x29010000 0x816c 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
samsung,poc_post_write_tx_cmds_revA = [29 00 00 00 00 00 02 c0 00];
|
|
samsung,poc_read_delay_us = <0x46>;
|
|
samsung,poc_read_addr_idx = <0x04 0x05 0x06>;
|
|
samsung,poc_pre_read_tx_cmds_revA = <0x29000000 0x3f0 0x5a5a2901 0x00 0x3f1f1a2 0x29000000 0x2c0 0x2290000 0x10004 0x71030000 0x29010000 0xac1 0x600 0x00 0x290000 0x10002 0xc0032900 0x00 0xac10000 0x1000200 0x80000029 0x100000a 0x2c003>;
|
|
samsung,poc_read_tx_cmds_revA = [29 01 00 00 00 00 0a c1 00 00 6b 00 00 00 c0 00 80 29 01 00 00 0a 00 02 c0 03];
|
|
samsung,poc_read_rx_cmds_revA = [06 01 00 00 00 00 01 6e 80 00];
|
|
samsung,poc_post_read_tx_cmds_revA = [29 01 00 00 00 00 02 c0 00 29 00 00 00 00 00 03 f0 a5 a5 29 01 00 00 00 00 03 f1 a5 a5];
|
|
samsung,poc_mca_check_rx_cmds_revA = [06 01 00 00 00 00 01 91 5e 00];
|
|
samsung,level0_key_enable_tx_cmds_revA = [29 01 00 00 00 00 03 9f a5 a5];
|
|
samsung,level0_key_disable_tx_cmds_revA = [29 01 00 00 00 00 03 9f 5a 5a];
|
|
samsung,level1_key_enable_tx_cmds_revA = [29 01 00 00 00 00 03 f0 5a 5a];
|
|
samsung,level1_key_disable_tx_cmds_revA = [29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,level2_key_enable_tx_cmds_revA = [29 01 00 00 00 00 03 fc 5a 5a];
|
|
samsung,level2_key_disable_tx_cmds_revA = [29 01 00 00 00 00 03 fc a5 a5];
|
|
samsung,brightness_tx_cmds_revA = <0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100 0x39010000 0x100>;
|
|
samsung,display_on_tx_cmds_revA = [05 01 00 00 00 00 02 29 00];
|
|
samsung,display_off_tx_cmds_revA = [05 01 00 00 00 00 02 28 00];
|
|
samsung,mdnie_read_rx_cmds_revA = [06 01 00 00 00 00 01 a1 04 00];
|
|
samsung,manufacture_date_rx_cmds_revA = [06 01 00 00 00 00 01 a1 04 04];
|
|
samsung,octa_id_rx_cmds_revA = [06 01 00 00 00 00 01 a1 14 0b];
|
|
samsung,cell_id_rx_cmds_revA = [06 01 00 00 00 00 01 a1 07 04];
|
|
samsung,ddi_id_rx_cmds_revA = [06 01 00 00 00 00 01 d6 05 00];
|
|
samsung,manufacture_id0_rx_cmds_revA = [06 01 00 00 00 00 01 da 01 00];
|
|
samsung,manufacture_id1_rx_cmds_revA = [06 01 00 00 00 00 01 db 01 00];
|
|
samsung,manufacture_id2_rx_cmds_revA = [06 01 00 00 00 00 01 dc 01 00];
|
|
samsung,mtp_read_sysfs_rx_cmds_revA = [06 01 00 00 00 00 01 00 00 00];
|
|
samsung,mask_crc_pass_data = [0f 09];
|
|
samsung,self_mask_check_rx_cmds = [06 01 00 00 00 00 01 fb 02 0f];
|
|
samsung,support_gamma_mode2;
|
|
samsung,support_self_display;
|
|
ss,self_display = <0x589>;
|
|
samsung,vint_tx_cmds_revA = [29 01 00 00 00 00 02 f4 cc];
|
|
samsung,mcd_on_tx_cmds_revA = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 02 f4 ce 29 01 00 00 00 00 2b cb 00 00 42 0f 00 02 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 40 47 00 4d 00 00 00 20 07 28 38 51 00 00 00 00 00 f0 f0 0b 46 29 01 00 00 00 00 03 b0 05 f6 29 01 00 00 00 00 02 f6 00 29 01 00 00 00 00 03 b0 04 cc 29 01 00 00 00 00 02 cc 12 29 01 00 00 64 00 02 f7 03 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,mcd_off_tx_cmds_revA = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 02 f4 cc 29 01 00 00 00 00 2b cb 00 00 42 0b 00 06 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 40 47 00 4d 00 00 00 20 07 28 38 51 00 00 00 00 00 f0 f0 00 00 29 01 00 00 00 00 03 b0 05 f6 29 01 00 00 00 00 02 f6 90 29 01 00 00 00 00 03 b0 04 cc 29 01 00 00 00 00 02 cc 00 29 01 00 00 64 00 02 f7 03 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,gray_spot_test_on_tx_cmds_revA = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 b0 05 f6 29 01 00 00 00 00 02 f6 00 29 01 00 00 00 00 03 b0 07 f2 29 01 00 00 00 00 06 f2 02 00 58 38 d0 29 01 00 00 00 00 03 b0 11 f4 29 01 00 00 00 00 02 f4 1e 29 01 00 00 00 00 05 b5 19 8d 35 00 29 01 00 00 64 00 02 f7 03 29 01 00 00 00 00 03 f0 a5 a5];
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samsung,gray_spot_test_off_tx_cmds_revA = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 b0 05 f6 29 01 00 00 00 00 02 f6 90 29 01 00 00 00 00 03 b0 07 f2 29 01 00 00 00 00 06 f2 02 0e 58 38 50 29 01 00 00 00 00 03 b0 11 f4 29 01 00 00 00 00 02 f4 1e 29 01 00 00 00 00 05 b5 19 8d 35 00 29 01 00 00 64 00 02 f7 03 29 01 00 00 00 00 03 f0 a5 a5];
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samsung,micro_short_test_on_tx_cmds_revA = [29 00 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 b0 03 f6 29 01 00 00 00 00 04 f6 3b 00 78 29 00 00 00 00 00 03 bf 33 25 29 01 00 00 00 00 03 f0 a5 a5];
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samsung,micro_short_test_off_tx_cmds_revA = [29 00 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 b0 03 f6 29 01 00 00 00 00 04 f6 00 00 90 29 00 00 00 00 00 03 bf 00 07 29 01 00 00 00 00 03 f0 a5 a5];
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samsung,ccd_test_on_tx_cmds_revA = [29 00 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 b0 02 cc 29 01 00 00 01 00 02 cc 01 29 01 00 00 00 00 03 f0 a5 a5];
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samsung,ccd_pass_val = <0x00>;
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samsung,ccd_fail_val = <0x04>;
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samsung,ccd_state_rx_cmds_revA = [06 01 00 00 00 00 01 cd 01 0e];
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samsung,ccd_test_off_tx_cmds_revA = [29 00 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 b0 02 cc 29 01 00 00 00 00 02 cc 00 29 01 00 00 00 00 03 f0 a5 a5];
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samsung,acl_on_tx_cmds_revA = [29 01 00 00 00 00 02 55 02];
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samsung,acl_off_tx_cmds_revA = [29 01 00 00 00 00 02 55 00];
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samsung,elvss_rx_cmds_revA = [06 01 00 00 00 00 01 b5 19];
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samsung,ffc_cmds_line_position = <0x02>;
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samsung,ffc_tx_cmds_revA = [29 00 00 00 00 00 03 f0 5a 5a 29 00 00 00 00 00 03 fc 5a 5a 29 00 00 00 00 00 0a c5 0d 10 64 1e af 05 00 26 b0 29 00 00 00 00 00 03 f0 a5 a5 29 00 00 00 00 00 03 fc a5 a5];
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samsung,dyn_mipi_clk_ffc_cmds_revA = [29 00 00 00 00 00 0a c5 0d 10 64 1e af 05 00 26 b0 29 00 00 00 00 00 0a c5 0d 10 64 1e af 05 00 26 b0 29 00 00 00 00 00 0a c5 0d 10 64 1e 32 05 00 26 b0 29 00 00 00 00 00 0a c5 0d 10 64 1f 61 05 00 26 b0 29 00 00 00 00 00 0a c5 0d 10 64 1f 34 05 00 26 b0];
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samsung,dynamic_mipi_clk_timing_table = <0x461ff720 0x461ff720 0x4741e1e0 0x44933ca0 0x44f66b40>;
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samsung,dynamic_mipi_clk_sel_table = <0x01 0x01 0x00 0x00 0x03 0x01 0x02 0x00 0x00 0x04 0x01 0x03 0x00 0x00 0x01 0x01 0x04 0x00 0x00 0x03 0x02 0x0b 0x2942 0x2950 0x02 0x02 0x0b 0x2951 0x29fb 0x01 0x02 0x0b 0x29fc 0x2a46 0x02 0x02 0x0b 0x2a47 0x2a56 0x01 0x02 0x0c 0x25be 0x2626 0x01 0x02 0x0c 0x2627 0x2671 0x02 0x02 0x0c 0x2672 0x26d2 0x01 0x02 0x0d 0x48a 0x4cf 0x02 0x02 0x0d 0x4d0 0x579 0x01 0x02 0x0d 0x57a 0x5c4 0x02 0x02 0x0d 0x5c5 0x5e9 0x01 0x02 0x0e 0x601 0x60f 0x02 0x02 0x0e 0x610 0x6ba 0x01 0x02 0x0e 0x6bb 0x6ca 0x02 0x02 0x0f 0x1105 0x1116 0x01 0x02 0x0f 0x1117 0x115d 0x02 0x02 0x0f 0x115e 0x1161 0x03 0x02 0x0f 0x1162 0x116a 0x01 0x02 0x11 0x8bd 0x913 0x01 0x02 0x11 0x914 0x929 0x04 0x02 0x11 0x92a 0x93a 0x03 0x02 0x11 0x93b 0x95e 0x02 0x02 0x11 0x95f 0xa03 0x01 0x02 0x12 0xb79 0xbb2 0x02 0x02 0x12 0xbb3 0xc10 0x01 0x03 0x5b 0x00 0x35 0x02 0x03 0x5b 0x36 0x18a 0x01 0x03 0x5b 0x18b 0x220 0x02 0x03 0x5b 0x221 0x257 0x01 0x03 0x5c 0x258 0x341 0x01 0x03 0x5c 0x342 0x3d7 0x02 0x03 0x5c 0x3d8 0x4af 0x01 0x03 0x5d 0x4b0 0x4bc 0x01 0x03 0x5d 0x4bd 0x552 0x02 0x03 0x5d 0x553 0x6a6 0x01 0x03 0x5d 0x6a7 0x73c 0x02 0x03 0x5d 0x73d 0x79d 0x01 0x03 0x5e 0x79e 0x7d3 0x02 0x03 0x5e 0x7d4 0x928 0x01 0x03 0x5e 0x929 0x95f 0x02 0x03 0x5f 0x960 0x99a 0x01 0x03 0x5f 0x99b 0xa29 0x02 0x03 0x5f 0xa2a 0xa30 0x03 0x03 0x5f 0xa31 0xa59 0x01 0x03 0x61 0xabe 0xb82 0x01 0x03 0x61 0xb83 0xbae 0x04 0x03 0x61 0xbaf 0xbd1 0x03 0x03 0x61 0xbd2 0xc18 0x02 0x03 0x61 0xc19 0xd6c 0x01 0x03 0x61 0xd6d 0xd79 0x04 0x03 0x62 0xd7a 0xe04 0x02 0x03 0x62 0xe05 0xed7 0x01 0x03 0x66 0x1392 0x13fc 0x02 0x03 0x66 0x13fd 0x141c 0x03 0x03 0x66 0x141d 0x143b 0x01 0x03 0x67 0x143c 0x149f 0x01 0x03 0x68 0x14a0 0x1503 0x01 0x03 0x6b 0x1662 0x169a 0x02 0x03 0x6b 0x169b 0x16ba 0x03 0x03 0x6b 0x16bb 0x16d9 0x01 0x03 0x6c 0x16da 0x176f 0x01 0x03 0x6d 0x1770 0x17fd 0x02 0x03 0x6d 0x17fe 0x1805 0x03 0x03 0x6e 0x1806 0x180e 0x03 0x03 0x6e 0x180f 0x1931 0x01 0x03 0x6f 0x1932 0x19c7 0x01 0x03 0x73 0x1f68 0x2051 0x01 0x03 0x73 0x2052 0x20e7 0x02 0x03 0x73 0x20e8 0x21f1 0x01 0x03 0x74 0x21f2 0x2290 0x01 0x03 0x74 0x2291 0x231f 0x02 0x03 0x74 0x2320 0x2326 0x03 0x03 0x74 0x2327 0x234f 0x01 0x03 0x76 0x23fa 0x24b6 0x01 0x03 0x76 0x24b7 0x2534 0x02 0x03 0x76 0x2535 0x254c 0x03 0x03 0x76 0x254d 0x25bb 0x01 0x03 0x77 0x25bc 0x2629 0x01 0x03 0x78 0x262a 0x268d 0x02 0x03 0x7a 0x26c0 0x272f 0x01 0x03 0x7a 0x2730 0x27c5 0x02 0x03 0x7a 0x27c6 0x2877 0x01 0x03 0x7c 0x8d68 0x8db1 0x02 0x03 0x7c 0x8db2 0x8dfd 0x01 0x03 0x80 0x9376 0x9444 0x01 0x03 0x80 0x9445 0x9479 0x04 0x03 0x80 0x9862 0x948b 0x03 0x03 0x80 0x948c 0x94da 0x02 0x03 0x80 0x94db 0x9569 0x01 0x03 0x81 0x956a 0x965d 0x01 0x03 0x81 0x965e 0x96f3 0x02 0x03 0x81 0x96f4 0x96f9 0x01 0x03 0x82 0x96fa 0x976c 0x02 0x03 0x82 0x976d 0x98c0 0x01 0x03 0x82 0x98c1 0x98e0 0x04 0x03 0x82 0x98e1 0x9956 0x02 0x03 0x82 0x9957 0x9aab 0x01 0x03 0x82 0x9aac 0x9ad2 0x04 0x03 0x82 0x9ad3 0x9ae1 0x02 0x03 0x83 0x9ae2 0x9af7 0x04 0x03 0x83 0x9af8 0x9b55 0x02 0x03 0x83 0x9b56 0x9ca9 0x01 0x03 0x83 0x9caa 0x9ce7 0x04 0x03 0x83 0x9ce8 0x9d3f 0x02 0x03 0x83 0x9d40 0x9e94 0x01 0x03 0x83 0x9e95 0x9ec8 0x04 0x03 0x83 0x9ec9 0x9edb 0x03 0x03 0x83 0x9edc 0x9f2a 0x02 0x03 0x83 0x9f2b 0xa07e 0x01 0x03 0x83 0xa07f 0xa0aa 0x04 0x03 0x83 0xa0ab 0xa0cd 0x03 0x03 0x83 0xa0ce 0xa114 0x02 0x03 0x83 0xa115 0xa268 0x01 0x03 0x83 0xa269 0xa275 0x04 0x03 0x84 0xa276 0xa365 0x01 0x03 0x84 0xa366 0xa39d 0x02 0x03 0x84 0xa39e 0xa3fb 0x03 0x03 0x84 0xa3fc 0xa54f 0x01 0x03 0x84 0xa550 0xa58f 0x02 0x03 0x84 0xa590 0xa5e5 0x03 0x03 0x84 0xa5e6 0xa73a 0x01 0x03 0x84 0xa73b 0xa781 0x02 0x03 0x84 0xa782 0xa7d0 0x03 0x03 0x84 0xa7d1 0xa924 0x01 0x03 0x84 0xa925 0xa974 0x02 0x03 0x84 0xa975 0xa9ba 0x03 0x03 0x84 0xa9bb 0xaa45 0x01 0x03 0x8a 0xd7c8 0xd89a 0x01 0x03 0x8a 0xd89b 0xd8ea 0x02 0x03 0x8a 0xd8eb 0xd930 0x03 0x03 0x8a 0xd931 0xda84 0x01 0x03 0x8a 0xda85 0xdadc 0x02 0x03 0x8a 0xdadd 0xdb1a 0x03 0x03 0x8a 0xdb1b 0xdc6e 0x01 0x03 0x8a 0xdc6f 0xdcce 0x02 0x03 0x8a 0xdccf 0xdd00 0x03 0x03 0x8a 0xdd01 0xdd04 0x04 0x03 0x8a 0xdd05 0xdda3 0x01 0x03 0x9c 0x10384 0x103b9 0x02 0x03 0x9c 0x103ba 0x1050e 0x01 0x03 0x9c 0x1050f 0x105a4 0x02 0x03 0x9c 0x105a5 0x106f8 0x01 0x03 0x9c 0x106f9 0x10700 0x04 0x03 0x9c 0x10701 0x10707 0x02 0x03 0xa1 0x10bea 0x10c69 0x01 0x03 0xa1 0x10c6a 0x10cd0 0x02 0x03 0xa1 0x10cd1 0x10cff 0x03 0x03 0xa1 0x10d00 0x10d47 0x01 0x04 0x33 0x00 0x00 0x02 0x04 0x34 0x00 0x00 0x01 0x04 0x35 0x00 0x00 0x02 0x04 0x36 0x00 0x00 0x01 0x04 0x37 0x00 0x00 0x04 0x04 0x38 0x00 0x00 0x02 0x05 0x3d 0x00 0x00 0x02 0x05 0x3e 0x00 0x00 0x01 0x05 0x47 0x00 0x00 0x01>;
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samsung,gamma_mode2_candela_map_table_revA = <0x00 0x00 0x00 0x03 0x02 0x01 0x01 0x01 0x06 0x03 0x02 0x02 0x02 0x09 0x04 0x03 0x03 0x03 0x0c 0x06 0x04 0x04 0x04 0x0f 0x07 0x05 0x05 0x05 0x12 0x08 0x06 0x06 0x06 0x15 0x09 0x07 0x07 0x07 0x18 0x0a 0x08 0x08 0x08 0x1b 0x0c 0x09 0x09 0x09 0x1e 0x0d 0x0a 0x0a 0x0a 0x21 0x0e 0x0b 0x0b 0x0b 0x24 0x0f 0x0c 0x0c 0x0c 0x27 0x10 0x0d 0x0d 0x0d 0x2a 0x12 0x0e 0x0e 0x0e 0x2d 0x13 0x0f 0x0f 0x0f 0x30 0x14 0x10 0x10 0x10 0x34 0x16 0x11 0x11 0x11 0x37 0x17 0x12 0x12 0x12 0x3b 0x18 0x13 0x13 0x13 0x3e 0x1a 0x14 0x14 0x14 0x42 0x1b 0x15 0x15 0x15 0x46 0x1d 0x16 0x16 0x16 0x49 0x1e 0x17 0x17 0x17 0x4d 0x20 0x18 0x18 0x18 0x50 0x21 0x19 0x19 0x19 0x54 0x22 0x1a 0x1a 0x1a 0x58 0x24 0x1b 0x1b 0x1b 0x5b 0x25 0x1c 0x1c 0x1c 0x5f 0x27 0x1d 0x1d 0x1d 0x62 0x28 0x1e 0x1e 0x1e 0x66 0x2a 0x1f 0x1f 0x1f 0x6a 0x2b 0x20 0x20 0x20 0x6d 0x2c 0x21 0x21 0x21 0x71 0x2e 0x22 0x22 0x22 0x74 0x2f 0x23 0x23 0x23 0x78 0x31 0x24 0x24 0x24 0x7c 0x32 0x25 0x25 0x25 0x7f 0x34 0x26 0x26 0x26 0x83 0x35 0x27 0x27 0x27 0x86 0x36 0x28 0x28 0x28 0x8a 0x38 0x29 0x29 0x29 0x8e 0x3a 0x2a 0x2a 0x2a 0x91 0x3b 0x2b 0x2b 0x2b 0x95 0x3c 0x2c 0x2c 0x2c 0x98 0x3e 0x2d 0x2d 0x2d 0x9c 0x3f 0x2e 0x2e 0x2e 0xa0 0x41 0x2f 0x2f 0x2f 0xa3 0x42 0x30 0x30 0x30 0xa7 0x44 0x31 0x31 0x31 0xaa 0x45 0x32 0x32 0x32 0xae 0x46 0x33 0x33 0x33 0xb2 0x48 0x34 0x34 0x34 0xb5 0x49 0x35 0x35 0x35 0xb9 0x4b 0x36 0x36 0x36 0xbc 0x4c 0x37 0x37 0x37 0xc0 0x4e 0x38 0x38 0x38 0xc4 0x4f 0x39 0x39 0x39 0xc7 0x50 0x3a 0x3a 0x3a 0xcb 0x52 0x3b 0x3b 0x3b 0xce 0x53 0x3c 0x3c 0x3c 0xd2 0x55 0x3d 0x3d 0x3d 0xd6 0x56 0x3e 0x3e 0x3e 0xd9 0x58 0x3f 0x3f 0x3f 0xdd 0x59 0x40 0x40 0x40 0xe0 0x5a 0x41 0x41 0x41 0xe4 0x5c 0x42 0x42 0x42 0xe8 0x5e 0x43 0x43 0x43 0xeb 0x5f 0x44 0x44 0x44 0xef 0x61 0x45 0x45 0x45 0xf2 0x62 0x46 0x46 0x46 0xf6 0x63 0x47 0x47 0x47 0xfa 0x65 0x48 0x48 0x48 0xfd 0x66 0x49 0x49 0x49 0x101 0x68 0x4a 0x4a 0x4a 0x104 0x69 0x4b 0x4b 0x4b 0x108 0x6b 0x4c 0x4c 0x4c 0x10c 0x6c 0x4d 0x4d 0x4d 0x10f 0x6d 0x4e 0x4e 0x4e 0x113 0x6f 0x4f 0x4f 0x4f 0x116 0x70 0x50 0x50 0x50 0x11a 0x72 0x51 0x51 0x51 0x11e 0x73 0x52 0x52 0x52 0x121 0x75 0x53 0x53 0x53 0x125 0x76 0x54 0x54 0x54 0x129 0x78 0x55 0x55 0x55 0x12c 0x79 0x56 0x56 0x56 0x130 0x7b 0x57 0x57 0x57 0x133 0x7c 0x58 0x58 0x58 0x137 0x7d 0x59 0x59 0x59 0x13b 0x7f 0x5a 0x5a 0x5a 0x13e 0x80 0x5b 0x5b 0x5b 0x142 0x82 0x5c 0x5c 0x5c 0x145 0x83 0x5d 0x5d 0x5d 0x149 0x85 0x5e 0x5e 0x5e 0x14d 0x86 0x5f 0x5f 0x5f 0x150 0x87 0x60 0x60 0x60 0x154 0x89 0x61 0x61 0x61 0x157 0x8a 0x62 0x62 0x62 0x15b 0x8c 0x63 0x63 0x63 0x15f 0x8d 0x64 0x64 0x64 0x162 0x8f 0x65 0x65 0x65 0x166 0x90 0x66 0x66 0x66 0x169 0x91 0x67 0x67 0x67 0x16d 0x93 0x68 0x68 0x68 0x171 0x95 0x69 0x69 0x69 0x174 0x96 0x6a 0x6a 0x6a 0x178 0x97 0x6b 0x6b 0x6b 0x17b 0x99 0x6c 0x6c 0x6c 0x17f 0x9a 0x6d 0x6d 0x6d 0x183 0x9c 0x6e 0x6e 0x6e 0x186 0x9d 0x6f 0x6f 0x6f 0x18a 0x9f 0x70 0x70 0x70 0x18d 0xa0 0x71 0x71 0x71 0x191 0xa1 0x72 0x72 0x72 0x195 0xa3 0x73 0x73 0x73 0x198 0xa4 0x74 0x74 0x74 0x19c 0xa6 0x75 0x75 0x75 0x19f 0xa7 0x76 0x76 0x76 0x1a3 0xa9 0x77 0x77 0x77 0x1a7 0xaa 0x78 0x78 0x78 0x1aa 0xab 0x79 0x79 0x79 0x1ae 0xad 0x7a 0x7a 0x7a 0x1b1 0xae 0x7b 0x7b 0x7b 0x1b5 0xb0 0x7c 0x7c 0x7c 0x1b9 0xb1 0x7d 0x7d 0x7d 0x1bc 0xb3 0x7e 0x7e 0x7e 0x1c0 0xb4 0x7f 0x7f 0x7f 0x1c3 0xb5 0x80 0x80 0x80 0x1c7 0xb7 0x81 0x81 0x81 0x1cb 0xb9 0x82 0x82 0x82 0x1d0 0xbb 0x83 0x83 0x83 0x1d4 0xbc 0x84 0x84 0x84 0x1d9 0xbf 0x85 0x85 0x85 0x1dd 0xc0 0x86 0x86 0x86 0x1e2 0xc2 0x87 0x87 0x87 0x1e6 0xc4 0x88 0x88 0x88 0x1eb 0xc6 0x89 0x89 0x89 0x1ef 0xc8 0x8a 0x8a 0x8a 0x1f4 0xca 0x8b 0x8b 0x8b 0x1f8 0xcb 0x8c 0x8c 0x8c 0x1fd 0xce 0x8d 0x8d 0x8d 0x201 0xcf 0x8e 0x8e 0x8e 0x206 0xd1 0x8f 0x8f 0x8f 0x20a 0xd3 0x90 0x90 0x90 0x20f 0xd5 0x91 0x91 0x91 0x213 0xd7 0x92 0x92 0x92 0x217 0xd8 0x93 0x93 0x93 0x21c 0xda 0x94 0x94 0x94 0x220 0xdc 0x95 0x95 0x95 0x225 0xde 0x96 0x96 0x96 0x229 0xe0 0x97 0x97 0x97 0x22e 0xe2 0x98 0x98 0x98 0x232 0xe4 0x99 0x99 0x99 0x237 0xe6 0x9a 0x9a 0x9a 0x23b 0xe7 0x9b 0x9b 0x9b 0x240 0xe9 0x9c 0x9c 0x9c 0x244 0xeb 0x9d 0x9d 0x9d 0x249 0xed 0x9e 0x9e 0x9e 0x24d 0xef 0x9f 0x9f 0x9f 0x252 0xf1 0xa0 0xa0 0xa0 0x256 0xf3 0xa1 0xa1 0xa1 0x25b 0xf5 0xa2 0xa2 0xa2 0x25f 0xf6 0xa3 0xa3 0xa3 0x264 0xf9 0xa4 0xa4 0xa4 0x268 0xfa 0xa5 0xa5 0xa5 0x26c 0xfc 0xa6 0xa6 0xa6 0x271 0xfe 0xa7 0xa7 0xa7 0x275 0x100 0xa8 0xa8 0xa8 0x27a 0x102 0xa9 0xa9 0xa9 0x27e 0x103 0xaa 0xaa 0xaa 0x283 0x105 0xab 0xab 0xab 0x287 0x107 0xac 0xac 0xac 0x28c 0x109 0xad 0xad 0xad 0x290 0x10b 0xae 0xae 0xae 0x295 0x10d 0xaf 0xaf 0xaf 0x299 0x10f 0xb0 0xb0 0xb0 0x29e 0x111 0xb1 0xb1 0xb1 0x2a2 0x112 0xb2 0xb2 0xb2 0x2a7 0x114 0xb3 0xb3 0xb3 0x2ab 0x116 0xb4 0xb4 0xb4 0x2b0 0x118 0xb5 0xb5 0xb5 0x2b4 0x11a 0xb6 0xb6 0xb6 0x2b8 0x11c 0xb7 0xb7 0xb7 0x2bd 0x11e 0xb8 0xb8 0xb8 0x2c1 0x11f 0xb9 0xb9 0xb9 0x2c6 0x121 0xba 0xba 0xba 0x2ca 0x123 0xbb 0xbb 0xbb 0x2cf 0x125 0xbc 0xbc 0xbc 0x2d3 0x127 0xbd 0xbd 0xbd 0x2d8 0x129 0xbe 0xbe 0xbe 0x2dc 0x12b 0xbf 0xbf 0xbf 0x2e1 0x12d 0xc0 0xc0 0xc0 0x2e5 0x12e 0xc1 0xc1 0xc1 0x2ea 0x130 0xc2 0xc2 0xc2 0x2ee 0x132 0xc3 0xc3 0xc3 0x2f3 0x134 0xc4 0xc4 0xc4 0x2f7 0x136 0xc5 0xc5 0xc5 0x2fc 0x138 0xc6 0xc6 0xc6 0x300 0x13a 0xc7 0xc7 0xc7 0x305 0x13c 0xc8 0xc8 0xc8 0x309 0x13d 0xc9 0xc9 0xc9 0x30d 0x13f 0xca 0xca 0xca 0x312 0x141 0xcb 0xcb 0xcb 0x316 0x143 0xcc 0xcc 0xcc 0x31b 0x145 0xcd 0xcd 0xcd 0x31f 0x147 0xce 0xce 0xce 0x324 0x149 0xcf 0xcf 0xcf 0x328 0x14a 0xd0 0xd0 0xd0 0x32d 0x14c 0xd1 0xd1 0xd1 0x331 0x14e 0xd2 0xd2 0xd2 0x336 0x150 0xd3 0xd3 0xd3 0x33a 0x152 0xd4 0xd4 0xd4 0x33f 0x154 0xd5 0xd5 0xd5 0x343 0x156 0xd6 0xd6 0xd6 0x348 0x158 0xd7 0xd7 0xd7 0x34c 0x159 0xd8 0xd8 0xd8 0x351 0x15b 0xd9 0xd9 0xd9 0x355 0x15d 0xda 0xda 0xda 0x35a 0x15f 0xdb 0xdb 0xdb 0x35e 0x161 0xdc 0xdc 0xdc 0x362 0x162 0xdd 0xdd 0xdd 0x367 0x165 0xde 0xde 0xde 0x36b 0x166 0xdf 0xdf 0xdf 0x370 0x168 0xe0 0xe0 0xe0 0x374 0x16a 0xe1 0xe1 0xe1 0x379 0x16c 0xe2 0xe2 0xe2 0x37d 0x16e 0xe3 0xe3 0xe3 0x382 0x170 0xe4 0xe4 0xe4 0x386 0x172 0xe5 0xe5 0xe5 0x38b 0x174 0xe6 0xe6 0xe6 0x38f 0x175 0xe7 0xe7 0xe7 0x394 0x177 0xe8 0xe8 0xe8 0x398 0x179 0xe9 0xe9 0xe9 0x39d 0x17b 0xea 0xea 0xea 0x3a1 0x17d 0xeb 0xeb 0xeb 0x3a6 0x17f 0xec 0xec 0xec 0x3aa 0x181 0xed 0xed 0xed 0x3ae 0x182 0xee 0xee 0xee 0x3b3 0x184 0xef 0xef 0xef 0x3b7 0x186 0xf0 0xf0 0xf0 0x3bc 0x188 0xf1 0xf1 0xf1 0x3c0 0x18a 0xf2 0xf2 0xf2 0x3c5 0x18c 0xf3 0xf3 0xf3 0x3c9 0x18d 0xf4 0xf4 0xf4 0x3ce 0x190 0xf5 0xf5 0xf5 0x3d2 0x191 0xf6 0xf6 0xf6 0x3d7 0x193 0xf7 0xf7 0xf7 0x3db 0x195 0xf8 0xf8 0xf8 0x3e0 0x197 0xf9 0xf9 0xf9 0x3e4 0x199 0xfa 0xfa 0xfa 0x3e9 0x19b 0xfb 0xfb 0xfb 0x3ed 0x19c 0xfc 0xfc 0xfc 0x3f2 0x19f 0xfd 0xfd 0xfd 0x3f6 0x1a0 0xfe 0xfe 0xfe 0x3fb 0x1a2 0xff 0xff 0xff 0x3ff 0x1a4 0x100 0x100 0x100 0x03 0x1a5 0x101 0x101 0x101 0x05 0x1a7 0x102 0x102 0x102 0x07 0x1a8 0x103 0x103 0x103 0x09 0x1a9 0x104 0x104 0x104 0x0c 0x1ac 0x105 0x105 0x105 0x0e 0x1ad 0x106 0x106 0x106 0x11 0x1af 0x107 0x107 0x107 0x13 0x1b0 0x108 0x108 0x108 0x15 0x1b2 0x109 0x109 0x109 0x18 0x1b4 0x10a 0x10a 0x10a 0x1a 0x1b5 0x10b 0x10b 0x10b 0x1d 0x1b7 0x10c 0x10c 0x10c 0x1f 0x1b9 0x10d 0x10d 0x10d 0x21 0x1ba 0x10e 0x10e 0x10e 0x24 0x1bc 0x10f 0x10f 0x10f 0x26 0x1be 0x110 0x110 0x110 0x28 0x1bf 0x111 0x111 0x111 0x2b 0x1c1 0x112 0x112 0x112 0x2d 0x1c2 0x113 0x113 0x113 0x30 0x1c5 0x114 0x114 0x114 0x32 0x1c6 0x115 0x115 0x115 0x34 0x1c7 0x116 0x116 0x116 0x37 0x1c9 0x117 0x117 0x117 0x39 0x1cb 0x118 0x118 0x118 0x3b 0x1cc 0x119 0x119 0x119 0x3e 0x1ce 0x11a 0x11a 0x11a 0x40 0x1d0 0x11b 0x11b 0x11b 0x43 0x1d2 0x11c 0x11c 0x11c 0x45 0x1d3 0x11d 0x11d 0x11d 0x47 0x1d5 0x11e 0x11e 0x11e 0x4a 0x1d7 0x11f 0x11f 0x11f 0x4c 0x1d8 0x120 0x120 0x120 0x4e 0x1d9 0x121 0x121 0x121 0x51 0x1dc 0x122 0x122 0x122 0x53 0x1dd 0x123 0x123 0x123 0x56 0x1df 0x124 0x124 0x124 0x58 0x1e0 0x125 0x125 0x125 0x5a 0x1e2 0x126 0x126 0x126 0x5d 0x1e4 0x127 0x127 0x127 0x5f 0x1e5 0x128 0x128 0x128 0x61 0x1e7 0x129 0x129 0x129 0x64 0x1e9 0x12a 0x12a 0x12a 0x66 0x1ea 0x12b 0x12b 0x12b 0x69 0x1ec 0x12c 0x12c 0x12c 0x6b 0x1ee 0x12d 0x12d 0x12d 0x6d 0x1ef 0x12e 0x12e 0x12e 0x70 0x1f1 0x12f 0x12f 0x12f 0x72 0x1f2 0x130 0x130 0x130 0x74 0x1f4 0x131 0x131 0x131 0x77 0x1f6 0x132 0x132 0x132 0x79 0x1f7 0x133 0x133 0x133 0x7c 0x1f9 0x134 0x134 0x134 0x7e 0x1fb 0x135 0x135 0x135 0x80 0x1fc 0x136 0x136 0x136 0x83 0x1fe 0x137 0x137 0x137 0x85 0x200 0x138 0x138 0x138 0x87 0x201 0x139 0x139 0x139 0x8a 0x203 0x13a 0x13a 0x13a 0x8c 0x205 0x13b 0x13b 0x13b 0x8f 0x207 0x13c 0x13c 0x13c 0x91 0x208 0x13d 0x13d 0x13d 0x93 0x209 0x13e 0x13e 0x13e 0x96 0x20b 0x13f 0x13f 0x13f 0x98 0x20d 0x140 0x140 0x140 0x9a 0x20e 0x141 0x141 0x141 0x9d 0x210 0x142 0x142 0x142 0x9f 0x212 0x143 0x143 0x143 0xa2 0x214 0x144 0x144 0x144 0xa4 0x215 0x145 0x145 0x145 0xa6 0x217 0x146 0x146 0x146 0xa9 0x219 0x147 0x147 0x147 0xab 0x21a 0x148 0x148 0x148 0xad 0x21b 0x149 0x149 0x149 0xb0 0x21e 0x14a 0x14a 0x14a 0xb2 0x21f 0x14b 0x14b 0x14b 0xb5 0x221 0x14c 0x14c 0x14c 0xb7 0x222 0x14d 0x14d 0x14d 0xb9 0x224 0x14e 0x14e 0x14e 0xbc 0x226 0x14f 0x14f 0x14f 0xbe 0x227 0x150 0x150 0x150 0xc0 0x229 0x151 0x151 0x151 0xc3 0x22b 0x152 0x152 0x152 0xc5 0x22c 0x153 0x153 0x153 0xc8 0x22e 0x154 0x154 0x154 0xca 0x230 0x155 0x155 0x155 0xcc 0x231 0x156 0x156 0x156 0xcf 0x233 0x157 0x157 0x157 0xd1 0x234 0x158 0x158 0x158 0xd3 0x236 0x159 0x159 0x159 0xd6 0x238 0x15a 0x15a 0x15a 0xd8 0x239 0x15b 0x15b 0x15b 0xdb 0x23b 0x15c 0x15c 0x15c 0xdd 0x23d 0x15d 0x15d 0x15d 0xdf 0x23e 0x15e 0x15e 0x15e 0xe2 0x240 0x15f 0x15f 0x15f 0xe4 0x242 0x160 0x160 0x160 0xe7 0x244 0x161 0x161 0x161 0xe9 0x245 0x162 0x162 0x162 0xeb 0x247 0x163 0x163 0x163 0xee 0x249 0x164 0x164 0x164 0xf0 0x24a 0x165 0x165 0x165 0xf2 0x24b 0x166 0x166 0x166 0xf5 0x24d 0x167 0x167 0x167 0xf7 0x24f 0x168 0x168 0x168 0xfa 0x251 0x169 0x169 0x169 0xfc 0x252 0x16a 0x16a 0x16a 0xfe 0x254 0x16b 0x16b 0x16b 0x101 0x256 0x16c 0x16c 0x16c 0x103 0x257 0x16d 0x16d 0x16d 0x105 0x259 0x16e 0x16e 0x16e 0x108 0x25b 0x16f 0x16f 0x16f 0x10a 0x25c 0x170 0x170 0x170 0x10d 0x25e 0x171 0x171 0x171 0x10f 0x260 0x172 0x172 0x172 0x111 0x261 0x173 0x173 0x173 0x114 0x263 0x174 0x174 0x174 0x116 0x264 0x175 0x175 0x175 0x118 0x266 0x176 0x176 0x176 0x11b 0x268 0x177 0x177 0x177 0x11d 0x269 0x178 0x178 0x178 0x120 0x26b 0x179 0x179 0x179 0x122 0x26d 0x17a 0x17a 0x17a 0x124 0x26e 0x17b 0x17b 0x17b 0x127 0x270 0x17c 0x17c 0x17c 0x129 0x272 0x17d 0x17d 0x17d 0x12b 0x273 0x17e 0x17e 0x17e 0x12e 0x275 0x17f 0x17f 0x17f 0x130 0x276 0x180 0x180 0x180 0x133 0x279 0x181 0x181 0x181 0x135 0x27a 0x182 0x182 0x182 0x137 0x27b 0x183 0x183 0x183 0x13a 0x27d 0x184 0x184 0x184 0x13c 0x27f 0x185 0x185 0x185 0x13e 0x280 0x186 0x186 0x186 0x141 0x282 0x187 0x187 0x187 0x143 0x284 0x188 0x188 0x188 0x146 0x286 0x189 0x189 0x189 0x148 0x287 0x18a 0x18a 0x18a 0x14a 0x289 0x18b 0x18b 0x18b 0x14d 0x28b 0x18c 0x18c 0x18c 0x14f 0x28c 0x18d 0x18d 0x18d 0x151 0x28d 0x18e 0x18e 0x18e 0x154 0x290 0x18f 0x18f 0x18f 0x156 0x291 0x190 0x190 0x190 0x159 0x293 0x191 0x191 0x191 0x15b 0x294 0x192 0x192 0x192 0x15d 0x296 0x193 0x193 0x193 0x160 0x298 0x194 0x194 0x194 0x162 0x299 0x195 0x195 0x195 0x164 0x29b 0x196 0x196 0x196 0x167 0x29d 0x197 0x197 0x197 0x169 0x29e 0x198 0x198 0x198 0x16c 0x2a0 0x199 0x199 0x199 0x16e 0x2a2 0x19a 0x19a 0x19a 0x170 0x2a3 0x19b 0x19b 0x19b 0x173 0x2a5 0x19c 0x19c 0x19c 0x175 0x2a6 0x19d 0x19d 0x19d 0x177 0x2a8 0x19e 0x19e 0x19e 0x17a 0x2aa 0x19f 0x19f 0x19f 0x17c 0x2ab 0x1a0 0x1a0 0x1a0 0x17f 0x2ad 0x1a1 0x1a1 0x1a1 0x181 0x2af 0x1a2 0x1a2 0x1a2 0x183 0x2b0 0x1a3 0x1a3 0x1a3 0x186 0x2b2 0x1a4 0x1a4 0x1a4 0x188 0x2b4 0x1a5 0x1a5 0x1a5 0x18a 0x2b5 0x1a6 0x1a6 0x1a6 0x18d 0x2b7 0x1a7 0x1a7 0x1a7 0x18f 0x2b9 0x1a8 0x1a8 0x1a8 0x192 0x2bb 0x1a9 0x1a9 0x1a9 0x194 0x2bc>;
|
|
samsung,aod_candela_map_table_revA = <0x00 0x00 0x27 0x02 0x01 0x28 0x46 0x0a 0x02 0x47 0x5d 0x1e 0x03 0x5e 0xff 0x3c>;
|
|
samsung,gamma_mode2_tx_cmds_revA = [39 00 00 00 00 00 02 53 20 39 00 00 00 00 00 04 b5 19 8d 10 39 01 00 00 00 00 03 51 03 ff];
|
|
samsung,fd_on_tx_cmds_revA = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 b0 0b b5 29 01 00 00 00 00 02 b5 40 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,fd_off_tx_cmds_revA = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 b0 0b b5 29 01 00 00 00 00 02 b5 80 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,lpm_on_tx_cmds_revA = [29 00 00 00 00 00 03 f0 5a 5a 29 00 00 00 00 00 03 b0 02 bb 29 00 00 00 00 00 03 bb 09 18 29 00 00 00 01 00 02 53 22 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,lpm_off_tx_cmds_revA = [29 00 00 00 00 00 03 f0 5a 5a 29 00 00 00 01 00 02 53 20 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,lpm_2nit_tx_cmds_revA = [29 01 00 00 01 00 02 53 23];
|
|
samsung,lpm_10nit_tx_cmds_revA = [29 01 00 00 01 00 02 53 22];
|
|
samsung,lpm_30nit_tx_cmds_revA = [29 01 00 00 01 00 02 53 22];
|
|
samsung,lpm_60nit_tx_cmds_revA = [29 01 00 00 01 00 02 53 22];
|
|
samsung,lpm_ctrl_hlpm_2nit_tx_cmds_revA = [29 01 00 00 00 00 03 bb 89 07];
|
|
samsung,lpm_ctrl_hlpm_10nit_tx_cmds_revA = [29 01 00 00 00 00 03 bb 89 07];
|
|
samsung,lpm_ctrl_hlpm_30nit_tx_cmds_revA = [29 01 00 00 00 00 03 bb 59 0c];
|
|
samsung,lpm_ctrl_hlpm_60nit_tx_cmds_revA = [29 01 00 00 00 00 03 bb 09 18];
|
|
samsung,lpm_brightnes_tx_cmds_revA = [29 00 00 00 00 00 03 f0 5a 5a 29 00 00 00 01 00 02 53 22 29 00 00 00 00 00 03 b0 02 bb 29 00 00 00 00 00 03 bb 09 18 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,lpm-init-delay-ms = <0x7c>;
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-display-active;
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4eb>;
|
|
qcom,platform-reset-gpio = <0x16c 0x0b 0x00>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
samsung,ub-con-det = <0x16c 0x42 0x00>;
|
|
samsung,support-optical-fingerprint;
|
|
phandle = <0x4eb>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
fhd {
|
|
qcom,display-topology = <0x01 0x00 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0x960>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x79>;
|
|
qcom,mdss-dsi-h-back-porch = <0x7a>;
|
|
qcom,mdss-dsi-h-front-porch = <0x78>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x02>;
|
|
qcom,mdss-dsi-v-back-porch = <0x10>;
|
|
qcom,mdss-dsi-v-front-porch = <0xf8>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-panel-clockrate = <0x461ff720>;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x270a0a 0x27250a0b 0x7020400>;
|
|
qcom,mdss-dsi-t-clk-pre = <0x3b>;
|
|
qcom,mdss-dsi-t-clk-post = <0x0f>;
|
|
qcom,mdss-fd-on-command = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 b0 0b b5 29 01 00 00 00 00 02 b5 40 29 01 00 00 00 00 03 f0 a5 a5];
|
|
qcom,mdss-dsi-on-command = [05 01 00 00 0a 00 02 11 00 29 00 00 00 00 00 03 f0 5a 5a 29 00 00 00 00 00 02 35 00 29 00 00 00 00 00 03 f0 a5 a5 29 00 00 00 00 00 05 2a 00 00 04 37 29 00 00 00 00 00 05 2b 00 00 09 5f 29 00 00 00 00 00 03 f0 5a 5a 29 00 00 00 00 00 03 fc 5a 5a 29 00 00 00 00 00 02 e5 13 29 00 00 00 00 00 03 ed 00 4c 29 00 00 00 00 00 03 f0 a5 a5 29 00 00 00 00 00 03 fc a5 a5 29 00 00 00 00 00 03 f0 5a 5a 29 00 00 00 00 00 0a b9 00 80 e8 09 00 00 00 11 03 29 00 00 00 00 00 03 f0 a5 a5];
|
|
qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
|
|
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
|
};
|
|
};
|
|
|
|
qcom,panel-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,panel-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "vddi";
|
|
qcom,supply-min-voltage = <0x00>;
|
|
qcom,supply-max-voltage = <0x00>;
|
|
qcom,supply-enable-load = <0x00>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
qcom,supply-pre-off-sleep = <0x00>;
|
|
qcom,supply-post-on-sleep = <0x00>;
|
|
};
|
|
|
|
qcom,panel-supply-entry@1 {
|
|
reg = <0x01>;
|
|
qcom,supply-name = "vddr";
|
|
qcom,supply-min-voltage = <0x00>;
|
|
qcom,supply-max-voltage = <0x00>;
|
|
qcom,supply-enable-load = <0x00>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
qcom,supply-pre-off-sleep = <0x00>;
|
|
qcom,supply-post-on-sleep = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ss_dsi_panel_PBA_BOOTING_FHD {
|
|
qcom,mdss-dsi-panel-name = "ss_dsi_panel_PBA_BOOTING_FHD";
|
|
label = "ss_dsi_panel_PBA_BOOTING_FHD";
|
|
qcom,mdss-dsi-bpp = <0x18>;
|
|
qcom,mdss-dsi-underflow-color = <0xff>;
|
|
qcom,mdss-dsi-border-color = <0x00>;
|
|
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
|
qcom,mdss-dsi-bl-min-level = <0x00>;
|
|
qcom,mdss-dsi-bl-max-level = <0x639c>;
|
|
qcom,mdss-brightness-max-level = <0x639c>;
|
|
qcom,mdss-dsi-interleave-mode = <0x00>;
|
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
|
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
|
qcom,mdss-dsi-bllp-eof-power-mode;
|
|
qcom,mdss-dsi-bllp-power-mode;
|
|
qcom,mdss-dsi-pixel-packing = "loose";
|
|
qcom,mdss-dsi-virtual-channel-id = <0x00>;
|
|
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
|
qcom,mdss-dsi-lane-0-state;
|
|
qcom,mdss-dsi-lane-1-state;
|
|
qcom,mdss-dsi-lane-2-state;
|
|
qcom,mdss-dsi-lane-3-state;
|
|
qcom,mdss-dsi-stream = <0x00>;
|
|
qcom,mdss-dsi-mdp-trigger = "none";
|
|
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
|
qcom,mdss-pan-physical-width-dimension = <0x3c>;
|
|
qcom,mdss-pan-physical-height-dimension = <0x6a>;
|
|
qcom,mdss-dsi-panel-mode-gpio-state = "invalid";
|
|
qcom,mdss-dsi-reset-sequence = <0x00 0x0a 0x01 0x0a>;
|
|
qcom,adjust-timer-wakeup-ms = <0x01>;
|
|
qcom,mdss-dsi-lp11-init;
|
|
qcom,mdss-dsi-rx-eot-ignore;
|
|
qcom,mdss-dsi-tx-eot-append;
|
|
samsung,candela_map_table_revA = <0x00 0x00 0x02 0x05 0x01 0x02 0x02 0x06 0x02 0x03 0x03 0x07 0x03 0x04 0x04 0x08 0x04 0x05 0x05 0x09 0x05 0x06 0x06 0x0a 0x06 0x07 0x07 0x0b 0x07 0x08 0x08 0x0c 0x08 0x09 0x09 0x0d 0x09 0x0a 0x0a 0x0e 0x0a 0x0b 0x0b 0x0f 0x0b 0x0c 0x0c 0x10 0x0c 0x0d 0x0d 0x11 0x0d 0x0e 0x0e 0x13 0x0e 0x0f 0x0f 0x14 0x0f 0x10 0x10 0x15 0x10 0x11 0x11 0x16 0x11 0x12 0x12 0x18 0x12 0x13 0x13 0x19 0x13 0x14 0x14 0x1b 0x14 0x15 0x15 0x1d 0x15 0x16 0x16 0x1e 0x16 0x17 0x18 0x20 0x17 0x19 0x1a 0x22 0x18 0x1b 0x1c 0x25 0x19 0x1d 0x1d 0x27 0x1a 0x1e 0x20 0x29 0x1b 0x21 0x22 0x2c 0x1c 0x23 0x24 0x2f 0x1d 0x25 0x26 0x32 0x1e 0x27 0x28 0x35 0x1f 0x29 0x2b 0x38 0x20 0x2c 0x2e 0x3c 0x21 0x2f 0x31 0x40 0x22 0x32 0x34 0x44 0x23 0x35 0x38 0x48 0x24 0x39 0x3b 0x4d 0x25 0x3c 0x3f 0x52 0x26 0x40 0x43 0x57 0x27 0x44 0x47 0x5d 0x28 0x48 0x4c 0x62 0x29 0x4d 0x50 0x69 0x2a 0x51 0x56 0x6f 0x2b 0x57 0x5b 0x77 0x2c 0x5c 0x61 0x7e 0x2d 0x62 0x68 0x86 0x2e 0x69 0x6e 0x8f 0x2f 0x6f 0x76 0x98 0x30 0x77 0x7d 0xa2 0x31 0x7e 0x85 0xac 0x32 0x86 0x8e 0xb7 0x33 0x8f 0x96 0xc3 0x34 0x97 0xa0 0xcf 0x35 0xa1 0xaa 0xdc 0x36 0xab 0xb5 0xea 0x37 0xb6 0xc1 0xf9 0x38 0xc2 0xcd 0x109 0x39 0xce 0xda 0x11a 0x3a 0xdb 0xe6 0x12c 0x3b 0xe7 0xf2 0x13c 0x3c 0xf3 0xfe 0x14d 0x3d 0xff 0xff 0x168>;
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-display-active;
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4ec>;
|
|
qcom,platform-reset-gpio = <0x16c 0x0b 0x00>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
phandle = <0x4ec>;
|
|
|
|
qcom,mdss-dsi-display-timings {
|
|
|
|
fhd@0 {
|
|
qcom,display-topology = <0x01 0x00 0x01>;
|
|
qcom,default-topology-index = <0x00>;
|
|
qcom,mdss-dsi-panel-width = <0x438>;
|
|
qcom,mdss-dsi-panel-height = <0x780>;
|
|
qcom,mdss-dsi-panel-framerate = <0x3c>;
|
|
qcom,mdss-dsi-h-pulse-width = <0x0c>;
|
|
qcom,mdss-dsi-h-back-porch = <0x20>;
|
|
qcom,mdss-dsi-h-front-porch = <0xa4>;
|
|
qcom,mdss-dsi-h-sync-skew = <0x00>;
|
|
qcom,mdss-dsi-v-pulse-width = <0x04>;
|
|
qcom,mdss-dsi-v-back-porch = <0x03>;
|
|
qcom,mdss-dsi-v-front-porch = <0x09>;
|
|
qcom,mdss-dsi-panel-clockrate = <0x35866480>;
|
|
qcom,mdss-dsi-panel-phy-timings = <0x1e0808 0x24220808 0x8020400>;
|
|
qcom,mdss-dsi-on-command = [39 01 00 00 78 00 02 11 00];
|
|
qcom,mdss-dsi-off-command = <0x5010000 0x24000128 0x5010000 0x78000110>;
|
|
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
|
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,sde_rscc@af20000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,sde-rsc";
|
|
reg = <0xaf20000 0x1c44 0xaf30000 0x3fd4>;
|
|
reg-names = "drv\0wrapper";
|
|
qcom,sde-rsc-version = <0x02>;
|
|
vdd-supply = <0xc3>;
|
|
clocks = <0x2a 0x25 0x2a 0x1d 0x2a 0x24>;
|
|
clock-names = "vsync_clk\0gdsc_clk\0iface_clk";
|
|
clock-rate = <0x00 0x00 0x00>;
|
|
qcom,sde-dram-channels = <0x02>;
|
|
mboxes = <0xc7 0x00>;
|
|
mbox-names = "disp_rsc";
|
|
phandle = <0x360>;
|
|
|
|
qcom,sde-data-bus {
|
|
qcom,msm-bus,name = "disp_rsc_mnoc";
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-cases = <0x03>;
|
|
qcom,msm-bus,num-paths = <0x02>;
|
|
qcom,msm-bus,vectors-KBps = <0x4e23 0x5023 0x00 0x00 0x4e24 0x5023 0x00 0x00 0x4e23 0x5023 0x00 0x61a800 0x4e24 0x5023 0x00 0x61a800 0x4e23 0x5023 0x00 0x61a800 0x4e24 0x5023 0x00 0x61a800>;
|
|
};
|
|
|
|
qcom,sde-llcc-bus {
|
|
qcom,msm-bus,name = "disp_rsc_llcc";
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-cases = <0x03>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x4e21 0x5021 0x00 0x00 0x4e21 0x5021 0x00 0x61a800 0x4e21 0x5021 0x00 0x61a800>;
|
|
};
|
|
|
|
qcom,sde-ebi-bus {
|
|
qcom,msm-bus,name = "disp_rsc_ebi";
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-cases = <0x03>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x4e20 0x5020 0x00 0x00 0x4e20 0x5020 0x00 0x61a800 0x4e20 0x5020 0x00 0x61a800>;
|
|
};
|
|
};
|
|
|
|
qcom,mdss_rotator@ae00000 {
|
|
compatible = "qcom,sde_rotator";
|
|
reg = <0xae00000 0xac000 0xaeb8000 0x3000>;
|
|
reg-names = "mdp_phys\0rot_vbif_phys";
|
|
#list-cells = <0x01>;
|
|
qcom,mdss-rot-mode = <0x01>;
|
|
qcom,mdss-highest-bank-bit = <0x01>;
|
|
qcom,msm-bus,name = "mdss_rotator";
|
|
qcom,msm-bus,num-cases = <0x03>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x19 0x200 0x00 0x00 0x19 0x200 0x00 0x61a800 0x19 0x200 0x00 0x61a800>;
|
|
rot-vdd-supply = <0xc3>;
|
|
qcom,supply-names = "rot-vdd";
|
|
clocks = <0x27 0x1c 0x27 0x20 0x2a 0x01 0x2a 0x22>;
|
|
clock-names = "gcc_iface\0gcc_bus\0iface_clk\0rot_clk";
|
|
interrupt-parent = <0x19e>;
|
|
interrupts = <0x02 0x00>;
|
|
power-domains = <0x19e>;
|
|
qcom,mdss-rot-vbif-qos-setting = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>;
|
|
qcom,mdss-rot-vbif-memtype = <0x03 0x03>;
|
|
qcom,mdss-rot-cdp-setting = <0x01 0x01>;
|
|
qcom,mdss-rot-qos-lut = <0x00 0x00 0x00 0x00>;
|
|
qcom,mdss-rot-danger-lut = <0x00 0x00>;
|
|
qcom,mdss-rot-safe-lut = <0xffff 0xffff>;
|
|
qcom,mdss-rot-qos-cpu-mask = <0x0f>;
|
|
qcom,mdss-rot-qos-cpu-dma-latency = <0x4b>;
|
|
qcom,mdss-default-ot-rd-limit = <0x20>;
|
|
qcom,mdss-default-ot-wr-limit = <0x20>;
|
|
qcom,mdss-sbuf-headroom = <0x14>;
|
|
cache-slice-names = "rotator";
|
|
cache-slices = <0x19f 0x04>;
|
|
phandle = <0x361>;
|
|
|
|
qcom,rot-reg-bus {
|
|
qcom,msm-bus,name = "mdss_rot_reg";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00>;
|
|
phandle = <0x362>;
|
|
};
|
|
|
|
qcom,smmu_rot_unsec_cb {
|
|
compatible = "qcom,smmu_sde_rot_unsec";
|
|
iommus = <0x30 0x1020 0x00>;
|
|
phandle = <0x363>;
|
|
};
|
|
|
|
qcom,smmu_rot_sec_cb {
|
|
compatible = "qcom,smmu_sde_rot_sec";
|
|
iommus = <0x30 0x1021 0x00>;
|
|
phandle = <0x364>;
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_ctrl0@ae94000 {
|
|
compatible = "qcom,dsi-ctrl-hw-v2.3";
|
|
label = "dsi-ctrl-0";
|
|
cell-index = <0x00>;
|
|
reg = <0xae94000 0x400 0xaf08000 0x04>;
|
|
reg-names = "dsi_ctrl\0disp_cc_base";
|
|
interrupt-parent = <0x19e>;
|
|
interrupts = <0x04 0x00>;
|
|
vdda-1p2-supply = <0x1a0>;
|
|
clocks = <0x2a 0x03 0x2a 0x04 0x2a 0x06 0x2a 0x1e 0x2a 0x1f 0x2a 0x16>;
|
|
clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk";
|
|
phandle = <0x365>;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <0x1174c0>;
|
|
qcom,supply-max-voltage = <0x12cc80>;
|
|
qcom,supply-enable-load = <0x5528>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0x00>;
|
|
qcom,supply-max-voltage = <0x00>;
|
|
qcom,supply-enable-load = <0x00>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_ctrl1@ae96000 {
|
|
compatible = "qcom,dsi-ctrl-hw-v2.3";
|
|
label = "dsi-ctrl-1";
|
|
cell-index = <0x01>;
|
|
reg = <0xae96000 0x400 0xaf08000 0x04>;
|
|
reg-names = "dsi_ctrl\0disp_cc_base";
|
|
interrupt-parent = <0x19e>;
|
|
interrupts = <0x05 0x00>;
|
|
vdda-1p2-supply = <0x1a0>;
|
|
clocks = <0x2a 0x07 0x2a 0x08 0x2a 0x0a 0x2a 0x20 0x2a 0x21 0x2a 0x18>;
|
|
clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk";
|
|
phandle = <0x366>;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <0x1174c0>;
|
|
qcom,supply-max-voltage = <0x12cc80>;
|
|
qcom,supply-enable-load = <0x5528>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0x00>;
|
|
qcom,supply-max-voltage = <0x00>;
|
|
qcom,supply-enable-load = <0x00>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_phy0@ae94400 {
|
|
compatible = "qcom,dsi-phy-v3.0";
|
|
label = "dsi-phy-0";
|
|
cell-index = <0x00>;
|
|
reg = <0xae94400 0x7c0 0xae94200 0x100>;
|
|
reg-names = "dsi_phy\0dyn_refresh_base";
|
|
vdda-0p9-supply = <0x1a1>;
|
|
qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00];
|
|
qcom,platform-lane-config = <0x00 0x00 0x00 0x00 0x80>;
|
|
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
|
phandle = <0x367>;
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <0xc92c0>;
|
|
qcom,supply-max-voltage = <0xe09c0>;
|
|
qcom,supply-enable-load = <0x8ca0>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,mdss_dsi_phy1@ae96400 {
|
|
compatible = "qcom,dsi-phy-v3.0";
|
|
label = "dsi-phy-1";
|
|
cell-index = <0x01>;
|
|
reg = <0xae96400 0x7c0 0xae96200 0x100>;
|
|
reg-names = "dsi_phy\0dyn_refresh_base";
|
|
vdda-0p9-supply = <0x1a1>;
|
|
qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00];
|
|
qcom,platform-lane-config = <0x00 0x00 0x00 0x00 0x80>;
|
|
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
|
phandle = <0x368>;
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <0xc92c0>;
|
|
qcom,supply-max-voltage = <0xe09c0>;
|
|
qcom,supply-enable-load = <0x8ca0>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,msm-ext-disp {
|
|
compatible = "qcom,msm-ext-disp";
|
|
phandle = <0x1a3>;
|
|
|
|
qcom,msm-ext-disp-audio-codec-rx {
|
|
compatible = "qcom,msm-ext-disp-audio-codec-rx";
|
|
phandle = <0x369>;
|
|
};
|
|
};
|
|
|
|
qcom,dp_display@0 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,dp-display";
|
|
vdda-1p2-supply = <0x1a0>;
|
|
vdda-0p9-supply = <0x1a1>;
|
|
reg = <0xae90000 0xdc 0xae90200 0xc0 0xae90400 0x508 0xae90a00 0x94 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf02000 0x1e0 0x780000 0x621c 0x88ea030 0x10 0x88e8000 0x20 0xaee1000 0x34 0xae91000 0x94>;
|
|
reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_mmss_cc\0qfprom_physical\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1";
|
|
interrupt-parent = <0x19e>;
|
|
interrupts = <0x0c 0x00>;
|
|
clocks = <0x2a 0x0b 0x27 0x97 0x2f 0x00 0x27 0x92 0x27 0x96 0x2a 0x0f 0x2a 0x11 0x2a 0x0d 0x2a 0x15 0x1a2 0x05 0x2a 0x13 0x1a2 0x05 0x2a 0x14 0x2a 0x12>;
|
|
clock-names = "core_aux_clk\0core_usb_ahb_clk\0core_usb_ref_clk_src\0core_usb_ref_clk\0core_usb_pipe_clk\0link_clk\0link_iface_clk\0crypto_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0pixel1_parent\0strm0_pixel_clk\0strm1_pixel_clk";
|
|
qcom,aux-cfg0-settings = " ";
|
|
qcom,aux-cfg1-settings = <0x2413231d>;
|
|
qcom,aux-cfg2-settings = [28 24];
|
|
qcom,aux-cfg3-settings = ",";
|
|
qcom,aux-cfg4-settings = [30 0a];
|
|
qcom,aux-cfg5-settings = [34 26];
|
|
qcom,aux-cfg6-settings = [38 0a];
|
|
qcom,aux-cfg7-settings = [3c 03];
|
|
qcom,aux-cfg8-settings = [40 bb];
|
|
qcom,aux-cfg9-settings = [44 03];
|
|
qcom,max-pclk-frequency-khz = <0xa4cb8>;
|
|
qcom,ext-disp = <0x1a3>;
|
|
qcom,usbplug-cc-gpio = <0x16c 0x68 0x00>;
|
|
pinctrl-names = "mdss_dp_active\0mdss_dp_sleep";
|
|
pinctrl-0 = <0x1a4>;
|
|
pinctrl-1 = <0x1a5>;
|
|
phandle = <0x36a>;
|
|
qcom,dp-usbpd-detection = <0x253>;
|
|
qcom,dp-aux-switch = <0x29b>;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <0x1174c0>;
|
|
qcom,supply-max-voltage = <0x12cc80>;
|
|
qcom,supply-enable-load = <0x5528>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <0xc92c0>;
|
|
qcom,supply-max-voltage = <0xe09c0>;
|
|
qcom,supply-enable-load = <0x8ca0>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0x00>;
|
|
qcom,supply-max-voltage = <0x00>;
|
|
qcom,supply-enable-load = <0x00>;
|
|
qcom,supply-disable-load = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,cam-req-mgr {
|
|
compatible = "qcom,cam-req-mgr";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,csiphy@ace0000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,csiphy-v1.2\0qcom,csiphy";
|
|
reg = <0xace0000 0x2000>;
|
|
reg-names = "csiphy";
|
|
reg-cam-base = <0xe0000>;
|
|
interrupts = <0x00 0x1dd 0x00>;
|
|
interrupt-names = "csiphy";
|
|
regulator-names = "gdscr\0refgen";
|
|
gdscr-supply = <0x1a6>;
|
|
refgen-supply = <0x1a7>;
|
|
csi-vdd-voltage = <0x124f80>;
|
|
mipi-csi-vdd-supply = <0x1a0>;
|
|
clocks = <0x29 0x1b 0x29 0x24 0x29 0x1d 0x29 0x1c>;
|
|
clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk";
|
|
src-clock-name = "csi0phytimer_clk_src";
|
|
clock-cntl-level = "svs\0svs_l1\0turbo";
|
|
clock-rates = <0x16e36000 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x11e1a300 0x00>;
|
|
status = "ok";
|
|
phandle = <0x36b>;
|
|
};
|
|
|
|
qcom,csiphy@ace2000 {
|
|
cell-index = <0x01>;
|
|
compatible = "qcom,csiphy-v1.2\0qcom,csiphy";
|
|
reg = <0xace2000 0x2000>;
|
|
reg-names = "csiphy";
|
|
reg-cam-base = <0xe2000>;
|
|
interrupts = <0x00 0x1de 0x00>;
|
|
interrupt-names = "csiphy";
|
|
regulator-names = "gdscr\0refgen";
|
|
gdscr-supply = <0x1a6>;
|
|
refgen-supply = <0x1a7>;
|
|
csi-vdd-voltage = <0x124f80>;
|
|
mipi-csi-vdd-supply = <0x1a0>;
|
|
clocks = <0x29 0x1b 0x29 0x24 0x29 0x25 0x29 0x1f 0x29 0x1e>;
|
|
clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk";
|
|
src-clock-name = "csi1phytimer_clk_src";
|
|
clock-cntl-level = "svs\0svs_l1\0turbo";
|
|
clock-rates = <0x16e36000 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00>;
|
|
status = "ok";
|
|
phandle = <0x36c>;
|
|
};
|
|
|
|
qcom,csiphy@ace4000 {
|
|
cell-index = <0x02>;
|
|
compatible = "qcom,csiphy-v1.2\0qcom,csiphy";
|
|
reg = <0xace4000 0x2000>;
|
|
reg-names = "csiphy";
|
|
reg-cam-base = <0xe4000>;
|
|
interrupts = <0x00 0x1df 0x00>;
|
|
interrupt-names = "csiphy";
|
|
regulator-names = "gdscr\0refgen";
|
|
gdscr-supply = <0x1a6>;
|
|
refgen-supply = <0x1a7>;
|
|
csi-vdd-voltage = <0x124f80>;
|
|
mipi-csi-vdd-supply = <0x1a0>;
|
|
clocks = <0x29 0x1b 0x29 0x24 0x29 0x26 0x29 0x21 0x29 0x20>;
|
|
clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk";
|
|
src-clock-name = "csi2phytimer_clk_src";
|
|
clock-cntl-level = "svs\0svs_l1\0turbo";
|
|
clock-rates = <0x16e36000 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00>;
|
|
status = "ok";
|
|
phandle = <0x36d>;
|
|
};
|
|
|
|
qcom,csiphy@ace6000 {
|
|
cell-index = <0x03>;
|
|
compatible = "qcom,csiphy-v1.2\0qcom,csiphy";
|
|
reg = <0xace6000 0x2000>;
|
|
reg-names = "csiphy";
|
|
reg-cam-base = <0xe6000>;
|
|
interrupts = <0x00 0x25f 0x00>;
|
|
interrupt-names = "csiphy";
|
|
regulator-names = "gdscr\0refgen";
|
|
gdscr-supply = <0x1a6>;
|
|
refgen-supply = <0x1a7>;
|
|
csi-vdd-voltage = <0x124f80>;
|
|
mipi-csi-vdd-supply = <0x1a0>;
|
|
clocks = <0x29 0x1b 0x29 0x24 0x29 0x27 0x29 0x23 0x29 0x22>;
|
|
clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk";
|
|
src-clock-name = "csi3phytimer_clk_src";
|
|
clock-cntl-level = "svs\0svs_l1\0turbo";
|
|
clock-rates = <0x16e36000 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x11e1a300 0x00>;
|
|
status = "ok";
|
|
phandle = <0x36e>;
|
|
};
|
|
|
|
qcom,cci@ac4a000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cci";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0xac4a000 0x1000>;
|
|
reg-names = "cci";
|
|
reg-cam-base = <0x4a000>;
|
|
interrupt-names = "cci";
|
|
interrupts = <0x00 0x1cc 0x00>;
|
|
status = "ok";
|
|
gdscr-supply = <0x1a6>;
|
|
regulator-names = "gdscr";
|
|
clocks = <0x29 0x15 0x29 0x16>;
|
|
clock-names = "cci_0_clk\0cci_0_clk_src";
|
|
src-clock-name = "cci_0_clk_src";
|
|
clock-cntl-level = "lowsvs";
|
|
clock-rates = <0x00 0x23c3460>;
|
|
pinctrl-names = "cam_default\0cam_suspend";
|
|
pinctrl-0 = <0x1a8 0x1a9>;
|
|
pinctrl-1 = <0x1aa 0x1ab>;
|
|
gpios = <0x16c 0x11 0x00 0x16c 0x12 0x00 0x16c 0x13 0x00 0x16c 0x14 0x00>;
|
|
gpio-req-tbl-num = <0x00 0x01 0x02 0x03>;
|
|
gpio-req-tbl-flags = <0x01 0x01 0x01 0x01>;
|
|
gpio-req-tbl-label = "CCI_I2C_DATA0\0CCI_I2C_CLK0\0CCI_I2C_DATA1\0CCI_I2C_CLK1";
|
|
phandle = <0x36f>;
|
|
|
|
qcom,i2c_standard_mode {
|
|
hw-thigh = <0xc9>;
|
|
hw-tlow = <0xae>;
|
|
hw-tsu-sto = <0xcc>;
|
|
hw-tsu-sta = <0xe7>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-thd-sta = <0xa2>;
|
|
hw-tbuf = <0xe3>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-trdhld = <0x06>;
|
|
hw-tsp = <0x03>;
|
|
cci-clk-src = <0x23c3460>;
|
|
status = "ok";
|
|
phandle = <0x370>;
|
|
};
|
|
|
|
qcom,i2c_fast_mode {
|
|
hw-thigh = <0x26>;
|
|
hw-tlow = <0x38>;
|
|
hw-tsu-sto = <0x28>;
|
|
hw-tsu-sta = <0x28>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-thd-sta = <0x23>;
|
|
hw-tbuf = <0x3e>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-trdhld = <0x06>;
|
|
hw-tsp = <0x03>;
|
|
cci-clk-src = <0x23c3460>;
|
|
status = "ok";
|
|
phandle = <0x371>;
|
|
};
|
|
|
|
qcom,i2c_custom_mode {
|
|
hw-thigh = <0x26>;
|
|
hw-tlow = <0x38>;
|
|
hw-tsu-sto = <0x28>;
|
|
hw-tsu-sta = <0x28>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-thd-sta = <0x23>;
|
|
hw-tbuf = <0x3e>;
|
|
hw-scl-stretch-en = <0x01>;
|
|
hw-trdhld = <0x06>;
|
|
hw-tsp = <0x03>;
|
|
cci-clk-src = <0x23c3460>;
|
|
status = "ok";
|
|
phandle = <0x372>;
|
|
};
|
|
|
|
qcom,i2c_fast_plus_mode {
|
|
hw-thigh = <0x10>;
|
|
hw-tlow = <0x16>;
|
|
hw-tsu-sto = <0x11>;
|
|
hw-tsu-sta = <0x12>;
|
|
hw-thd-dat = <0x10>;
|
|
hw-thd-sta = <0x0f>;
|
|
hw-tbuf = <0x18>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-trdhld = <0x03>;
|
|
hw-tsp = <0x03>;
|
|
cci-clk-src = <0x23c3460>;
|
|
status = "ok";
|
|
phandle = <0x373>;
|
|
};
|
|
|
|
qcom,cam-sensor@0 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cam-sensor";
|
|
reg = <0x00>;
|
|
csiphy-sd-index = <0x00>;
|
|
sensor-position-roll = <0x5a>;
|
|
sensor-position-pitch = <0x00>;
|
|
sensor-position-yaw = <0xb4>;
|
|
actuator-src = <0x55f>;
|
|
led-flash-src = <0x560>;
|
|
eeprom-src = <0x561>;
|
|
cam_vio-supply = <0x3ef>;
|
|
cam_vaf-supply = <0x562>;
|
|
cam_vana-supply = <0x563>;
|
|
cam_v_custom1-supply = <0x564>;
|
|
cam_vdig-supply = <0x3ed>;
|
|
cam_clk-supply = <0x1a6>;
|
|
regulator-names = "cam_vio\0cam_vaf\0cam_vana\0cam_v_custom1\0cam_vdig\0cam_clk";
|
|
rgltr-cntrl-support;
|
|
rgltr-min-voltage = <0x1b7740 0x2ab980 0x2ab980 0x1b7740 0x100590 0x00>;
|
|
rgltr-max-voltage = <0x1b7740 0x2ab980 0x2ab980 0x1b7740 0x100590 0x00>;
|
|
rgltr-load-current = <0x30d40 0x30d40 0x30d40 0x30d40 0x30d40 0x00>;
|
|
gpio-no-mux = <0x00>;
|
|
pinctrl-names = "cam_default\0cam_suspend";
|
|
pinctrl-0 = <0x565 0x566>;
|
|
pinctrl-1 = <0x567 0x568>;
|
|
gpios = <0x16c 0x0d 0x00 0x16c 0x21 0x00>;
|
|
gpio-reset = <0x01>;
|
|
gpio-req-tbl-num = <0x00 0x01>;
|
|
gpio-req-tbl-flags = <0x01 0x00>;
|
|
gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET0";
|
|
sensor-mode = <0x00>;
|
|
cci-device = <0x00>;
|
|
cci-master = <0x00>;
|
|
status = "ok";
|
|
clocks = <0x29 0x50>;
|
|
clock-names = "cam_clk";
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x16e3600>;
|
|
cam,isp = <0x00>;
|
|
cam,cal_memory = <0x02>;
|
|
cam,read_version = <0x00>;
|
|
cam,core_voltage = <0x00>;
|
|
cam,upgrade = <0x00>;
|
|
cam,fw_write = <0x00>;
|
|
cam,fw_dump = <0x00>;
|
|
cam,companion_chip = <0x00>;
|
|
cam,ois = <0x00>;
|
|
cam,dual_open = <0x00>;
|
|
cam,valid = <0x01>;
|
|
};
|
|
|
|
qcom,cam-sensor@1 {
|
|
cell-index = <0x01>;
|
|
compatible = "qcom,cam-sensor";
|
|
reg = <0x01>;
|
|
slave-addr = <0x34>;
|
|
csiphy-sd-index = <0x01>;
|
|
sensor-position-roll = <0x10e>;
|
|
sensor-position-pitch = <0x00>;
|
|
sensor-position-yaw = <0x00>;
|
|
eeprom-src = <0x569>;
|
|
cam_vio-supply = <0x564>;
|
|
cam_vana-supply = <0x56a>;
|
|
cam_vdig-supply = <0x56b>;
|
|
cam_v_custom1-supply = <0x3ef>;
|
|
cam_clk-supply = <0x1a6>;
|
|
regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_v_custom1\0cam_clk";
|
|
rgltr-cntrl-support;
|
|
rgltr-min-voltage = <0x1b7740 0x2c4020 0x100590 0x1b7740 0x00>;
|
|
rgltr-max-voltage = <0x1b7740 0x2c4020 0x100590 0x1b7740 0x00>;
|
|
rgltr-load-current = <0x30d40 0x30d40 0x30d40 0x30d40 0x00>;
|
|
gpio-no-mux = <0x00>;
|
|
pinctrl-names = "cam_default\0cam_suspend";
|
|
pinctrl-0 = <0x56c 0x56d>;
|
|
pinctrl-1 = <0x56e 0x56f>;
|
|
gpios = <0x16c 0x0e 0x00 0x16c 0x17 0x00>;
|
|
gpio-reset = <0x01>;
|
|
gpio-req-tbl-num = <0x00 0x01>;
|
|
gpio-req-tbl-flags = <0x01 0x00>;
|
|
gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET1";
|
|
sensor-mode = <0x00>;
|
|
cci-device = <0x00>;
|
|
cci-master = <0x01>;
|
|
status = "ok";
|
|
clocks = <0x29 0x52>;
|
|
clock-names = "cam_clk";
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x16e3600>;
|
|
cam,isp = <0x00>;
|
|
cam,cal_memory = <0x02>;
|
|
cam,read_version = <0x00>;
|
|
cam,core_voltage = <0x00>;
|
|
cam,upgrade = <0x00>;
|
|
cam,fw_write = <0x00>;
|
|
cam,fw_dump = <0x00>;
|
|
cam,companion_chip = <0x00>;
|
|
cam,ois = <0x00>;
|
|
cam,dual_open = <0x00>;
|
|
cam,valid = <0x01>;
|
|
};
|
|
|
|
qcom,cam-sensor@8 {
|
|
cell-index = <0x08>;
|
|
compatible = "qcom,cam-sensor";
|
|
reg = <0x08>;
|
|
slave-addr = <0x34>;
|
|
csiphy-sd-index = <0x01>;
|
|
sensor-position-roll = <0x10e>;
|
|
sensor-position-pitch = <0x00>;
|
|
sensor-position-yaw = <0x00>;
|
|
eeprom-src = <0x569>;
|
|
cam_vio-supply = <0x564>;
|
|
cam_vana-supply = <0x56a>;
|
|
cam_vdig-supply = <0x56b>;
|
|
cam_v_custom1-supply = <0x3ef>;
|
|
cam_clk-supply = <0x1a6>;
|
|
regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_v_custom1\0cam_clk";
|
|
rgltr-cntrl-support;
|
|
rgltr-min-voltage = <0x1b7740 0x2c4020 0x100590 0x1b7740 0x00>;
|
|
rgltr-max-voltage = <0x1b7740 0x2c4020 0x100590 0x1b7740 0x00>;
|
|
rgltr-load-current = <0x30d40 0x30d40 0x30d40 0x30d40 0x00>;
|
|
gpio-no-mux = <0x00>;
|
|
pinctrl-names = "cam_default\0cam_suspend";
|
|
pinctrl-0 = <0x56c 0x56d>;
|
|
pinctrl-1 = <0x56e 0x56f>;
|
|
gpios = <0x16c 0x0e 0x00 0x16c 0x17 0x00>;
|
|
gpio-reset = <0x01>;
|
|
gpio-req-tbl-num = <0x00 0x01>;
|
|
gpio-req-tbl-flags = <0x01 0x00>;
|
|
gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET1";
|
|
sensor-mode = <0x00>;
|
|
cci-device = <0x00>;
|
|
cci-master = <0x01>;
|
|
status = "ok";
|
|
clocks = <0x29 0x52>;
|
|
clock-names = "cam_clk";
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x16e3600>;
|
|
cam,isp = <0x00>;
|
|
cam,cal_memory = <0x02>;
|
|
cam,read_version = <0x00>;
|
|
cam,core_voltage = <0x00>;
|
|
cam,upgrade = <0x00>;
|
|
cam,fw_write = <0x00>;
|
|
cam,fw_dump = <0x00>;
|
|
cam,companion_chip = <0x00>;
|
|
cam,ois = <0x00>;
|
|
cam,dual_open = <0x00>;
|
|
cam,valid = <0x01>;
|
|
};
|
|
|
|
qcom,cam-sensor@3 {
|
|
cell-index = <0x03>;
|
|
compatible = "qcom,cam-sensor";
|
|
reg = <0x03>;
|
|
csiphy-sd-index = <0x03>;
|
|
sensor-position-roll = <0x5a>;
|
|
sensor-position-pitch = <0x00>;
|
|
sensor-position-yaw = <0xb4>;
|
|
eeprom-src = <0x570>;
|
|
cam_vio-supply = <0x3ef>;
|
|
cam_vdig-supply = <0x571>;
|
|
cam_vana-supply = <0x4ea>;
|
|
cam_clk-supply = <0x1a6>;
|
|
regulator-names = "cam_vio\0cam_vdig\0cam_vana\0cam_clk";
|
|
rgltr-cntrl-support;
|
|
rgltr-min-voltage = <0x1b7740 0x124f80 0x2ab980 0x00>;
|
|
rgltr-max-voltage = <0x1b7740 0x124f80 0x2ab980 0x00>;
|
|
rgltr-load-current = <0x30d40 0x30d40 0x30d40 0x00>;
|
|
gpio-no-mux = <0x00>;
|
|
pinctrl-names = "cam_default\0cam_suspend";
|
|
pinctrl-0 = <0x572 0x573>;
|
|
pinctrl-1 = <0x574 0x575>;
|
|
gpios = <0x16c 0x10 0x00 0x16c 0x43 0x00>;
|
|
gpio-reset = <0x01>;
|
|
gpio-req-tbl-num = <0x00 0x01>;
|
|
gpio-req-tbl-flags = <0x01 0x00>;
|
|
gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET2";
|
|
sensor-mode = <0x00>;
|
|
cci-device = <0x00>;
|
|
cci-master = <0x01>;
|
|
status = "ok";
|
|
clocks = <0x29 0x56>;
|
|
clock-names = "cam_clk";
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x16e3600>;
|
|
cam,isp = <0x00>;
|
|
cam,cal_memory = <0x00>;
|
|
cam,read_version = <0x00>;
|
|
cam,core_voltage = <0x00>;
|
|
cam,upgrade = <0x00>;
|
|
cam,fw_write = <0x00>;
|
|
cam,fw_dump = <0x00>;
|
|
cam,companion_chip = <0x00>;
|
|
cam,ois = <0x00>;
|
|
cam,dual_open = <0x00>;
|
|
cam,valid = <0x01>;
|
|
};
|
|
|
|
qcom,cam-sensor@2 {
|
|
cell-index = <0x02>;
|
|
compatible = "qcom,cam-sensor";
|
|
reg = <0x02>;
|
|
csiphy-sd-index = <0x02>;
|
|
sensor-position-roll = <0x5a>;
|
|
sensor-position-pitch = <0x00>;
|
|
sensor-position-yaw = <0xb4>;
|
|
eeprom-src = <0x576>;
|
|
cam_vio-supply = <0x3ef>;
|
|
cam_vdig-supply = <0x577>;
|
|
cam_clk-supply = <0x1a6>;
|
|
regulator-names = "cam_vio\0cam_vdig\0cam_clk";
|
|
rgltr-cntrl-support;
|
|
rgltr-min-voltage = <0x1b7740 0x100590 0x00>;
|
|
rgltr-max-voltage = <0x1b7740 0x100590 0x00>;
|
|
rgltr-load-current = <0x30d40 0x30d40 0x00>;
|
|
gpio-no-mux = <0x00>;
|
|
pinctrl-names = "cam_default\0cam_suspend";
|
|
pinctrl-0 = <0x578 0x579 0x57a 0x57b>;
|
|
pinctrl-1 = <0x57c 0x57d 0x57e 0x57f>;
|
|
gpios = <0x16c 0x0f 0x00 0x16c 0x35 0x00 0x16c 0x04 0x00 0x16c 0x33 0x00>;
|
|
gpio-reset = <0x01>;
|
|
gpio-vana = <0x02>;
|
|
gpio-custom1 = <0x03>;
|
|
gpio-req-tbl-num = <0x00 0x01 0x02 0x03>;
|
|
gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>;
|
|
gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET3\0CAM_VANA\0MIPI_SEL";
|
|
sensor-mode = <0x00>;
|
|
cci-device = <0x00>;
|
|
cci-master = <0x01>;
|
|
status = "ok";
|
|
clocks = <0x29 0x54>;
|
|
clock-names = "cam_clk";
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x16e3600>;
|
|
cam,isp = <0x00>;
|
|
cam,cal_memory = <0x02>;
|
|
cam,read_version = <0x00>;
|
|
cam,core_voltage = <0x00>;
|
|
cam,upgrade = <0x00>;
|
|
cam,fw_write = <0x00>;
|
|
cam,fw_dump = <0x00>;
|
|
cam,companion_chip = <0x00>;
|
|
cam,ois = <0x00>;
|
|
cam,dual_open = <0x00>;
|
|
cam,valid = <0x01>;
|
|
};
|
|
|
|
qcom,cam-sensor@4 {
|
|
cell-index = <0x04>;
|
|
compatible = "qcom,cam-sensor";
|
|
reg = <0x04>;
|
|
csiphy-sd-index = <0x02>;
|
|
sensor-position-roll = <0x5a>;
|
|
sensor-position-pitch = <0x00>;
|
|
sensor-position-yaw = <0xb4>;
|
|
led-flash-src = <0x560>;
|
|
eeprom-src = <0x580>;
|
|
cam_vio-supply = <0x3ef>;
|
|
cam_clk-supply = <0x1a6>;
|
|
regulator-names = "cam_vio\0cam_clk";
|
|
rgltr-cntrl-support;
|
|
rgltr-min-voltage = <0x1b7740 0x00>;
|
|
rgltr-max-voltage = <0x1b7740 0x00>;
|
|
rgltr-load-current = <0x30d40 0x00>;
|
|
gpio-no-mux = <0x00>;
|
|
pinctrl-names = "cam_default\0cam_suspend";
|
|
pinctrl-0 = <0x578 0x581 0x582 0x583 0x57b>;
|
|
pinctrl-1 = <0x57c 0x584 0x585 0x586 0x57f>;
|
|
gpios = <0x16c 0x0f 0x00 0x2e4 0x0b 0x00 0x2e4 0x0c 0x00 0x2e4 0x0a 0x00 0x16c 0x33 0x00>;
|
|
gpio-reset = <0x01>;
|
|
gpio-vana = <0x02>;
|
|
gpio-vdig = <0x03>;
|
|
gpio-custom1 = <0x04>;
|
|
gpio-req-tbl-num = <0x00 0x01 0x02 0x03 0x04>;
|
|
gpio-req-tbl-flags = <0x01 0x00 0x00 0x00 0x00>;
|
|
gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET2\0CAM_VANA\0CAM_VDIG\0MIPI_SEL";
|
|
sensor-mode = <0x00>;
|
|
cci-device = <0x00>;
|
|
cci-master = <0x01>;
|
|
status = "ok";
|
|
clocks = <0x29 0x54>;
|
|
clock-names = "cam_clk";
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x16e3600>;
|
|
cam,isp = <0x00>;
|
|
cam,cal_memory = <0x00>;
|
|
cam,read_version = <0x00>;
|
|
cam,core_voltage = <0x00>;
|
|
cam,upgrade = <0x00>;
|
|
cam,fw_write = <0x00>;
|
|
cam,fw_dump = <0x00>;
|
|
cam,companion_chip = <0x00>;
|
|
cam,ois = <0x00>;
|
|
cam,dual_open = <0x00>;
|
|
cam,valid = <0x01>;
|
|
};
|
|
};
|
|
|
|
qcom,cci@ac4b000 {
|
|
cell-index = <0x01>;
|
|
compatible = "qcom,cci";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0xac4b000 0x1000>;
|
|
reg-names = "cci";
|
|
reg-cam-base = <0x4b000>;
|
|
interrupt-names = "cci";
|
|
interrupts = <0x00 0x1cd 0x00>;
|
|
status = "ok";
|
|
gdscr-supply = <0x1a6>;
|
|
regulator-names = "gdscr";
|
|
clocks = <0x29 0x17 0x29 0x18>;
|
|
clock-names = "cci_clk\0cci_1_clk_src";
|
|
src-clock-name = "cci_1_clk_src";
|
|
clock-cntl-level = "lowsvs";
|
|
clock-rates = <0x00 0x23c3460>;
|
|
pinctrl-names = "cam_default\0cam_suspend";
|
|
pinctrl-0 = <0x1ac>;
|
|
pinctrl-1 = <0x1ad>;
|
|
gpios = <0x16c 0x1b 0x00 0x16c 0x1c 0x00>;
|
|
gpio-req-tbl-num = <0x00 0x01>;
|
|
gpio-req-tbl-flags = <0x01 0x01>;
|
|
gpio-req-tbl-label = "CCI_I2C_DATA2\0CCI_I2C_CLK2";
|
|
phandle = <0x374>;
|
|
|
|
qcom,i2c_standard_mode {
|
|
hw-thigh = <0xc9>;
|
|
hw-tlow = <0xae>;
|
|
hw-tsu-sto = <0xcc>;
|
|
hw-tsu-sta = <0xe7>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-thd-sta = <0xa2>;
|
|
hw-tbuf = <0xe3>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-trdhld = <0x06>;
|
|
hw-tsp = <0x03>;
|
|
cci-clk-src = <0x23c3460>;
|
|
status = "ok";
|
|
phandle = <0x375>;
|
|
};
|
|
|
|
qcom,i2c_fast_mode {
|
|
hw-thigh = <0x26>;
|
|
hw-tlow = <0x38>;
|
|
hw-tsu-sto = <0x28>;
|
|
hw-tsu-sta = <0x28>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-thd-sta = <0x23>;
|
|
hw-tbuf = <0x3e>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-trdhld = <0x06>;
|
|
hw-tsp = <0x03>;
|
|
cci-clk-src = <0x23c3460>;
|
|
status = "ok";
|
|
phandle = <0x376>;
|
|
};
|
|
|
|
qcom,i2c_custom_mode {
|
|
hw-thigh = <0x26>;
|
|
hw-tlow = <0x38>;
|
|
hw-tsu-sto = <0x28>;
|
|
hw-tsu-sta = <0x28>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-thd-sta = <0x23>;
|
|
hw-tbuf = <0x3e>;
|
|
hw-scl-stretch-en = <0x01>;
|
|
hw-trdhld = <0x06>;
|
|
hw-tsp = <0x03>;
|
|
cci-clk-src = <0x23c3460>;
|
|
status = "ok";
|
|
phandle = <0x377>;
|
|
};
|
|
|
|
qcom,i2c_fast_plus_mode {
|
|
hw-thigh = <0x10>;
|
|
hw-tlow = <0x16>;
|
|
hw-tsu-sto = <0x11>;
|
|
hw-tsu-sta = <0x12>;
|
|
hw-thd-dat = <0x10>;
|
|
hw-thd-sta = <0x0f>;
|
|
hw-tbuf = <0x18>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-trdhld = <0x03>;
|
|
hw-tsp = <0x03>;
|
|
cci-clk-src = <0x23c3460>;
|
|
status = "ok";
|
|
phandle = <0x378>;
|
|
};
|
|
|
|
qcom,actuator@0xC {
|
|
cell-index = <0x00>;
|
|
reg = <0x0c>;
|
|
cci-device = <0x01>;
|
|
cci-master = <0x00>;
|
|
slave-addr = <0x18>;
|
|
compatible = "qcom,actuator";
|
|
cam_vio-supply = <0x3ef>;
|
|
cam_vaf-supply = <0x562>;
|
|
regulator-names = "cam_vio\0cam_vaf";
|
|
rgltr-min-voltage = <0x1b7740 0x2ab980>;
|
|
rgltr-max-voltage = <0x1b7740 0x2ab980>;
|
|
rgltr-load-current = <0x30d40 0x30d40>;
|
|
phandle = <0x55f>;
|
|
};
|
|
|
|
qcom,eeprom@50 {
|
|
cell-index = <0x00>;
|
|
reg = <0x50>;
|
|
compatible = "qcom,eeprom";
|
|
i2c-freq-mode = <0x01>;
|
|
slave-addr = <0xa0>;
|
|
sensor-mode = <0x00>;
|
|
cci-device = <0x01>;
|
|
cci-master = <0x00>;
|
|
qcom,cam-power-seq-type = "sensor_vreg\0sensor_vreg";
|
|
qcom,cam-power-seq-val = "cam_vaf\0cam_vio";
|
|
qcom,cam-power-seq-cfg-val = <0x01 0x01>;
|
|
qcom,cam-power-seq-delay = <0x02 0x02>;
|
|
cam_vaf-supply = <0x562>;
|
|
cam_vio-supply = <0x3ef>;
|
|
regulator-names = "cam_vaf\0cam_vio";
|
|
rgltr-min-voltage = <0x2ab980 0x1b7740>;
|
|
rgltr-max-voltage = <0x2ab980 0x1b7740>;
|
|
rgltr-load-current = <0x30d40 0x30d40>;
|
|
sensor-position = <0x00>;
|
|
rgltr-cntrl-support;
|
|
phandle = <0x561>;
|
|
};
|
|
|
|
qcom,eeprom@51 {
|
|
cell-index = <0x01>;
|
|
reg = <0x51>;
|
|
compatible = "qcom,eeprom";
|
|
i2c-freq-mode = <0x01>;
|
|
cci-device = <0x01>;
|
|
cci-master = <0x00>;
|
|
slave-addr = <0xa2>;
|
|
qcom,cam-power-seq-type = "sensor_vreg\0sensor_vreg";
|
|
qcom,cam-power-seq-val = "cam_v_custom1\0cam_vio";
|
|
qcom,cam-power-seq-cfg-val = <0x01 0x01>;
|
|
qcom,cam-power-seq-delay = <0x02 0x02>;
|
|
cam_v_custom1-supply = <0x564>;
|
|
cam_vio-supply = <0x3ef>;
|
|
regulator-names = "cam_v_custom1\0cam_vio";
|
|
rgltr-min-voltage = <0x1b7740 0x1b7740>;
|
|
rgltr-max-voltage = <0x1b7740 0x1b7740>;
|
|
rgltr-load-current = <0x30d40 0x30d40>;
|
|
sensor-position = <0x01>;
|
|
rgltr-cntrl-support;
|
|
phandle = <0x569>;
|
|
};
|
|
|
|
qcom,eeprom@54 {
|
|
cell-index = <0x02>;
|
|
reg = <0x54>;
|
|
compatible = "qcom,eeprom";
|
|
i2c-freq-mode = <0x01>;
|
|
cci-device = <0x01>;
|
|
cci-master = <0x00>;
|
|
slave-addr = <0xa8>;
|
|
cam_vio-supply = <0x3ef>;
|
|
regulator-names = "cam_vio";
|
|
rgltr-min-voltage = <0x1b7740>;
|
|
rgltr-max-voltage = <0x1b7740>;
|
|
rgltr-load-current = <0x30d40>;
|
|
sensor-position = <0x00>;
|
|
rgltr-cntrl-support;
|
|
phandle = <0x576>;
|
|
};
|
|
|
|
qcom,eeprom@53 {
|
|
cell-index = <0x03>;
|
|
reg = <0x53>;
|
|
compatible = "qcom,eeprom";
|
|
i2c-freq-mode = <0x01>;
|
|
slave-addr = <0xa0>;
|
|
sensor-mode = <0x00>;
|
|
cci-device = <0x01>;
|
|
cci-master = <0x00>;
|
|
qcom,cam-power-seq-type = "sensor_vreg\0sensor_vreg";
|
|
qcom,cam-power-seq-val = "cam_vaf\0cam_vio";
|
|
qcom,cam-power-seq-cfg-val = <0x01 0x01>;
|
|
qcom,cam-power-seq-delay = <0x02 0x02>;
|
|
cam_vaf-supply = <0x562>;
|
|
cam_vio-supply = <0x3ef>;
|
|
regulator-names = "cam_vaf\0cam_vio";
|
|
rgltr-min-voltage = <0x2ab980 0x1b7740>;
|
|
rgltr-max-voltage = <0x2ab980 0x1b7740>;
|
|
rgltr-load-current = <0x30d40 0x30d40>;
|
|
sensor-position = <0x00>;
|
|
rgltr-cntrl-support;
|
|
phandle = <0x570>;
|
|
};
|
|
|
|
qcom,eeprom@52 {
|
|
cell-index = <0x04>;
|
|
reg = <0x52>;
|
|
compatible = "qcom,eeprom";
|
|
i2c-freq-mode = <0x01>;
|
|
cci-device = <0x01>;
|
|
cci-master = <0x00>;
|
|
slave-addr = <0xa4>;
|
|
cam_vio-supply = <0x3ef>;
|
|
regulator-names = "cam_vio";
|
|
rgltr-min-voltage = <0x1b7740>;
|
|
rgltr-max-voltage = <0x1b7740>;
|
|
rgltr-load-current = <0x30d40>;
|
|
sensor-position = <0x00>;
|
|
rgltr-cntrl-support;
|
|
phandle = <0x580>;
|
|
};
|
|
};
|
|
|
|
qcom,cam_smmu {
|
|
compatible = "qcom,msm-cam-smmu";
|
|
status = "ok";
|
|
|
|
msm_cam_smmu_ife {
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
iommus = <0x30 0x900 0x460 0x30 0xd00 0x460 0x30 0x880 0x460 0x30 0xc80 0x460 0x30 0x820 0x440 0x30 0xc20 0x440 0x30 0x920 0x460 0x30 0xd20 0x460 0x30 0x8a0 0x460 0x30 0xca0 0x460 0x30 0x940 0x460 0x30 0xd40 0x460 0x30 0x8c0 0x460 0x30 0xcc0 0x460>;
|
|
label = "ife";
|
|
|
|
iova-mem-map {
|
|
phandle = <0x379>;
|
|
|
|
iova-mem-region-io {
|
|
iova-region-name = "io";
|
|
iova-region-start = "\a@\0";
|
|
iova-region-len = <0xd8c00000>;
|
|
iova-region-id = <0x03>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_smmu_jpeg {
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
iommus = <0x30 0x1280 0x20 0x30 0x12a0 0x20>;
|
|
label = "jpeg";
|
|
|
|
iova-mem-map {
|
|
phandle = <0x37a>;
|
|
|
|
iova-mem-region-io {
|
|
iova-region-name = "io";
|
|
iova-region-start = "\a@\0";
|
|
iova-region-len = <0xd8c00000>;
|
|
iova-region-id = <0x03>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_icp_fw {
|
|
compatible = "qcom,msm-cam-smmu-fw-dev";
|
|
label = "icp";
|
|
memory-region = <0x1ae>;
|
|
};
|
|
|
|
msm_cam_smmu_icp {
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
iommus = <0x30 0x1180 0x00 0x30 0x11e0 0x00 0x30 0x11a0 0x00 0x30 0x1200 0x00 0x30 0x1260 0x00 0x30 0x1220 0x00 0x30 0x1042 0x00 0x30 0x1300 0x60 0x30 0x1320 0x60>;
|
|
label = "icp";
|
|
|
|
iova-mem-map {
|
|
phandle = <0x37b>;
|
|
|
|
iova-mem-region-firmware {
|
|
iova-region-name = "firmware";
|
|
iova-region-start = <0x00>;
|
|
iova-region-len = <0x500000>;
|
|
iova-region-id = <0x00>;
|
|
status = "ok";
|
|
};
|
|
|
|
iova-mem-region-shared {
|
|
iova-region-name = "shared";
|
|
iova-region-start = "\a@\0";
|
|
iova-region-len = "\t`\0";
|
|
iova-region-id = <0x01>;
|
|
status = "ok";
|
|
};
|
|
|
|
iova-mem-region-secondary-heap {
|
|
iova-region-name = "secheap";
|
|
iova-region-start = <0x10a00000>;
|
|
iova-region-len = <0x100000>;
|
|
iova-region-id = <0x04>;
|
|
status = "ok";
|
|
};
|
|
|
|
iova-mem-region-io {
|
|
iova-region-name = "io";
|
|
iova-region-start = <0x10c00000>;
|
|
iova-region-len = <0xa9c00000>;
|
|
iova-region-id = <0x03>;
|
|
status = "ok";
|
|
};
|
|
|
|
iova-mem-qdss-region {
|
|
iova-region-name = "qdss";
|
|
iova-region-start = <0x10b00000>;
|
|
iova-region-len = <0x100000>;
|
|
iova-region-id = <0x05>;
|
|
qdss-phy-addr = <0x16790000>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_smmu_cpas_cdm {
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
iommus = <0x30 0x1000 0x00>;
|
|
label = "cpas-cdm0";
|
|
|
|
iova-mem-map {
|
|
phandle = <0x37c>;
|
|
|
|
iova-mem-region-io {
|
|
iova-region-name = "io";
|
|
iova-region-start = "\a@\0";
|
|
iova-region-len = <0xd8c00000>;
|
|
iova-region-id = <0x03>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_smmu_secure {
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
label = "cam-secure";
|
|
qcom,secure-cb;
|
|
};
|
|
|
|
msm_cam_smmu_fd {
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
iommus = <0x30 0x12c0 0x20 0x30 0x12e0 0x20>;
|
|
label = "fd";
|
|
|
|
iova-mem-map {
|
|
phandle = <0x37d>;
|
|
|
|
iova-mem-region-io {
|
|
iova-region-name = "io";
|
|
iova-region-start = "\a@\0";
|
|
iova-region-len = <0xd8c00000>;
|
|
iova-region-id = <0x03>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_smmu_lrme {
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
iommus = <0x30 0x11c0 0x00 0x30 0x1240 0x00>;
|
|
label = "lrme";
|
|
|
|
iova-mem-map {
|
|
phandle = <0x37e>;
|
|
|
|
iova-mem-region-shared {
|
|
iova-region-name = "shared";
|
|
iova-region-start = "\a@\0";
|
|
iova-region-len = <0x6400000>;
|
|
iova-region-id = <0x01>;
|
|
status = "ok";
|
|
};
|
|
|
|
iova-mem-region-io {
|
|
iova-region-name = "io";
|
|
iova-region-start = <0xd800000>;
|
|
iova-region-len = <0xd2800000>;
|
|
iova-region-id = <0x03>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,cam-cdm-intf {
|
|
compatible = "qcom,cam-cdm-intf";
|
|
cell-index = <0x00>;
|
|
label = "cam-cdm-intf";
|
|
num-hw-cdm = <0x01>;
|
|
cdm-client-names = "vfe\0jpegdma\0jpegenc\0fd\0lrmecdm";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,cpas-cdm0@ac48000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cam170-cpas-cdm0";
|
|
label = "cpas-cdm";
|
|
reg = <0xac48000 0x1000>;
|
|
reg-names = "cpas-cdm";
|
|
reg-cam-base = <0x48000>;
|
|
interrupts = <0x00 0x1d4 0x00>;
|
|
interrupt-names = "cpas-cdm";
|
|
regulator-names = "camss";
|
|
camss-supply = <0x1a6>;
|
|
clock-names = "cam_cc_cpas_slow_ahb_clk\0cam_cc_cpas_ahb_clk";
|
|
clocks = <0x29 0x5a 0x29 0x1a>;
|
|
clock-rates = <0x00 0x00>;
|
|
clock-cntl-level = "svs";
|
|
cdm-client-names = "ife";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,cam-isp {
|
|
compatible = "qcom,cam-isp";
|
|
arch-compat = "ife";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,csid0@acb3000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,csid175_200";
|
|
reg-names = "csid";
|
|
reg = <0xacb3000 0x1000>;
|
|
reg-cam-base = "\0\v0";
|
|
interrupt-names = "csid";
|
|
interrupts = <0x00 0x1d0 0x00>;
|
|
regulator-names = "camss\0ife0";
|
|
camss-supply = <0x1a6>;
|
|
ife0-supply = <0x1af>;
|
|
clock-names = "ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk\0ife_axi_clk";
|
|
clocks = <0x29 0x35 0x29 0x34 0x29 0x1b 0x29 0x33 0x29 0x32 0x29 0x31 0x29 0x30>;
|
|
clock-rates = <0x11e1a300 0x00 0x00 0x00 0x16a65700 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x1e65fb80 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x25f7d940 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x2d4cae00 0x00 0x00>;
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";
|
|
src-clock-name = "ife_csid_clk_src";
|
|
clock-control-debugfs = "true";
|
|
status = "ok";
|
|
phandle = <0x37f>;
|
|
};
|
|
|
|
qcom,vfe0@acaf000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,vfe175_130";
|
|
reg-names = "ife\0cam_camnoc";
|
|
reg = <0xacaf000 0x5200 0xac42000 0x6000>;
|
|
reg-cam-base = <0xaf000 0x42000>;
|
|
interrupt-names = "ife";
|
|
interrupts = <0x00 0x1d1 0x00>;
|
|
regulator-names = "camss\0ife0";
|
|
camss-supply = <0x1a6>;
|
|
ife0-supply = <0x1af>;
|
|
clock-names = "ife_clk_src\0ife_clk\0ife_axi_clk";
|
|
clocks = <0x29 0x32 0x29 0x31 0x29 0x30>;
|
|
clock-rates = <0x16a65700 0x00 0x00 0x1e65fb80 0x00 0x00 0x25f7d940 0x00 0x00 0x2d4cae00 0x00 0x00>;
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";
|
|
src-clock-name = "ife_clk_src";
|
|
clock-control-debugfs = "true";
|
|
clock-names-option = "ife_dsp_clk";
|
|
clocks-option = <0x29 0x36>;
|
|
clock-rates-option = <0x2d4cae00>;
|
|
qcom,cam-cx-ipeak = <0x19b 0x03>;
|
|
status = "ok";
|
|
phandle = <0x380>;
|
|
};
|
|
|
|
qcom,csid1@acba000 {
|
|
cell-index = <0x01>;
|
|
compatible = "qcom,csid175_200";
|
|
reg-names = "csid";
|
|
reg = <0xacba000 0x1000>;
|
|
reg-cam-base = <0xba000>;
|
|
interrupt-names = "csid";
|
|
interrupts = <0x00 0x1d2 0x00>;
|
|
regulator-names = "camss\0ife1";
|
|
camss-supply = <0x1a6>;
|
|
ife1-supply = <0x1b0>;
|
|
clock-names = "ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk\0ife_axi_clk";
|
|
clocks = <0x29 0x3c 0x29 0x3b 0x29 0x1b 0x29 0x3a 0x29 0x39 0x29 0x38 0x29 0x37>;
|
|
clock-rates = <0x11e1a300 0x00 0x00 0x00 0x16a65700 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x1e65fb80 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x25f7d940 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x2d4cae00 0x00 0x00>;
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";
|
|
src-clock-name = "ife_csid_clk_src";
|
|
clock-control-debugfs = "true";
|
|
status = "ok";
|
|
phandle = <0x381>;
|
|
};
|
|
|
|
qcom,vfe1@acb6000 {
|
|
cell-index = <0x01>;
|
|
compatible = "qcom,vfe175_130";
|
|
reg-names = "ife\0cam_camnoc";
|
|
reg = <0xacb6000 0x5200 0xac42000 0x6000>;
|
|
reg-cam-base = <0xb6000 0x42000>;
|
|
interrupt-names = "ife";
|
|
interrupts = <0x00 0x1d3 0x00>;
|
|
regulator-names = "camss\0ife1";
|
|
camss-supply = <0x1a6>;
|
|
ife1-supply = <0x1b0>;
|
|
clock-names = "ife_clk_src\0ife_clk\0ife_axi_clk";
|
|
clocks = <0x29 0x39 0x29 0x38 0x29 0x37>;
|
|
clock-rates = <0x16a65700 0x00 0x00 0x1e65fb80 0x00 0x00 0x25f7d940 0x00 0x00 0x2d4cae00 0x00 0x00>;
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";
|
|
src-clock-name = "ife_clk_src";
|
|
clock-control-debugfs = "true";
|
|
clock-names-option = "ife_dsp_clk";
|
|
clocks-option = <0x29 0x3d>;
|
|
clock-rates-option = <0x2d4cae00>;
|
|
qcom,cam-cx-ipeak = <0x19b 0x03>;
|
|
status = "ok";
|
|
phandle = <0x382>;
|
|
};
|
|
|
|
qcom,csid-lite0@acc8000 {
|
|
cell-index = <0x02>;
|
|
compatible = "qcom,csid-lite175";
|
|
reg-names = "csid-lite";
|
|
reg = <0xacc8000 0x1000>;
|
|
reg-cam-base = <0xc8000>;
|
|
interrupt-names = "csid-lite";
|
|
interrupts = <0x00 0x1b6 0x00>;
|
|
regulator-names = "camss";
|
|
camss-supply = <0x1a6>;
|
|
clock-names = "ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk";
|
|
clocks = <0x29 0x42 0x29 0x41 0x29 0x1b 0x29 0x40 0x29 0x3f 0x29 0x3e>;
|
|
clock-rates = <0x11e1a300 0x00 0x00 0x00 0x1312d000 0x00 0x16e36000 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x17d78400 0x00 0x00 0x00 0x23c34600 0x00>;
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";
|
|
src-clock-name = "ife_csid_clk_src";
|
|
clock-control-debugfs = "true";
|
|
status = "ok";
|
|
phandle = <0x383>;
|
|
};
|
|
|
|
qcom,vfe-lite0@acc4000 {
|
|
cell-index = <0x02>;
|
|
compatible = "qcom,vfe-lite175";
|
|
reg-names = "ife-lite";
|
|
reg = <0xacc4000 0x4000>;
|
|
reg-cam-base = "\0\f@";
|
|
interrupt-names = "ife-lite";
|
|
interrupts = <0x00 0x1b2 0x00>;
|
|
regulator-names = "camss";
|
|
camss-supply = <0x1a6>;
|
|
clock-names = "ife_clk_src\0ife_clk";
|
|
clocks = <0x29 0x3f 0x29 0x3e>;
|
|
clock-rates = <0x1312d000 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x23c34600 0x00>;
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";
|
|
src-clock-name = "ife_clk_src";
|
|
clock-control-debugfs = "true";
|
|
status = "ok";
|
|
phandle = <0x384>;
|
|
};
|
|
|
|
qcom,cam-icp {
|
|
compatible = "qcom,cam-icp";
|
|
compat-hw-name = "qcom,a5\0qcom,ipe0\0qcom,ipe1\0qcom,bps";
|
|
num-a5 = <0x01>;
|
|
num-ipe = <0x02>;
|
|
num-bps = <0x01>;
|
|
icp_pc_en;
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,a5@ac00000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cam-a5";
|
|
reg = <0xac00000 0x6000 0xac10000 0x8000 0xac18000 0x3000>;
|
|
reg-names = "a5_qgic\0a5_sierra\0a5_csr";
|
|
reg-cam-base = <0x00 0x10000 0x18000>;
|
|
interrupts = <0x00 0x1cf 0x00>;
|
|
interrupt-names = "a5";
|
|
regulator-names = "camss-vdd";
|
|
camss-vdd-supply = <0x1a6>;
|
|
clock-names = "soc_fast_ahb\0icp_ahb_clk\0icp_clk_src\0icp_clk";
|
|
clocks = <0x29 0x28 0x29 0x2d 0x29 0x2f 0x29 0x2e>;
|
|
clock-rates = <0xbebc200 0x00 0x17d78400 0x00 0x17d78400 0x00 0x23c34600 0x00>;
|
|
clock-cntl-level = "svs\0turbo";
|
|
fw_name = "CAMERA_ICP.elf";
|
|
ubwc-cfg = <0x73 0x1cf>;
|
|
status = "ok";
|
|
phandle = <0x385>;
|
|
};
|
|
|
|
qcom,ipe0 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cam-ipe";
|
|
reg = <0xac87000 0x3000>;
|
|
reg-names = "ipe0_top";
|
|
reg-cam-base = "\0\bp";
|
|
regulator-names = "ipe0-vdd";
|
|
ipe0-vdd-supply = <0x1b1>;
|
|
clock-names = "ipe_0_ahb_clk\0ipe_0_areg_clk\0ipe_0_axi_clk\0ipe_0_clk_src\0ipe_0_clk";
|
|
src-clock-name = "ipe_0_clk_src";
|
|
clock-control-debugfs = "true";
|
|
clocks = <0x29 0x43 0x29 0x44 0x29 0x45 0x29 0x47 0x29 0x46>;
|
|
clock-rates = <0x00 0x00 0x00 0x1443fd00 0x00 0x00 0x00 0x00 0x19a14780 0x00 0x00 0x00 0x00 0x1efe9200 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600 0x00>;
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
qcom,cam-cx-ipeak = <0x19b 0x03>;
|
|
status = "ok";
|
|
phandle = <0x386>;
|
|
};
|
|
|
|
qcom,ipe1 {
|
|
cell-index = <0x01>;
|
|
compatible = "qcom,cam-ipe";
|
|
reg = <0xac91000 0x3000>;
|
|
reg-names = "ipe1_top";
|
|
reg-cam-base = <0x91000>;
|
|
regulator-names = "ipe1-vdd";
|
|
ipe1-vdd-supply = <0x1b2>;
|
|
clock-names = "ipe_1_ahb_clk\0ipe_1_areg_clk\0ipe_1_axi_clk\0ipe_1_clk_src\0ipe_1_clk";
|
|
src-clock-name = "ipe_1_clk_src";
|
|
clock-control-debugfs = "true";
|
|
clocks = <0x29 0x48 0x29 0x49 0x29 0x4a 0x29 0x47 0x29 0x4b>;
|
|
clock-rates = <0x00 0x00 0x00 0x1443fd00 0x00 0x00 0x00 0x00 0x19a14780 0x00 0x00 0x00 0x00 0x1efe9200 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600 0x00>;
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
qcom,cam-cx-ipeak = <0x19b 0x03>;
|
|
status = "ok";
|
|
phandle = <0x387>;
|
|
};
|
|
|
|
qcom,bps {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cam-bps";
|
|
reg = <0xac6f000 0x3000>;
|
|
reg-names = "bps_top";
|
|
reg-cam-base = <0x6f000>;
|
|
regulator-names = "bps-vdd";
|
|
bps-vdd-supply = <0x1b3>;
|
|
clock-names = "bps_ahb_clk\0bps_areg_clk\0bps_axi_clk\0bps_clk_src\0bps_clk";
|
|
src-clock-name = "bps_clk_src";
|
|
clock-control-debugfs = "true";
|
|
clocks = <0x29 0x0d 0x29 0x0e 0x29 0x0f 0x29 0x11 0x29 0x10>;
|
|
clock-rates = <0x00 0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600 0x00>;
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
qcom,cam-cx-ipeak = <0x19b 0x03>;
|
|
status = "ok";
|
|
phandle = <0x388>;
|
|
};
|
|
|
|
qcom,cam-jpeg {
|
|
compatible = "qcom,cam-jpeg";
|
|
compat-hw-name = "qcom,jpegenc\0qcom,jpegdma";
|
|
num-jpeg-enc = <0x01>;
|
|
num-jpeg-dma = <0x01>;
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,jpegenc@ac4e000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cam_jpeg_enc";
|
|
reg-names = "jpege_hw";
|
|
reg = <0xac4e000 0x4000>;
|
|
reg-cam-base = <0x4e000>;
|
|
interrupt-names = "jpeg";
|
|
interrupts = <0x00 0x1da 0x00>;
|
|
regulator-names = "camss-vdd";
|
|
camss-vdd-supply = <0x1a6>;
|
|
clock-names = "jpegenc_clk_src\0jpegenc_clk";
|
|
clocks = <0x29 0x4d 0x29 0x4c>;
|
|
clock-rates = <0x23c34600 0x00>;
|
|
src-clock-name = "jpegenc_clk_src";
|
|
clock-cntl-level = "nominal";
|
|
status = "ok";
|
|
phandle = <0x389>;
|
|
};
|
|
|
|
qcom,jpegdma@ac52000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cam_jpeg_dma";
|
|
reg-names = "jpegdma_hw";
|
|
reg = <0xac52000 0x4000>;
|
|
reg-cam-base = <0x52000>;
|
|
interrupt-names = "jpegdma";
|
|
interrupts = <0x00 0x1db 0x00>;
|
|
regulator-names = "camss-vdd";
|
|
camss-vdd-supply = <0x1a6>;
|
|
clock-names = "jpegdma_clk_src\0jpegdma_clk";
|
|
clocks = <0x29 0x4d 0x29 0x4c>;
|
|
clock-rates = <0x23c34600 0x00>;
|
|
src-clock-name = "jpegdma_clk_src";
|
|
clock-cntl-level = "nominal";
|
|
status = "ok";
|
|
phandle = <0x38a>;
|
|
};
|
|
|
|
qcom,cam-fd {
|
|
compatible = "qcom,cam-fd";
|
|
compat-hw-name = "qcom,fd";
|
|
num-fd = <0x01>;
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,fd@ac5a000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,fd501";
|
|
reg-names = "fd_core\0fd_wrapper";
|
|
reg = <0xac5a000 0x1000 0xac5b000 0x400>;
|
|
reg-cam-base = <0x5a000 0x5b000>;
|
|
interrupt-names = "fd";
|
|
interrupts = <0x00 0x1ce 0x00>;
|
|
regulator-names = "camss-vdd";
|
|
camss-vdd-supply = <0x1a6>;
|
|
clock-names = "fd_core_clk_src\0fd_core_clk\0fd_core_uar_clk";
|
|
clocks = <0x29 0x2a 0x29 0x29 0x29 0x2b>;
|
|
src-clock-name = "fd_core_clk_src";
|
|
clock-control-debugfs = "true";
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";
|
|
clock-rates = <0x16a65700 0x00 0x00 0x16e36000 0x00 0x00 0x1c9c3800 0x00 0x00 0x23c34600 0x00 0x00>;
|
|
status = "ok";
|
|
phandle = <0x38b>;
|
|
};
|
|
|
|
qcom,cam-lrme {
|
|
compatible = "qcom,cam-lrme";
|
|
arch-compat = "lrme";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,lrme@ac6b000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,lrme";
|
|
reg-names = "lrme";
|
|
reg = <0xac6b000 0xa00>;
|
|
reg-cam-base = <0x6b000>;
|
|
interrupt-names = "lrme";
|
|
interrupts = <0x00 0x1dc 0x00>;
|
|
regulator-names = "camss";
|
|
camss-supply = <0x1a6>;
|
|
clock-names = "lrme_clk_src\0lrme_clk";
|
|
clocks = <0x29 0x4f 0x29 0x4e>;
|
|
clock-rates = <0xe4e1c00 0x00 0x11e1a300 0x00 0x1312d000 0x00 0x17d78400 0x00>;
|
|
clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo";
|
|
src-clock-name = "lrme_clk_src";
|
|
status = "ok";
|
|
phandle = <0x38c>;
|
|
};
|
|
|
|
qcom,cam-cpas@ac40000 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cam-cpas";
|
|
label = "cpas";
|
|
arch-compat = "cpas_top";
|
|
status = "ok";
|
|
reg-names = "cam_cpas_top\0cam_camnoc";
|
|
reg = <0xac40000 0x1000 0xac42000 0x6000>;
|
|
reg-cam-base = <0x40000 0x42000>;
|
|
interrupt-names = "cpas_camnoc";
|
|
interrupts = <0x00 0x1cb 0x00>;
|
|
camnoc-axi-min-ib-bw = <0xb2d05e00>;
|
|
regulator-names = "camss-vdd";
|
|
camss-vdd-supply = <0x1a6>;
|
|
clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0slow_ahb_clk_src\0cpas_ahb_clk\0camnoc_axi_clk_src\0camnoc_axi_clk";
|
|
clocks = <0x27 0x0e 0x27 0x0f 0x27 0x10 0x29 0x5a 0x29 0x1a 0x29 0x13 0x29 0x12>;
|
|
src-clock-name = "camnoc_axi_clk_src";
|
|
clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x8f0d180 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0xe4e1c00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x1312d000 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x1c9c3800 0x00>;
|
|
clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
qcom,cam-cx-ipeak = <0x19b 0x03>;
|
|
control-camnoc-axi-clk;
|
|
camnoc-bus-width = <0x20>;
|
|
camnoc-axi-clk-bw-margin-perc = <0x14>;
|
|
qcom,msm-bus,name = "cam_ahb";
|
|
qcom,msm-bus,num-cases = <0x06>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x1d4c0 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x493e0 0x01 0x24d 0x00 0x493e0>;
|
|
vdd-corners = <0x01 0x11 0x31 0x41 0x81 0xc1 0x101 0x141 0x151 0x181 0x1a1>;
|
|
vdd-corner-ahb-mapping = "suspend\0suspend\0minsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo";
|
|
client-id-based;
|
|
client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0cci0\0cci1\0csid0\0csid1\0csid2\0iferdi0\0ifenrdi0\0iferdi1\0ifenrdi1\0iferdi2\0ifenrdi2\0ipe0\0ipe1\0cam-cdm-intf0\0cpas-cdm0\0bps0\0icp0\0jpeg-dma0\0jpeg-enc0\0fd0\0lrmecpas0";
|
|
client-axi-port-names = "cam_hf_0\0cam_hf_0\0cam_hf_0\0cam_hf_0\0cam_sf_0\0cam_sf_0\0cam_hf_0\0cam_hf_0\0cam_hf_0\0cam_hf_1\0cam_hf_0\0cam_hf_1\0cam_hf_0\0cam_hf_1\0cam_hf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_1\0cam_sf_0\0cam_sf_0\0cam_sf_0\0cam_sf_0";
|
|
client-bus-camnoc-based;
|
|
|
|
qcom,axi-port-list {
|
|
|
|
qcom,axi-port1 {
|
|
qcom,axi-port-name = "cam_hf_0";
|
|
ib-bw-voting-needed;
|
|
|
|
qcom,axi-port-mnoc {
|
|
qcom,msm-bus,name = "cam_hf_0_mnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x88 0x200 0x00 0x00 0x88 0x200 0x00 0x00>;
|
|
};
|
|
|
|
qcom,axi-port-camnoc {
|
|
qcom,msm-bus,name = "cam_hf_0_camnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x92 0x30a 0x00 0x00 0x92 0x30a 0x00 0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,axi-port2 {
|
|
qcom,axi-port-name = "cam_hf_1";
|
|
ib-bw-voting-needed;
|
|
|
|
qcom,axi-port-mnoc {
|
|
qcom,msm-bus,name = "cam_hf_1_mnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0xac 0x200 0x00 0x00 0xac 0x200 0x00 0x00>;
|
|
};
|
|
|
|
qcom,axi-port-camnoc {
|
|
qcom,msm-bus,name = "cam_hf_1_camnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0xb2 0x30a 0x00 0x00 0xb2 0x30a 0x00 0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,axi-port3 {
|
|
qcom,axi-port-name = "cam_sf_0";
|
|
|
|
qcom,axi-port-mnoc {
|
|
qcom,msm-bus,name = "cam_sf_0_mnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x89 0x200 0x00 0x00 0x89 0x200 0x00 0x00>;
|
|
};
|
|
|
|
qcom,axi-port-camnoc {
|
|
qcom,msm-bus,name = "cam_sf_0_camnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x94 0x30a 0x00 0x00 0x94 0x30a 0x00 0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,axi-port4 {
|
|
qcom,axi-port-name = "cam_sf_1";
|
|
|
|
qcom,axi-port-mnoc {
|
|
qcom,msm-bus,name = "cam_sf_1_mnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0xab 0x200 0x00 0x00 0xab 0x200 0x00 0x00>;
|
|
};
|
|
|
|
qcom,axi-port-camnoc {
|
|
qcom,msm-bus,name = "cam_sf_1_camnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0xb3 0x30a 0x00 0x00 0xb3 0x30a 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_2_out {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-2-out";
|
|
qcom,smem-states = <0x1b4 0x00>;
|
|
qcom,smem-state-names = "rdbg-smp2p-out";
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_2_in {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-2-in";
|
|
interrupts-extended = <0x1b5 0x00 0x00>;
|
|
interrupt-names = "rdbg-smp2p-in";
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_5_out {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-5-out";
|
|
qcom,smem-states = <0x1b6 0x00>;
|
|
qcom,smem-state-names = "rdbg-smp2p-out";
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_5_in {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-5-in";
|
|
interrupts-extended = <0x1b7 0x00 0x00>;
|
|
interrupt-names = "rdbg-smp2p-in";
|
|
};
|
|
|
|
qcom,smp2p_interrupt_qvrexternal_5_out {
|
|
compatible = "qcom,smp2p-interrupt-qvrexternal-5-out";
|
|
qcom,smem-states = <0x1b8 0x00>;
|
|
qcom,smem-state-names = "qvrexternal-smp2p-out";
|
|
};
|
|
|
|
qcom,ion {
|
|
compatible = "qcom,msm-ion";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,ion-heap@25 {
|
|
reg = <0x19>;
|
|
qcom,ion-heap-type = "SYSTEM";
|
|
phandle = <0x38d>;
|
|
};
|
|
|
|
qcom,ion-heap@27 {
|
|
reg = <0x1b>;
|
|
memory-region = <0x90>;
|
|
qcom,ion-heap-type = "DMA";
|
|
};
|
|
|
|
qcom,ion-heap@19 {
|
|
reg = <0x13>;
|
|
memory-region = <0x1b9>;
|
|
qcom,ion-heap-type = "DMA";
|
|
};
|
|
|
|
qcom,ion-heap@13 {
|
|
reg = <0x0d>;
|
|
memory-region = <0x1ba>;
|
|
qcom,ion-heap-type = "DMA";
|
|
};
|
|
|
|
qcom,ion-heap@10 {
|
|
reg = <0x0a>;
|
|
memory-region = <0x1bb>;
|
|
qcom,ion-heap-type = "HYP_CMA";
|
|
};
|
|
|
|
qcom,ion-heap@14 {
|
|
reg = <0x0e>;
|
|
qcom,ion-heap-type = "SECURE_CARVEOUT";
|
|
|
|
cdsp {
|
|
memory-region = <0x1bc>;
|
|
token = <0x20000000>;
|
|
};
|
|
};
|
|
|
|
qcom,ion-heap@9 {
|
|
reg = <0x09>;
|
|
qcom,ion-heap-type = "SYSTEM_SECURE";
|
|
};
|
|
|
|
qcom,ion-heap@30 {
|
|
reg = <0x1e>;
|
|
memory-region = <0x543>;
|
|
qcom,ion-heap-type = "RBIN";
|
|
};
|
|
};
|
|
|
|
arm,smmu-kgsl@5040000 {
|
|
status = "ok";
|
|
compatible = "qcom,smmu-v2";
|
|
reg = <0x5040000 0x10000>;
|
|
#iommu-cells = <0x01>;
|
|
qcom,dynamic;
|
|
qcom,use-3-lvl-tables;
|
|
qcom,disable-atos;
|
|
#global-interrupts = <0x02>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <0x1bd>;
|
|
interrupts = <0x00 0xe5 0x04 0x00 0xe7 0x04 0x00 0x16c 0x04 0x00 0x16d 0x04 0x00 0x16e 0x04 0x00 0x16f 0x04 0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04 0x00 0x173 0x04>;
|
|
clock-names = "gcc_gpu_memnoc_gfx_clk";
|
|
clocks = <0x27 0x2b>;
|
|
attach-impl-defs = <0x6000 0x2378 0x6060 0x1055 0x678c 0x08 0x6794 0x28 0x6800 0x06 0x6900 0x3ff 0x6924 0x204 0x6928 0x11000 0x6930 0x800 0x6960 0xffffffff 0x6b64 0x1a5551 0x6b68 0x9a82a382>;
|
|
phandle = <0x1c5>;
|
|
};
|
|
|
|
apps-smmu@0x15000000 {
|
|
compatible = "qcom,qsmmu-v500";
|
|
reg = <0x15000000 0x100000 0x15182000 0x20>;
|
|
reg-names = "base\0tcu-base";
|
|
#iommu-cells = <0x02>;
|
|
qcom,skip-init;
|
|
qcom,use-3-lvl-tables;
|
|
#global-interrupts = <0x01>;
|
|
#size-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
ranges;
|
|
interrupts = <0x00 0x41 0x04 0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04 0x00 0x18e 0x04 0x00 0x18f 0x04 0x00 0x190 0x04 0x00 0x191 0x04 0x00 0x192 0x04 0x00 0x193 0x04 0x00 0x194 0x04 0x00 0x195 0x04 0x00 0x196 0x04 0x00 0x197 0x04 0x00 0x198 0x04 0x00 0x199 0x04 0x00 0x19a 0x04 0x00 0x19b 0x04 0x00 0x19c 0x04 0x00 0x19d 0x04>;
|
|
qcom,msm-bus,name = "apps_smmu";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>;
|
|
qcom,actlr = <0x800 0x7ff 0x103 0x1000 0x3ff 0x103 0x1460 0x1f 0x303>;
|
|
phandle = <0x30>;
|
|
|
|
anoc_1_tbu@0x15185000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x15185000 0x1000 0x15182200 0x08>;
|
|
reg-names = "base\0status-reg";
|
|
qcom,stream-id-range = <0x00 0x400>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <0x1be>;
|
|
qcom,msm-bus,name = "apps_smmu";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>;
|
|
phandle = <0x38e>;
|
|
};
|
|
|
|
anoc_2_tbu@0x15189000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x15189000 0x1000 0x15182208 0x08>;
|
|
reg-names = "base\0status-reg";
|
|
qcom,stream-id-range = <0x400 0x400>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <0x1bf>;
|
|
qcom,msm-bus,name = "apps_smmu";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>;
|
|
phandle = <0x38f>;
|
|
};
|
|
|
|
mnoc_hf_0_tbu@0x1518d000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x1518d000 0x1000 0x15182210 0x08>;
|
|
reg-names = "base\0status-reg";
|
|
qcom,stream-id-range = <0x800 0x400>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <0x1c0>;
|
|
qcom,msm-bus,name = "mnoc_hf_0_tbu";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8>;
|
|
phandle = <0x390>;
|
|
};
|
|
|
|
mnoc_hf_1_tbu@0x15191000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x15191000 0x1000 0x15182218 0x08>;
|
|
reg-names = "base\0status-reg";
|
|
qcom,stream-id-range = <0xc00 0x400>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <0x1c1>;
|
|
qcom,msm-bus,name = "mnoc_hf_1_tbu";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8>;
|
|
phandle = <0x391>;
|
|
};
|
|
|
|
mnoc_sf_0_tbu@0x15195000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x15195000 0x1000 0x15182220 0x08>;
|
|
reg-names = "base\0status-reg";
|
|
qcom,stream-id-range = <0x1000 0x400>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <0x1c2>;
|
|
qcom,msm-bus,name = "mnoc_sf_0_tbu";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x89 0x304 0x00 0x00 0x89 0x304 0x00 0x3e8>;
|
|
phandle = <0x392>;
|
|
};
|
|
|
|
compute_dsp_0_tbu@0x15199000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x15199000 0x1000 0x15182228 0x08>;
|
|
reg-names = "base\0status-reg";
|
|
qcom,stream-id-range = <0x1400 0x400>;
|
|
qcom,msm-bus,name = "apps_smmu";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x9a 0x275c 0x00 0x00 0x9a 0x275c 0x00 0x3e8>;
|
|
phandle = <0x393>;
|
|
};
|
|
|
|
adsp_tbu@0x1519d000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x1519d000 0x1000 0x15182230 0x08>;
|
|
reg-names = "base\0status-reg";
|
|
qcom,stream-id-range = <0x1800 0x400>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <0x1c3>;
|
|
qcom,msm-bus,name = "apps_smmu";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>;
|
|
phandle = <0x394>;
|
|
};
|
|
|
|
anoc_1_pcie_tbu@0x151a1000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x151a1000 0x1000 0x15182238 0x08>;
|
|
reg-names = "base\0status-reg";
|
|
qcom,stream-id-range = <0x1c00 0x400>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <0x1c4>;
|
|
clock-names = "gcc_aggre_noc_pcie_tbu_clk";
|
|
clocks = <0x27 0x08>;
|
|
qcom,msm-bus,name = "apps_smmu";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>;
|
|
phandle = <0x395>;
|
|
};
|
|
};
|
|
|
|
kgsl_iommu_test_device {
|
|
compatible = "iommu-debug-test";
|
|
iommus = <0x1c5 0x07>;
|
|
};
|
|
|
|
apps_iommu_test_device {
|
|
compatible = "iommu-debug-test";
|
|
iommus = <0x30 0x21 0x00>;
|
|
};
|
|
|
|
apps_iommu_coherent_test_device {
|
|
compatible = "iommu-debug-test";
|
|
iommus = <0x30 0x23 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,lpm-levels {
|
|
compatible = "qcom,lpm-levels";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,pm-cluster@0 {
|
|
reg = <0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
label = "L3";
|
|
qcom,psci-mode-shift = <0x04>;
|
|
qcom,psci-mode-mask = <0xfff>;
|
|
qcom,clstr-tmr-add = <0x3e8>;
|
|
|
|
qcom,pm-cluster-level@0 {
|
|
reg = <0x00>;
|
|
label = "l3-wfi";
|
|
qcom,psci-mode = <0x01>;
|
|
qcom,entry-latency-us = <0x294>;
|
|
qcom,exit-latency-us = <0x258>;
|
|
qcom,min-residency-us = <0x4ec>;
|
|
};
|
|
|
|
qcom,pm-cluster-level@1 {
|
|
reg = <0x01>;
|
|
label = "l3-pc";
|
|
qcom,psci-mode = <0x04>;
|
|
qcom,entry-latency-us = <0xac0>;
|
|
qcom,exit-latency-us = <0xbe8>;
|
|
qcom,min-residency-us = <0x17e6>;
|
|
qcom,min-child-idx = <0x02>;
|
|
qcom,is-reset;
|
|
};
|
|
|
|
qcom,pm-cluster-level@2 {
|
|
reg = <0x02>;
|
|
label = "cx-off";
|
|
qcom,psci-mode = <0x224>;
|
|
qcom,entry-latency-us = <0xe36>;
|
|
qcom,exit-latency-us = <0x11d2>;
|
|
qcom,min-residency-us = <0x2113>;
|
|
qcom,min-child-idx = <0x02>;
|
|
qcom,is-reset;
|
|
qcom,notify-rpm;
|
|
};
|
|
|
|
qcom,pm-cluster-level@3 {
|
|
reg = <0x03>;
|
|
label = "llcc-off";
|
|
qcom,psci-mode = <0xc24>;
|
|
qcom,entry-latency-us = <0xcbf>;
|
|
qcom,exit-latency-us = <0x19a2>;
|
|
qcom,min-residency-us = <0x2662>;
|
|
qcom,min-child-idx = <0x02>;
|
|
qcom,is-reset;
|
|
qcom,notify-rpm;
|
|
};
|
|
|
|
qcom,pm-cpu@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
qcom,psci-mode-shift = <0x00>;
|
|
qcom,psci-mode-mask = <0x0f>;
|
|
qcom,ref-stddev = <0x1f4>;
|
|
qcom,tmr-add = <0x3e8>;
|
|
qcom,ref-premature-cnt = <0x01>;
|
|
qcom,disable-ipi-prediction;
|
|
qcom,cpu = <0x11 0x12 0x13 0x14 0x15 0x16>;
|
|
|
|
qcom,pm-cpu-level@0 {
|
|
reg = <0x00>;
|
|
label = "wfi";
|
|
qcom,psci-cpu-mode = <0x01>;
|
|
qcom,entry-latency-us = <0x3d>;
|
|
qcom,exit-latency-us = <0x3c>;
|
|
qcom,min-residency-us = <0x79>;
|
|
};
|
|
|
|
qcom,pm-cpu-level@1 {
|
|
reg = <0x01>;
|
|
label = "pc";
|
|
qcom,psci-cpu-mode = <0x03>;
|
|
qcom,entry-latency-us = <0x225>;
|
|
qcom,exit-latency-us = <0x385>;
|
|
qcom,min-residency-us = <0x6ee>;
|
|
qcom,is-reset;
|
|
qcom,use-broadcast-timer;
|
|
};
|
|
|
|
qcom,pm-cpu-level@2 {
|
|
reg = <0x02>;
|
|
label = "rail-pc";
|
|
qcom,psci-cpu-mode = <0x04>;
|
|
qcom,entry-latency-us = <0x2be>;
|
|
qcom,exit-latency-us = <0x393>;
|
|
qcom,min-residency-us = <0xfa1>;
|
|
qcom,is-reset;
|
|
qcom,use-broadcast-timer;
|
|
};
|
|
};
|
|
|
|
qcom,pm-cpu@1 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
qcom,psci-mode-shift = <0x00>;
|
|
qcom,psci-mode-mask = <0x0f>;
|
|
qcom,ref-stddev = <0x64>;
|
|
qcom,tmr-add = <0x64>;
|
|
qcom,ref-premature-cnt = <0x03>;
|
|
qcom,disable-ipi-prediction;
|
|
qcom,cpu = <0x17 0x18>;
|
|
|
|
qcom,pm-cpu-level@0 {
|
|
reg = <0x00>;
|
|
label = "wfi";
|
|
qcom,psci-cpu-mode = <0x01>;
|
|
qcom,entry-latency-us = <0x37>;
|
|
qcom,exit-latency-us = <0x42>;
|
|
qcom,min-residency-us = <0x79>;
|
|
};
|
|
|
|
qcom,pm-cpu-level@1 {
|
|
reg = <0x01>;
|
|
label = "pc";
|
|
qcom,psci-cpu-mode = <0x03>;
|
|
qcom,entry-latency-us = <0x20b>;
|
|
qcom,exit-latency-us = <0x4dc>;
|
|
qcom,min-residency-us = <0x89f>;
|
|
qcom,is-reset;
|
|
qcom,use-broadcast-timer;
|
|
};
|
|
|
|
qcom,pm-cpu-level@2 {
|
|
reg = <0x02>;
|
|
label = "rail-pc";
|
|
qcom,psci-cpu-mode = <0x04>;
|
|
qcom,entry-latency-us = <0x20e>;
|
|
qcom,exit-latency-us = <0x73e>;
|
|
qcom,min-residency-us = <0x15b3>;
|
|
qcom,is-reset;
|
|
qcom,use-broadcast-timer;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,rpm-stats@c300000 {
|
|
compatible = "qcom,rpm-stats";
|
|
reg = <0xc300000 0x1000 0xc3f0004 0x04>;
|
|
reg-names = "phys_addr_base\0offset_addr";
|
|
qcom,num-records = <0x03>;
|
|
};
|
|
|
|
qcom,rpmh-master-stats@b221200 {
|
|
compatible = "qcom,rpmh-master-stats-v1";
|
|
reg = <0xb221200 0x60>;
|
|
};
|
|
|
|
pinctrl@3400000 {
|
|
compatible = "qcom,sdmmagpie-pinctrl";
|
|
reg = <0x3400000 0xdc2000 0x17c000f0 0x60>;
|
|
reg-names = "pinctrl\0spi_cfg";
|
|
interrupts = <0x00 0xd0 0x00>;
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x16c>;
|
|
|
|
ufs_dev_reset_assert {
|
|
phandle = <0x93>;
|
|
|
|
config {
|
|
pins = "ufs_reset";
|
|
bias-pull-down;
|
|
drive-strength = <0x08>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
ufs_dev_reset_deassert {
|
|
phandle = <0x94>;
|
|
|
|
config {
|
|
pins = "ufs_reset";
|
|
bias-pull-down;
|
|
drive-strength = <0x08>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_pins {
|
|
phandle = <0x5b6>;
|
|
|
|
qupv3_se0_i2c_active {
|
|
phandle = <0x15e>;
|
|
|
|
mux {
|
|
pins = "gpio49\0gpio50";
|
|
function = "qup00";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49\0gpio50";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_sleep {
|
|
phandle = <0x15f>;
|
|
|
|
mux {
|
|
pins = "gpio49\0gpio50";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49\0gpio50";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_amp_i2c_active {
|
|
phandle = <0x534>;
|
|
|
|
mux {
|
|
pins = "gpio49\0gpio50";
|
|
function = "qup00";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49\0gpio50";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_amp_i2c_sleep {
|
|
phandle = <0x535>;
|
|
|
|
mux {
|
|
pins = "gpio49\0gpio50";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49\0gpio50";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_pins {
|
|
phandle = <0x397>;
|
|
|
|
qupv3_se0_spi_active {
|
|
phandle = <0x170>;
|
|
|
|
mux {
|
|
pins = "gpio49\0gpio50\0gpio51\0gpio52";
|
|
function = "qup00";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49\0gpio50\0gpio51\0gpio52";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_sleep {
|
|
phandle = <0x171>;
|
|
|
|
mux {
|
|
pins = "gpio49\0gpio50\0gpio51\0gpio52";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49\0gpio50\0gpio51\0gpio52";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i2c_pins {
|
|
phandle = <0x398>;
|
|
|
|
qupv3_se1_i2c_active {
|
|
phandle = <0x161>;
|
|
|
|
mux {
|
|
pins = "gpio0\0gpio1";
|
|
function = "qup01";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0\0gpio1";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i2c_sleep {
|
|
phandle = <0x162>;
|
|
|
|
mux {
|
|
pins = "gpio0\0gpio1";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0\0gpio1";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_pins {
|
|
phandle = <0x399>;
|
|
|
|
qupv3_se1_spi_active {
|
|
phandle = <0x172>;
|
|
|
|
mux {
|
|
pins = "gpio0\0gpio1\0gpio2\0gpio3";
|
|
function = "qup01";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0\0gpio1\0gpio2\0gpio3";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_sleep {
|
|
phandle = <0x173>;
|
|
|
|
mux {
|
|
pins = "gpio0\0gpio1\0gpio2\0gpio3";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0\0gpio1\0gpio2\0gpio3";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_pins {
|
|
phandle = <0x39a>;
|
|
|
|
qupv3_se2_i2c_active {
|
|
phandle = <0x163>;
|
|
|
|
mux {
|
|
pins = "gpio34\0gpio35";
|
|
function = "qup02";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio34\0gpio35";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_sleep {
|
|
phandle = <0x164>;
|
|
|
|
mux {
|
|
pins = "gpio34\0gpio35";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio34\0gpio35";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
nfc {
|
|
|
|
nfc_int_active {
|
|
phandle = <0x39b>;
|
|
|
|
mux {
|
|
pins = "gpio37";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio37";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
nfc_int_suspend {
|
|
phandle = <0x39c>;
|
|
|
|
mux {
|
|
pins = "gpio37";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio37";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
nfc_enable_active {
|
|
phandle = <0x39d>;
|
|
|
|
mux {
|
|
pins = "gpio12\0gpio36";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12\0gpio36";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
nfc_enable_suspend {
|
|
phandle = <0x39e>;
|
|
|
|
mux {
|
|
pins = "gpio12\0gpio36";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12\0gpio36";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
nfc_clk_req_active {
|
|
phandle = <0x39f>;
|
|
|
|
mux {
|
|
pins = "gpio31";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio31";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
nfc_clk_req_suspend {
|
|
phandle = <0x3a0>;
|
|
|
|
mux {
|
|
pins = "gpio31";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio31";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_pins {
|
|
phandle = <0x3a1>;
|
|
|
|
qupv3_se3_i2c_active {
|
|
phandle = <0x165>;
|
|
|
|
mux {
|
|
pins = "gpio38\0gpio39";
|
|
function = "qup03";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio38\0gpio39";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_sleep {
|
|
phandle = <0x166>;
|
|
|
|
mux {
|
|
pins = "gpio38\0gpio39";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio38\0gpio39";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_4uart_pins {
|
|
phandle = <0x3a2>;
|
|
|
|
qupv3_se3_ctsrx {
|
|
phandle = <0x169>;
|
|
|
|
mux {
|
|
pins = "gpio38\0gpio41";
|
|
function = "qup03";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio38\0gpio41";
|
|
drive-strength = <0x02>;
|
|
bias-no-pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_rts {
|
|
phandle = <0x16a>;
|
|
|
|
mux {
|
|
pins = "gpio39";
|
|
function = "qup03";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio39";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_tx {
|
|
phandle = <0x16b>;
|
|
|
|
mux {
|
|
pins = "gpio40";
|
|
function = "qup03";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_pins {
|
|
phandle = <0x3a3>;
|
|
|
|
qupv3_se3_spi_active {
|
|
phandle = <0x174>;
|
|
|
|
mux {
|
|
pins = "gpio38\0gpio39\0gpio40\0gpio41";
|
|
function = "qup03";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio38\0gpio39\0gpio40\0gpio41";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_sleep {
|
|
phandle = <0x175>;
|
|
|
|
mux {
|
|
pins = "gpio38\0gpio39\0gpio40\0gpio41";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio38\0gpio39\0gpio40\0gpio41";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
fpc_reset_int {
|
|
|
|
reset_low {
|
|
phandle = <0x3a4>;
|
|
|
|
mux {
|
|
pins = "gpio91";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio91";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
reset_high {
|
|
phandle = <0x3a5>;
|
|
|
|
mux {
|
|
pins = "gpio91";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio91";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
int_low {
|
|
phandle = <0x3a6>;
|
|
|
|
mux {
|
|
pins = "gpio90";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio90";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i2c_pins {
|
|
phandle = <0x3a7>;
|
|
|
|
qupv3_se4_i2c_active {
|
|
phandle = <0x167>;
|
|
|
|
mux {
|
|
pins = "gpio53\0gpio54";
|
|
function = "qup04";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53\0gpio54";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i2c_sleep {
|
|
phandle = <0x168>;
|
|
|
|
mux {
|
|
pins = "gpio53\0gpio54";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53\0gpio54";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
smb1390_i2c {
|
|
phandle = <0x3a8>;
|
|
|
|
smb1390_i2c_active {
|
|
phandle = <0x3a9>;
|
|
|
|
mux {
|
|
pins = "gpio43\0gpio42";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio43\0gpio42";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se4_4uart_pins {
|
|
phandle = <0x3aa>;
|
|
|
|
qupv3_se4_ctsrx {
|
|
phandle = <0x16d>;
|
|
|
|
mux {
|
|
pins = "gpio53\0gpio56";
|
|
function = "qup04";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53\0gpio56";
|
|
drive-strength = <0x02>;
|
|
bias-no-pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_rts {
|
|
phandle = <0x16e>;
|
|
|
|
mux {
|
|
pins = "gpio54";
|
|
function = "qup04";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio54";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_tx {
|
|
phandle = <0x16f>;
|
|
|
|
mux {
|
|
pins = "gpio55";
|
|
function = "qup04";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio55";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_pins {
|
|
phandle = <0x3ab>;
|
|
|
|
qupv3_se4_spi_active {
|
|
phandle = <0x176>;
|
|
|
|
mux {
|
|
pins = "gpio53\0gpio54\0gpio55\0gpio56";
|
|
function = "qup04";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53\0gpio54\0gpio55\0gpio56";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_sleep {
|
|
phandle = <0x177>;
|
|
|
|
mux {
|
|
pins = "gpio53\0gpio54\0gpio55\0gpio56";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53\0gpio54\0gpio55\0gpio56";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_pins {
|
|
phandle = <0x3ac>;
|
|
|
|
qupv3_se6_i2c_active {
|
|
phandle = <0x17c>;
|
|
|
|
mux {
|
|
pins = "gpio59\0gpio60";
|
|
function = "qup10";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio59\0gpio60";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_sleep {
|
|
phandle = <0x17d>;
|
|
|
|
mux {
|
|
pins = "gpio59\0gpio60";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio59\0gpio60";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_pins {
|
|
phandle = <0x3ad>;
|
|
|
|
qupv3_se6_spi_active {
|
|
phandle = <0x18f>;
|
|
|
|
mux {
|
|
pins = "gpio59\0gpio60\0gpio61\0gpio62";
|
|
function = "qup10";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio59\0gpio60\0gpio61\0gpio62";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_sleep {
|
|
phandle = <0x190>;
|
|
|
|
mux {
|
|
pins = "gpio59\0gpio60\0gpio61\0gpio62";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio59\0gpio60\0gpio61\0gpio62";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_pins {
|
|
phandle = <0x3ae>;
|
|
|
|
qupv3_se7_i2c_active {
|
|
phandle = <0x17e>;
|
|
|
|
mux {
|
|
pins = "gpio6\0gpio7";
|
|
function = "qup11";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6\0gpio7";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_sleep {
|
|
phandle = <0x17f>;
|
|
|
|
mux {
|
|
pins = "gpio6\0gpio7";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6\0gpio7";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_pins {
|
|
phandle = <0x3af>;
|
|
|
|
qupv3_se7_spi_active {
|
|
phandle = <0x191>;
|
|
|
|
mux {
|
|
pins = "gpio6\0gpio7\0gpio8\0gpio9";
|
|
function = "qup11";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6\0gpio7\0gpio8\0gpio9";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_sleep {
|
|
phandle = <0x192>;
|
|
|
|
mux {
|
|
pins = "gpio6\0gpio7\0gpio8\0gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6\0gpio7\0gpio8\0gpio9";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_pins {
|
|
phandle = <0x3b0>;
|
|
|
|
qupv3_se8_i2c_active {
|
|
phandle = <0x180>;
|
|
|
|
mux {
|
|
pins = "gpio42\0gpio43";
|
|
function = "qup12";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42\0gpio43";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_sleep {
|
|
phandle = <0x181>;
|
|
|
|
mux {
|
|
pins = "gpio42\0gpio43";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42\0gpio43";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_pins {
|
|
phandle = <0x5b3>;
|
|
|
|
qupv3_se8_2uart_active {
|
|
phandle = <0x178>;
|
|
|
|
mux {
|
|
pins = "gpio44\0gpio45";
|
|
function = "qup12";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44\0gpio45";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_sleep {
|
|
phandle = <0x179>;
|
|
|
|
mux {
|
|
pins = "gpio44\0gpio45";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44\0gpio45";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_tx_active {
|
|
phandle = <0x54b>;
|
|
|
|
mux {
|
|
pins = "gpio44";
|
|
function = "qup12";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_rx_active {
|
|
phandle = <0x54c>;
|
|
|
|
mux {
|
|
pins = "gpio45";
|
|
function = "qup12";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio45";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_tx_sleep {
|
|
phandle = <0x54d>;
|
|
|
|
mux {
|
|
pins = "gpio44";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
input-enable;
|
|
input-high;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_rx_sleep {
|
|
phandle = <0x54e>;
|
|
|
|
mux {
|
|
pins = "gpio45";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio45";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_pins {
|
|
phandle = <0x3b2>;
|
|
|
|
qupv3_se8_spi_active {
|
|
phandle = <0x193>;
|
|
|
|
mux {
|
|
pins = "gpio42\0gpio43\0gpio44\0gpio45";
|
|
function = "qup12";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42\0gpio43\0gpio44\0gpio45";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_sleep {
|
|
phandle = <0x194>;
|
|
|
|
mux {
|
|
pins = "gpio42\0gpio43\0gpio44\0gpio45";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42\0gpio43\0gpio44\0gpio45";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_pins {
|
|
phandle = <0x3b3>;
|
|
|
|
qupv3_se9_i2c_active {
|
|
phandle = <0x182>;
|
|
|
|
mux {
|
|
pins = "gpio46\0gpio47";
|
|
function = "qup13";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio46\0gpio47";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_sleep {
|
|
phandle = <0x183>;
|
|
|
|
mux {
|
|
pins = "gpio46\0gpio47";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6\0gpio7";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_pins {
|
|
phandle = <0x3b4>;
|
|
|
|
qupv3_se10_i2c_active {
|
|
phandle = <0x185>;
|
|
|
|
mux {
|
|
pins = "gpio110\0gpio111";
|
|
function = "qup14";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110\0gpio111";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_sleep {
|
|
phandle = <0x186>;
|
|
|
|
mux {
|
|
pins = "gpio110\0gpio111";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110\0gpio111";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_4uart_pins {
|
|
phandle = <0x3b5>;
|
|
|
|
qupv3_se10_ctsrx {
|
|
phandle = <0x189>;
|
|
|
|
mux {
|
|
pins = "gpio110\0gpio113";
|
|
function = "qup14";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110\0gpio113";
|
|
drive-strength = <0x02>;
|
|
bias-no-pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_rts {
|
|
phandle = <0x18a>;
|
|
|
|
mux {
|
|
pins = "gpio111";
|
|
function = "qup14";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio111";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_tx {
|
|
phandle = <0x18b>;
|
|
|
|
mux {
|
|
pins = "gpio112";
|
|
function = "qup14";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio112";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_pins {
|
|
phandle = <0x3b6>;
|
|
|
|
qupv3_se10_spi_active {
|
|
phandle = <0x195>;
|
|
|
|
mux {
|
|
pins = "gpio110\0gpio111\0gpio112\0gpio113";
|
|
function = "qup14";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110\0gpio111\0gpio112\0gpio113";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_sleep {
|
|
phandle = <0x196>;
|
|
|
|
mux {
|
|
pins = "gpio110\0gpio111\0gpio112\0gpio113";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110\0gpio111\0gpio112\0gpio113";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_pins {
|
|
phandle = <0x3b7>;
|
|
|
|
qupv3_se11_i2c_active {
|
|
phandle = <0x187>;
|
|
|
|
mux {
|
|
pins = "gpio101\0gpio102";
|
|
function = "qup15";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101\0gpio102";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_sleep {
|
|
phandle = <0x188>;
|
|
|
|
mux {
|
|
pins = "gpio101\0gpio102";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101\0gpio102";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
input-enable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_4uart_pins {
|
|
phandle = <0x3b8>;
|
|
|
|
qupv3_se11_ctsrx {
|
|
phandle = <0x18c>;
|
|
|
|
mux {
|
|
pins = "gpio101\0gpio92";
|
|
function = "qup15";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101\0gpio92";
|
|
drive-strength = <0x02>;
|
|
bias-no-pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_rts {
|
|
phandle = <0x18d>;
|
|
|
|
mux {
|
|
pins = "gpio102";
|
|
function = "qup15";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio102";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_tx {
|
|
phandle = <0x18e>;
|
|
|
|
mux {
|
|
pins = "gpio103";
|
|
function = "qup15";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio103";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_pins {
|
|
phandle = <0x3b9>;
|
|
|
|
qupv3_se11_spi_active {
|
|
phandle = <0x197>;
|
|
|
|
mux {
|
|
pins = "gpio101\0gpio102\0gpio103\0gpio92";
|
|
function = "qup15";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101\0gpio102\0gpio103\0gpio92";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_sleep {
|
|
phandle = <0x198>;
|
|
|
|
mux {
|
|
pins = "gpio101\0gpio102\0gpio103\0gpio92";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101\0gpio102\0gpio103\0gpio92";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_sde_te {
|
|
|
|
sde_te_active {
|
|
phandle = <0x4e1>;
|
|
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sde_te_suspend {
|
|
phandle = <0x4e6>;
|
|
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sde_te1_active {
|
|
phandle = <0x3bc>;
|
|
|
|
mux {
|
|
pins = "gpio11";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sde_te1_suspend {
|
|
phandle = <0x3bd>;
|
|
|
|
mux {
|
|
pins = "gpio11";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
sde_dp_aux_active {
|
|
phandle = <0x3be>;
|
|
|
|
mux {
|
|
pins = "gpio42\0gpio33";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42\0gpio33";
|
|
bias-disable = <0x00>;
|
|
drive-strength = <0x08>;
|
|
};
|
|
};
|
|
|
|
sde_dp_aux_suspend {
|
|
phandle = <0x3bf>;
|
|
|
|
mux {
|
|
pins = "gpio42\0gpio33";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42\0gpio33";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sde_dp_usbplug_cc_active {
|
|
phandle = <0x1a4>;
|
|
|
|
mux {
|
|
pins = "gpio104";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio104";
|
|
bias-disable;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
sde_dp_usbplug_cc_suspend {
|
|
phandle = <0x1a5>;
|
|
|
|
mux {
|
|
pins = "gpio104";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio104";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
wsa_swr_clk_pin {
|
|
|
|
wsa_swr_clk_sleep {
|
|
phandle = <0x3c0>;
|
|
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "wsa_clk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <0x02>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
wsa_swr_clk_active {
|
|
phandle = <0x3c1>;
|
|
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "wsa_clk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <0x02>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
};
|
|
|
|
wsa_swr_data_pin {
|
|
|
|
wsa_swr_data_sleep {
|
|
phandle = <0x3c2>;
|
|
|
|
mux {
|
|
pins = "gpio50";
|
|
function = "wsa_data";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio50";
|
|
drive-strength = <0x04>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
wsa_swr_data_active {
|
|
phandle = <0x3c3>;
|
|
|
|
mux {
|
|
pins = "gpio50";
|
|
function = "wsa_data";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio50";
|
|
drive-strength = <0x04>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
};
|
|
|
|
spkr_1_sd_n {
|
|
|
|
spkr_1_sd_n_sleep {
|
|
phandle = <0x3c4>;
|
|
|
|
mux {
|
|
pins = "gpio51";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio51";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
spkr_1_sd_n_active {
|
|
phandle = <0x3c5>;
|
|
|
|
mux {
|
|
pins = "gpio51";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio51";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
spkr_2_sd_n {
|
|
|
|
spkr_2_sd_n_sleep {
|
|
phandle = <0x3c6>;
|
|
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
spkr_2_sd_n_active {
|
|
phandle = <0x3c7>;
|
|
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
wcd9xxx_intr {
|
|
|
|
wcd_intr_default {
|
|
phandle = <0x3c8>;
|
|
|
|
mux {
|
|
pins = "gpio58";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio58";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
};
|
|
|
|
fsa_usbc_ana_en_n@42 {
|
|
|
|
fsa_usbc_ana_en {
|
|
phandle = <0x184>;
|
|
|
|
mux {
|
|
pins = "gpio42";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
};
|
|
|
|
cci0_active {
|
|
phandle = <0x1a8>;
|
|
|
|
mux {
|
|
pins = "gpio17\0gpio18";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio17\0gpio18";
|
|
bias-pull-up;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
cci0_suspend {
|
|
phandle = <0x1aa>;
|
|
|
|
mux {
|
|
pins = "gpio17\0gpio18";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio17\0gpio18";
|
|
bias-disable;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
cci1_active {
|
|
phandle = <0x1a9>;
|
|
|
|
mux {
|
|
pins = "gpio19\0gpio20";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19\0gpio20";
|
|
bias-pull-up;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
cci1_suspend {
|
|
phandle = <0x1ab>;
|
|
|
|
mux {
|
|
pins = "gpio19\0gpio20";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19\0gpio20";
|
|
bias-disable;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
cci2_active {
|
|
phandle = <0x1ac>;
|
|
|
|
mux {
|
|
pins = "gpio27\0gpio28";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27\0gpio28";
|
|
bias-pull-up;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
cci2_suspend {
|
|
phandle = <0x1ad>;
|
|
|
|
mux {
|
|
pins = "gpio27\0gpio28";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27\0gpio28";
|
|
bias-disable;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk0_active {
|
|
phandle = <0x565>;
|
|
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk0_suspend {
|
|
phandle = <0x567>;
|
|
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
bias-pull-down;
|
|
drive-strength = <0x06>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk1_active {
|
|
phandle = <0x56c>;
|
|
|
|
mux {
|
|
pins = "gpio14";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14";
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk1_suspend {
|
|
phandle = <0x56e>;
|
|
|
|
mux {
|
|
pins = "gpio14";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14";
|
|
bias-pull-down;
|
|
drive-strength = <0x06>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk2_active {
|
|
phandle = <0x572>;
|
|
|
|
mux {
|
|
pins = "gpio16";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16";
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk2_suspend {
|
|
phandle = <0x574>;
|
|
|
|
mux {
|
|
pins = "gpio16";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16";
|
|
bias-pull-down;
|
|
drive-strength = <0x06>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk3_active {
|
|
phandle = <0x578>;
|
|
|
|
mux {
|
|
pins = "gpio15";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio15";
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk3_suspend {
|
|
phandle = <0x57c>;
|
|
|
|
mux {
|
|
pins = "gpio15";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio15";
|
|
bias-pull-down;
|
|
drive-strength = <0x06>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
sdc1_clk_on {
|
|
phandle = <0x3d1>;
|
|
|
|
config {
|
|
pins = "sdc1_clk";
|
|
bias-disable;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
sdc1_clk_off {
|
|
phandle = <0x3d2>;
|
|
|
|
config {
|
|
pins = "sdc1_clk";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc1_cmd_on {
|
|
phandle = <0x3d3>;
|
|
|
|
config {
|
|
pins = "sdc1_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
};
|
|
|
|
sdc1_cmd_off {
|
|
phandle = <0x3d4>;
|
|
|
|
config {
|
|
pins = "sdc1_cmd";
|
|
num-grp-pins = <0x01>;
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc1_data_on {
|
|
phandle = <0x3d5>;
|
|
|
|
config {
|
|
pins = "sdc1_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
};
|
|
|
|
sdc1_data_off {
|
|
phandle = <0x3d6>;
|
|
|
|
config {
|
|
pins = "sdc1_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc1_rclk_on {
|
|
phandle = <0x3d7>;
|
|
|
|
config {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sdc1_rclk_off {
|
|
phandle = <0x3d8>;
|
|
|
|
config {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sdc2_clk_on {
|
|
phandle = <0x3d9>;
|
|
|
|
config {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
sdc2_clk_off {
|
|
phandle = <0x3da>;
|
|
|
|
config {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc2_cmd_on {
|
|
phandle = <0x3db>;
|
|
|
|
config {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
};
|
|
|
|
sdc2_cmd_off {
|
|
phandle = <0x3dc>;
|
|
|
|
config {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc2_data_on {
|
|
phandle = <0x3dd>;
|
|
|
|
config {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
};
|
|
|
|
sdc2_data_off {
|
|
phandle = <0x3de>;
|
|
|
|
config {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cd_on {
|
|
phandle = <0x4f4>;
|
|
|
|
mux {
|
|
pins = "gpio88";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio88";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
cd_off {
|
|
phandle = <0x4f5>;
|
|
|
|
mux {
|
|
pins = "gpio88";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio88";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pmx_ts_active {
|
|
|
|
ts_active {
|
|
phandle = <0x3e1>;
|
|
|
|
mux {
|
|
pins = "gpio8\0gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8\0gpio9";
|
|
drive-strength = <0x08>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_int_suspend {
|
|
|
|
ts_int_suspend {
|
|
phandle = <0x3e2>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_reset_suspend {
|
|
|
|
ts_reset_suspend {
|
|
phandle = <0x3e3>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_release {
|
|
|
|
ts_release {
|
|
phandle = <0x3e4>;
|
|
|
|
mux {
|
|
pins = "gpio9\0gpio8";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9\0gpio8";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
usbpd_irq {
|
|
phandle = <0x588>;
|
|
|
|
mux {
|
|
pins = "gpio32";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
if_pmic_irq {
|
|
phandle = <0x4fa>;
|
|
|
|
mux {
|
|
pins = "gpio68";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio68";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
s2mu106_fg_i2c {
|
|
phandle = <0x5b4>;
|
|
|
|
s2mu106_fg_active {
|
|
phandle = <0x587>;
|
|
|
|
mux {
|
|
pins = "gpio102\0gpio101";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio102\0gpio101";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
dc_irq_default {
|
|
phandle = <0x58a>;
|
|
|
|
config {
|
|
pins = "gpio57";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
attn_irq {
|
|
phandle = <0x540>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
input-enable;
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
attn_input {
|
|
phandle = <0x541>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
tas2562_int_default {
|
|
phandle = <0x536>;
|
|
|
|
mux {
|
|
pins = "gpio89";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio89";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
tas2562_rst_default {
|
|
phandle = <0x537>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
s2mpb03_i2c_pins {
|
|
|
|
s2mpb03_i2c_active {
|
|
phandle = <0x54f>;
|
|
|
|
mux {
|
|
pins = "gpio46\0gpio47";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio46\0gpio47";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
grip_i2c {
|
|
|
|
grip_i2c_active {
|
|
phandle = <0x544>;
|
|
|
|
grip_i2c_active {
|
|
pins = "gpio25\0gpio26";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
grip_i2c_suspend {
|
|
phandle = <0x545>;
|
|
|
|
grip_i2c_suspend {
|
|
pins = "gpio25\0gpio26";
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
fuel_irq {
|
|
phandle = <0x551>;
|
|
|
|
config {
|
|
pins = "gpio104";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
hall_default {
|
|
phandle = <0x557>;
|
|
|
|
mux {
|
|
pins = "gpio91";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio91";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
certify_hall_default {
|
|
phandle = <0x558>;
|
|
|
|
mux {
|
|
pins = "gpio93";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio93";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear_active {
|
|
phandle = <0x566>;
|
|
|
|
mux {
|
|
pins = "gpio33";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio33";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear_suspend {
|
|
phandle = <0x568>;
|
|
|
|
mux {
|
|
pins = "gpio33";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio33";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_front_active {
|
|
phandle = <0x56d>;
|
|
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_front_suspend {
|
|
phandle = <0x56f>;
|
|
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear3sw_active {
|
|
phandle = <0x579>;
|
|
|
|
mux {
|
|
pins = "gpio53";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear3sw_suspend {
|
|
phandle = <0x57d>;
|
|
|
|
mux {
|
|
pins = "gpio53";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_rear3_pwr_active {
|
|
phandle = <0x57a>;
|
|
|
|
mux {
|
|
pins = "gpio4";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_rear3_pwr_suspend {
|
|
phandle = <0x57e>;
|
|
|
|
mux {
|
|
pins = "gpio4";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_mipi_sel_active {
|
|
phandle = <0x57b>;
|
|
|
|
mux {
|
|
pins = "gpio51";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio51";
|
|
bias-disable;
|
|
output-high;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_mipi_sel_suspend {
|
|
phandle = <0x57f>;
|
|
|
|
mux {
|
|
pins = "gpio51";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio51";
|
|
bias-pull-down;
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear_sub2_active {
|
|
phandle = <0x573>;
|
|
|
|
mux {
|
|
pins = "gpio67";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio67";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear_sub2_suspend {
|
|
phandle = <0x575>;
|
|
|
|
mux {
|
|
pins = "gpio67";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio67";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_flash_active {
|
|
phandle = <0x552>;
|
|
|
|
mux {
|
|
pins = "gpio22";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_flash_suspend {
|
|
phandle = <0x554>;
|
|
|
|
mux {
|
|
pins = "gpio22";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
cam_torch_active {
|
|
phandle = <0x553>;
|
|
|
|
mux {
|
|
pins = "gpio24";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio24";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
cam_torch_suspend {
|
|
phandle = <0x555>;
|
|
|
|
mux {
|
|
pins = "gpio24";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio24";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
led_enable {
|
|
phandle = <0x5b7>;
|
|
|
|
mux {
|
|
pins = "gpio22";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
led_disable {
|
|
phandle = <0x5b8>;
|
|
|
|
mux {
|
|
pins = "gpio22";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
etspi_rstpin {
|
|
|
|
etspi_rstpin {
|
|
phandle = <0x559>;
|
|
|
|
mux {
|
|
pins = "gpio58";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio58";
|
|
driver-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_sleep {
|
|
phandle = <0x55b>;
|
|
|
|
mux {
|
|
pins = "gpio0\0gpio1\0gpio2\0gpio3";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0\0gpio1\0gpio2\0gpio3";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
nfc_qupv3_se2_i2c_sleep {
|
|
phandle = <0x55a>;
|
|
|
|
mux {
|
|
pins = "gpio34\0gpio35";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio34\0gpio35";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pmx_sde {
|
|
phandle = <0x5bf>;
|
|
|
|
sde_dsi_active {
|
|
phandle = <0x4e2>;
|
|
|
|
mux {
|
|
pins = "gpio11\0gpio64";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11\0gpio64";
|
|
drive-strength = <0x08>;
|
|
bias-disable = <0x00>;
|
|
};
|
|
};
|
|
|
|
sde_dsi_suspend {
|
|
phandle = <0x4e7>;
|
|
|
|
mux {
|
|
pins = "gpio11\0gpio64";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11\0gpio64";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
sde_en_active {
|
|
phandle = <0x4e0>;
|
|
|
|
mux {
|
|
pins = "gpio69";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio69";
|
|
drive-strength = <0x08>;
|
|
bias-disable = <0x00>;
|
|
};
|
|
};
|
|
|
|
sde_en_suspend {
|
|
phandle = <0x4e5>;
|
|
|
|
mux {
|
|
pins = "gpio69";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio69";
|
|
drive-strength = <0x02>;
|
|
bias-disable = <0x00>;
|
|
};
|
|
};
|
|
|
|
pmx_sde_ub_det {
|
|
|
|
sde_ub_det_active {
|
|
phandle = <0x4e4>;
|
|
|
|
mux {
|
|
pins = "gpio66";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio66";
|
|
drive-strength = <0x02>;
|
|
bias-disable = <0x00>;
|
|
};
|
|
};
|
|
|
|
sde_ub_det_suspend {
|
|
phandle = <0x4e9>;
|
|
|
|
mux {
|
|
pins = "gpio66";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio66";
|
|
drive-strength = <0x02>;
|
|
bias-disable = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sde_esd_active {
|
|
phandle = <0x4e3>;
|
|
|
|
mux {
|
|
pins = "gpio63";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio63";
|
|
drive-strength = <0x08>;
|
|
bias-disable = <0x00>;
|
|
};
|
|
};
|
|
|
|
sde_esd_suspend {
|
|
phandle = <0x4e8>;
|
|
|
|
mux {
|
|
pins = "gpio63";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio63";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-gfxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "gfx.lvl";
|
|
|
|
regulator-pm6150-s2-level {
|
|
regulator-name = "pm6150_s2_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x11>;
|
|
regulator-max-microvolt = <0x10000>;
|
|
qcom,init-voltage-level = <0x11>;
|
|
phandle = <0x20>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-mxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "mx.lvl";
|
|
|
|
regulator-pm6150-s3 {
|
|
regulator-name = "pm6150_s3_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x11>;
|
|
regulator-max-microvolt = <0x10000>;
|
|
qcom,init-voltage-level = <0x11>;
|
|
phandle = <0x1f>;
|
|
};
|
|
|
|
regulator-pm6150-s3-level-ao {
|
|
regulator-name = "pm6150_s3_level_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x11>;
|
|
regulator-max-microvolt = <0x10000>;
|
|
qcom,init-voltage-level = <0x11>;
|
|
phandle = <0x1c6>;
|
|
};
|
|
|
|
mx-cdev-lvl {
|
|
compatible = "qcom,regulator-cooling-device";
|
|
regulator-cdev-supply = <0x1f>;
|
|
regulator-levels = <0x101 0x01>;
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x6b>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpc1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "smpc1";
|
|
|
|
regulator-pm6150l-s1 {
|
|
regulator-name = "pm6150l_s1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xf4240>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0xf4240>;
|
|
phandle = <0x3e5>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-cxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "cx.lvl";
|
|
pm6150l-s2-level-parent-supply = <0x1f>;
|
|
pm6150l-s2-level_ao-parent-supply = <0x1c6>;
|
|
|
|
regulator-pm6150l-s2 {
|
|
regulator-name = "pm6150l_s2_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x11>;
|
|
regulator-max-microvolt = <0x10000>;
|
|
qcom,init-voltage-level = <0x11>;
|
|
qcom,min-dropout-voltage-level = <0xffffffff>;
|
|
phandle = <0x1d>;
|
|
};
|
|
|
|
regulator-pm6150l-s2-level-ao {
|
|
qcom,set = <0x01>;
|
|
regulator-name = "pm6150l_s2_level_ao";
|
|
regulator-min-microvolt = <0x11>;
|
|
regulator-max-microvolt = <0x10000>;
|
|
qcom,init-voltage-level = <0x11>;
|
|
qcom,min-dropout-voltage-level = <0xffffffff>;
|
|
phandle = <0x1e>;
|
|
};
|
|
|
|
regulator-cdev {
|
|
compatible = "qcom,rpmh-reg-cdev";
|
|
mboxes = <0x1c 0x00>;
|
|
qcom,reg-resource-name = "cx";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x6a>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-modemlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "mss.lvl";
|
|
|
|
regulator-pm6150l-s7 {
|
|
regulator-name = "pm6150l_s7_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x11>;
|
|
regulator-max-microvolt = <0x10000>;
|
|
qcom,init-voltage-level = <0x11>;
|
|
phandle = <0xa8>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpc8 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "smpc8";
|
|
|
|
regulator-pm6150l-s8 {
|
|
regulator-name = "pm6150l_s8";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x111700>;
|
|
regulator-max-microvolt = <0x157c00>;
|
|
qcom,init-voltage = <0x111700>;
|
|
phandle = <0x3e6>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpf1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "smpf1";
|
|
|
|
regulator-pm8009-s1 {
|
|
regulator-name = "pm8009_s1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x103c40>;
|
|
regulator-max-microvolt = <0x14c080>;
|
|
qcom,init-voltage = <0x103c40>;
|
|
phandle = <0x3e7>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpf2 {
|
|
compatible = "qcom,rpmh-xob-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "smpf2";
|
|
|
|
regulator-pm8009-s2 {
|
|
regulator-name = "pm8009_s2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2c4020>;
|
|
regulator-max-microvolt = <0x2c4020>;
|
|
phandle = <0x3e8>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l1 {
|
|
regulator-name = "pm6150_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10b940>;
|
|
regulator-max-microvolt = <0x13e5c0>;
|
|
qcom,init-voltage = <0x10b940>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3e9>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l2 {
|
|
regulator-name = "pm6150_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xe6780>;
|
|
regulator-max-microvolt = <0x101d00>;
|
|
qcom,init-voltage = <0xe6780>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3ea>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l3 {
|
|
regulator-name = "pm6150_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xec540>;
|
|
regulator-max-microvolt = <0x103c40>;
|
|
qcom,init-voltage = <0xec540>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3eb>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa4";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l4 {
|
|
regulator-name = "pm6150_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xc92c0>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xc92c0>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x1a1>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa5";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l5 {
|
|
regulator-name = "pm6150_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x27ac40>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x27ac40>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3ec>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa6";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l6 {
|
|
regulator-name = "pm6150_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x100590>;
|
|
regulator-max-microvolt = <0x13e5c0>;
|
|
qcom,init-voltage = <0x100590>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3ed>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-lmxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "lmx.lvl";
|
|
|
|
regulator-pm6150-l7 {
|
|
regulator-name = "pm6150_l7_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x11>;
|
|
regulator-max-microvolt = <0x10000>;
|
|
qcom,init-voltage-level = <0x11>;
|
|
phandle = <0x96>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-lcxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "lcx.lvl";
|
|
|
|
regulator-pm6150-l8 {
|
|
regulator-name = "pm6150_l8_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x11>;
|
|
regulator-max-microvolt = <0x10000>;
|
|
qcom,init-voltage-level = <0x11>;
|
|
phandle = <0x95>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa9 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa9";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l9 {
|
|
regulator-name = "pm6150_l9";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x98580>;
|
|
regulator-max-microvolt = <0xb98c0>;
|
|
qcom,init-voltage = <0x98580>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0xb0>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa10 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa10";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm6150-l10 {
|
|
regulator-name = "pm6150_l10";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1a3ec0>;
|
|
regulator-max-microvolt = <0x1bf440>;
|
|
qcom,init-voltage = <0x1a3ec0>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x31>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa11 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa11";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l11 {
|
|
regulator-name = "pm6150_l11";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x19e100>;
|
|
regulator-max-microvolt = <0x1e4600>;
|
|
qcom,init-voltage = <0x19e100>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x1c7>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa12 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa12";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l12 {
|
|
regulator-name = "pm6150_l12";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x19e100>;
|
|
regulator-max-microvolt = <0x1dc900>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3ee>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa13 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa13";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l13 {
|
|
regulator-name = "pm6150_l13";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x19e100>;
|
|
regulator-max-microvolt = <0x1d0d80>;
|
|
qcom,init-voltage = <0x19e100>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3ef>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa14 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa14";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l14 {
|
|
regulator-name = "pm6150_l14";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1a3ec0>;
|
|
regulator-max-microvolt = <0x1c5200>;
|
|
qcom,init-voltage = <0x1a3ec0>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3f0>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa15 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa15";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l15 {
|
|
regulator-name = "pm6150_l15";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x19e100>;
|
|
regulator-max-microvolt = <0x1d0d80>;
|
|
qcom,init-voltage = <0x19e100>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3f1>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa16 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa16";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l16 {
|
|
regulator-name = "pm6150_l16";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
qcom,init-voltage = <0x325aa0>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3f2>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa17 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa17";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
pm6150_l17-parent-supply = <0x1c7>;
|
|
|
|
regulator-pm6150-l17 {
|
|
regulator-name = "pm6150_l17";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2dc6c0>;
|
|
regulator-max-microvolt = "\01Q";
|
|
qcom,init-voltage = <0x2dc6c0>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x9c>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa18 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa18";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l18 {
|
|
regulator-name = "pm6150_l18";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2dc6c0>;
|
|
phandle = <0x4ea>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
qcom,init-mode = <0x02>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoa19 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoa19";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150-l19 {
|
|
regulator-name = "pm6150_l19";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2cec00>;
|
|
regulator-max-microvolt = <0x326a40>;
|
|
qcom,init-voltage = <0x2cec00>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3f4>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm6150l-l1 {
|
|
regulator-name = "pm6150l_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x18a880>;
|
|
regulator-max-microvolt = <0x1e4600>;
|
|
qcom,init-voltage = <0x18a880>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x34>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm6150l-l2 {
|
|
regulator-name = "pm6150l_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x14a140>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x32>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150l-l3 {
|
|
regulator-name = "pm6150l_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1174c0>;
|
|
regulator-max-microvolt = <0x132a40>;
|
|
qcom,init-voltage = <0x1174c0>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x1a0>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc4";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150l-l4 {
|
|
regulator-name = "pm6150l_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x192580>;
|
|
regulator-max-microvolt = <0x2d0370>;
|
|
qcom,init-voltage = <0x192580>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3f5>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc5";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150l-l5 {
|
|
regulator-name = "pm6150l_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x192580>;
|
|
regulator-max-microvolt = <0x2d0370>;
|
|
qcom,init-voltage = <0x192580>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3f6>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc6";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150l-l6 {
|
|
regulator-name = "pm6150l_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x192580>;
|
|
regulator-max-microvolt = <0x2f4d60>;
|
|
qcom,init-voltage = <0x192580>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3f7>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc7 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc7";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150l-l7 {
|
|
regulator-name = "pm6150l_l7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
qcom,init-voltage = <0x325aa0>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3f8>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc8 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc8";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150l-l8 {
|
|
regulator-name = "pm6150l_l8";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1cfde0>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3f9>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc9 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc9";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150l-l9 {
|
|
regulator-name = "pm6150l_l9";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2d0370>;
|
|
regulator-max-microvolt = <0x328980>;
|
|
qcom,init-voltage = <0x2d0370>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3fa>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc10 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc10";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm6150l-l10 {
|
|
regulator-name = "pm6150l_l10";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x30d400>;
|
|
regulator-max-microvolt = <0x328980>;
|
|
qcom,init-voltage = <0x30d400>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x33>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoc11 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldoc11";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm6150l-l11 {
|
|
regulator-name = "pm6150l_l11";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
qcom,init-voltage = <0x325aa0>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3fb>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-bobc1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "bobc1";
|
|
qcom,regulator-type = "pmic5-bob";
|
|
qcom,supported-modes = <0x00 0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0xf4240 0x1e8480>;
|
|
qcom,send-defaults;
|
|
|
|
regulator-pm6150l-bob {
|
|
regulator-name = "pm6150l_bob";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = "\02K";
|
|
regulator-max-microvolt = <0x3c6cc0>;
|
|
qcom,init-voltage = "\02K";
|
|
qcom,init-mode = <0x00>;
|
|
phandle = <0x3fc>;
|
|
};
|
|
|
|
regulator-pm6150l-bob-ao {
|
|
regulator-name = "pm6150l_bob_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = "\02K";
|
|
regulator-max-microvolt = <0x3c6cc0>;
|
|
qcom,init-voltage = "\02K";
|
|
qcom,init-mode = <0x03>;
|
|
phandle = <0x3fd>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldof1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldof1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm8009-l1 {
|
|
regulator-name = "pm8009_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10c8e0>;
|
|
regulator-max-microvolt = <0x13e5c0>;
|
|
qcom,init-voltage = <0x10c8e0>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x3fe>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldof2 {
|
|
compatible = "qcom,rpmh-xob-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldof2";
|
|
|
|
regulator-pm8009-l2 {
|
|
regulator-name = "pm8009_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x100590>;
|
|
regulator-max-microvolt = <0x100590>;
|
|
phandle = <0x3ff>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldof4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldof4";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm8009-l4 {
|
|
regulator-name = "pm8009_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10b940>;
|
|
regulator-max-microvolt = <0x13e5c0>;
|
|
qcom,init-voltage = <0x10b940>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x400>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldof5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldof5";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm8009-l5 {
|
|
regulator-name = "pm8009_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x292340>;
|
|
regulator-max-microvolt = <0x2c4fc0>;
|
|
qcom,init-voltage = <0x292340>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x401>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldof6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldof6";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x01>;
|
|
|
|
regulator-pm8009-l6 {
|
|
regulator-name = "pm8009_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x292340>;
|
|
regulator-max-microvolt = <0x2c4fc0>;
|
|
qcom,init-voltage = <0x292340>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x402>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldof7 {
|
|
compatible = "qcom,rpmh-xob-regulator";
|
|
mboxes = <0x1b 0x00>;
|
|
qcom,resource-name = "ldof7";
|
|
|
|
regulator-pm8009-l7 {
|
|
regulator-name = "pm8009_l7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
phandle = <0x403>;
|
|
};
|
|
};
|
|
|
|
refgen-regulator@ff1000 {
|
|
compatible = "qcom,refgen-regulator";
|
|
reg = <0xff1000 0x60>;
|
|
regulator-name = "refgen";
|
|
regulator-enable-ramp-delay = <0x05>;
|
|
proxy-supply = <0x1a7>;
|
|
qcom,proxy-consumer-enable;
|
|
phandle = <0x1a7>;
|
|
};
|
|
|
|
csr@6001000 {
|
|
compatible = "qcom,coresight-csr";
|
|
reg = <0x6001000 0x1000>;
|
|
reg-names = "csr-base";
|
|
coresight-name = "coresight-csr";
|
|
qcom,usb-bam-support;
|
|
qcom,hwctrl-set-support;
|
|
qcom,set-byte-cntr-support;
|
|
qcom,blk-size = <0x01>;
|
|
phandle = <0x1ce>;
|
|
};
|
|
|
|
replicator@6046000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b909>;
|
|
reg = <0x6046000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x404>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c8>;
|
|
phandle = <0x1cf>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c9>;
|
|
phandle = <0x1cc>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1ca>;
|
|
phandle = <0x1d0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@604a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b909>;
|
|
reg = <0x604a000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-qdss1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x405>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1cb>;
|
|
phandle = <0x1f1>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1cc>;
|
|
phandle = <0x1c9>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@6048000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b961>;
|
|
reg = <0x6048000 0x1000 0x6064000 0x15000>;
|
|
reg-names = "tmc-base\0bam-base";
|
|
iommus = <0x30 0x5e0 0x00 0x30 0x4a0 0x00>;
|
|
arm,buffer-size = <0x400000>;
|
|
coresight-name = "coresight-tmc-etr";
|
|
coresight-ctis = <0x1cd 0x1cd>;
|
|
coresight-csr = <0x1ce>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
interrupts = <0x00 0x10e 0x01>;
|
|
interrupt-names = "byte-cntr-irq";
|
|
phandle = <0x406>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1cf>;
|
|
phandle = <0x1c8>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@6047000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b961>;
|
|
reg = <0x6047000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etf";
|
|
coresight-ctis = <0x1cd 0x1cd>;
|
|
arm,default-sink;
|
|
coresight-csr = <0x1ce>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x407>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d0>;
|
|
phandle = <0x1ca>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1d1>;
|
|
phandle = <0x1d2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6045000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6045000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-merg";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x408>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d2>;
|
|
phandle = <0x1d1>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1d3>;
|
|
phandle = <0x1d6>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1d4>;
|
|
phandle = <0x1dc>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1d5>;
|
|
phandle = <0x1f8>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@0x6041000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6041000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-in0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x409>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d6>;
|
|
phandle = <0x1d3>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1d7>;
|
|
phandle = <0x224>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1d8>;
|
|
phandle = <0x1db>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1d9>;
|
|
phandle = <0x21e>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1da>;
|
|
phandle = <0x21d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
audio_etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-audio-etm0";
|
|
qcom,inst-id = <0x05>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1db>;
|
|
phandle = <0x1d8>;
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6042000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6042000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-in1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x40a>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1dc>;
|
|
phandle = <0x1d4>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1dd>;
|
|
phandle = <0x1e9>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1de>;
|
|
phandle = <0x1ec>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1df>;
|
|
phandle = <0x1e0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6832000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6832000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-modem";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x40b>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e0>;
|
|
phandle = <0x1df>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1e1>;
|
|
phandle = <0x1e3>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1e2>;
|
|
phandle = <0x1e5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@6831000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b969>;
|
|
reg = <0x6831000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-modem-0";
|
|
qcom,tpda-atid = <0x43>;
|
|
qcom,dsb-elem-size = <0x00 0x20>;
|
|
qcom,cmb-elem-size = <0x00 0x40>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x40c>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e3>;
|
|
phandle = <0x1e1>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1e4>;
|
|
phandle = <0x1e7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@6833000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b969>;
|
|
reg = <0x6833000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-modem-1";
|
|
qcom,tpda-atid = <0x62>;
|
|
qcom,dsb-elem-size = <0x00 0x20>;
|
|
qcom,cmb-elem-size = <0x00 0x40>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x40d>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e5>;
|
|
phandle = <0x1e2>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1e6>;
|
|
phandle = <0x1e8>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6830000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6830000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-modem-0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x40e>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e7>;
|
|
phandle = <0x1e4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6834000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6834000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-modem-1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x40f>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e8>;
|
|
phandle = <0x1e6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
modem_etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-modem-etm0";
|
|
qcom,inst-id = <0x02>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e9>;
|
|
phandle = <0x1dd>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dummy_sink {
|
|
compatible = "qcom,coresight-dummy";
|
|
coresight-name = "coresight-eud";
|
|
qcom,dummy-sink;
|
|
phandle = <0x410>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1ea>;
|
|
phandle = <0x1eb>;
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@6b0a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b909>;
|
|
reg = <0x6b0a000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-swao";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x411>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1eb>;
|
|
phandle = <0x1ea>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ec>;
|
|
phandle = <0x1de>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1ed>;
|
|
phandle = <0x1ee>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@6b09000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b961>;
|
|
reg = <0x6b09000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etf-swao";
|
|
coresight-csr = <0x1ce>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x412>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ee>;
|
|
phandle = <0x1ed>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1ef>;
|
|
phandle = <0x1f0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
csr@6b0e000 {
|
|
compatible = "qcom,coresight-csr";
|
|
reg = <0x6b0e000 0x1000>;
|
|
reg-names = "csr-base";
|
|
coresight-name = "coresight-swao-csr";
|
|
qcom,timestamp-support;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
qcom,blk-size = <0x01>;
|
|
phandle = <0x413>;
|
|
};
|
|
|
|
funnel@6b08000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6b08000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-swao";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x414>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f0>;
|
|
phandle = <0x1ef>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1f1>;
|
|
phandle = <0x1cb>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1f2>;
|
|
phandle = <0x1f3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@6b01000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b969>;
|
|
reg = <0x6b01000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-swao";
|
|
qcom,tpda-atid = <0x47>;
|
|
qcom,dsb-elem-size = <0x01 0x20>;
|
|
qcom,cmb-elem-size = <0x00 0x40>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x415>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f3>;
|
|
phandle = <0x1f2>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1f4>;
|
|
phandle = <0x1f6>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1f5>;
|
|
phandle = <0x1f7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6b02000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6b02000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x416>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f6>;
|
|
phandle = <0x1f4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6b03000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6b03000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
qcom,msr-fix-req;
|
|
phandle = <0x417>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f7>;
|
|
phandle = <0x1f5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6043000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6043000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-in2";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x418>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f8>;
|
|
phandle = <0x1d5>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1f9>;
|
|
phandle = <0x1fa>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@7810000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x7810000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-apss-merg";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x419>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fa>;
|
|
phandle = <0x1f9>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1fb>;
|
|
phandle = <0x20c>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1fc>;
|
|
phandle = <0x200>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1fd>;
|
|
phandle = <0x206>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1fe>;
|
|
phandle = <0x209>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x1ff>;
|
|
phandle = <0x203>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@7832000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b969>;
|
|
reg = <0x7832000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-olc";
|
|
qcom,tpda-atid = <0x45>;
|
|
qcom,cmb-elem-size = <0x00 0x40>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x41a>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x200>;
|
|
phandle = <0x1fc>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x201>;
|
|
phandle = <0x202>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@7830000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x7830000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-olc";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x41b>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x202>;
|
|
phandle = <0x201>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@7862000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b969>;
|
|
reg = <0x7862000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-apss";
|
|
qcom,tpda-atid = <0x42>;
|
|
qcom,dsb-elem-size = <0x00 0x20>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x41c>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x203>;
|
|
phandle = <0x1ff>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x204>;
|
|
phandle = <0x205>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@7860000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x7860000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-apss";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x41d>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x205>;
|
|
phandle = <0x204>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@78c0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b969>;
|
|
reg = <0x78c0000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-llm-silver";
|
|
qcom,tpda-atid = <0x48>;
|
|
qcom,cmb-elem-size = <0x00 0x20>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x41e>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x206>;
|
|
phandle = <0x1fd>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x207>;
|
|
phandle = <0x208>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@78a0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x78a0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-llm-silver";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x41f>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x208>;
|
|
phandle = <0x207>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@78d0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b969>;
|
|
reg = <0x78d0000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-llm-gold";
|
|
qcom,tpda-atid = <0x49>;
|
|
qcom,cmb-elem-size = <0x00 0x20>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x420>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x209>;
|
|
phandle = <0x1fe>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x20a>;
|
|
phandle = <0x20b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@78b0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x78b0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-llm-gold";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x421>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20b>;
|
|
phandle = <0x20a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@7800000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x7800000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-apss";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x422>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20c>;
|
|
phandle = <0x1fb>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x20d>;
|
|
phandle = <0x215>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x20e>;
|
|
phandle = <0x216>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x20f>;
|
|
phandle = <0x217>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x210>;
|
|
phandle = <0x218>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x211>;
|
|
phandle = <0x219>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x212>;
|
|
phandle = <0x21a>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x213>;
|
|
phandle = <0x21b>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x214>;
|
|
phandle = <0x21c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7040000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb95d>;
|
|
reg = <0x7040000 0x1000>;
|
|
cpu = <0x11>;
|
|
qcom,tupwr-disable;
|
|
coresight-name = "coresight-etm0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x423>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x215>;
|
|
phandle = <0x20d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7140000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb95d>;
|
|
reg = <0x7140000 0x1000>;
|
|
cpu = <0x12>;
|
|
qcom,tupwr-disable;
|
|
coresight-name = "coresight-etm1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x424>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x216>;
|
|
phandle = <0x20e>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7240000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb95d>;
|
|
reg = <0x7240000 0x1000>;
|
|
cpu = <0x13>;
|
|
qcom,tupwr-disable;
|
|
coresight-name = "coresight-etm2";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x425>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x217>;
|
|
phandle = <0x20f>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7340000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb95d>;
|
|
reg = <0x7340000 0x1000>;
|
|
cpu = <0x14>;
|
|
qcom,tupwr-disable;
|
|
coresight-name = "coresight-etm3";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x426>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x218>;
|
|
phandle = <0x210>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7440000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb95d>;
|
|
reg = <0x7440000 0x1000>;
|
|
cpu = <0x15>;
|
|
qcom,tupwr-disable;
|
|
coresight-name = "coresight-etm4";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x427>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x219>;
|
|
phandle = <0x211>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7540000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb95d>;
|
|
reg = <0x7540000 0x1000>;
|
|
cpu = <0x16>;
|
|
qcom,tupwr-disable;
|
|
coresight-name = "coresight-etm5";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x428>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21a>;
|
|
phandle = <0x212>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7640000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb95d>;
|
|
reg = <0x7640000 0x1000>;
|
|
cpu = <0x17>;
|
|
qcom,tupwr-disable;
|
|
coresight-name = "coresight-etm6";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x429>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21b>;
|
|
phandle = <0x213>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7740000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb95d>;
|
|
reg = <0x7740000 0x1000>;
|
|
cpu = <0x18>;
|
|
qcom,tupwr-disable;
|
|
coresight-name = "coresight-etm7";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x42a>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21c>;
|
|
phandle = <0x214>;
|
|
};
|
|
};
|
|
};
|
|
|
|
stm@6002000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b962>;
|
|
reg = <0x6002000 0x1000 0x16280000 0x180000>;
|
|
reg-names = "stm-base\0stm-stimulus-base";
|
|
coresight-name = "coresight-stm";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x42b>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21d>;
|
|
phandle = <0x1da>;
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6005000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6005000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-qatb";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x42c>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21e>;
|
|
phandle = <0x1d9>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x21f>;
|
|
phandle = <0x226>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x220>;
|
|
phandle = <0x222>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x221>;
|
|
phandle = <0x23f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel_1@6b53000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6b58000 0x10 0x6b53000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-dl-south-1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x42d>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x222>;
|
|
phandle = <0x220>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x223>;
|
|
phandle = <0x225>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dummy_source {
|
|
compatible = "qcom,coresight-dummy";
|
|
coresight-name = "coresight-tpdm-lpass";
|
|
qcom,dummy-source;
|
|
phandle = <0x42e>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x224>;
|
|
phandle = <0x1d7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@699c000 {
|
|
compatible = "qcom,coresight-dummy";
|
|
coresight-name = "coresight-tpdm-wcss";
|
|
qcom,dummy-source;
|
|
phandle = <0x42f>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x225>;
|
|
phandle = <0x223>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@6004000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b969>;
|
|
reg = <0x6004000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda";
|
|
qcom,tpda-atid = <0x41>;
|
|
qcom,bc-elem-size = <0x0a 0x20 0x0d 0x20>;
|
|
qcom,tc-elem-size = <0x0d 0x20>;
|
|
qcom,dsb-elem-size = <0x00 0x20 0x02 0x20 0x03 0x20 0x05 0x20 0x06 0x20 0x0a 0x20 0x0b 0x20 0x0d 0x20>;
|
|
qcom,cmb-elem-size = <0x03 0x40 0x07 0x40 0x0d 0x40>;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x430>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x226>;
|
|
phandle = <0x21f>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x227>;
|
|
phandle = <0x236>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x228>;
|
|
phandle = <0x239>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x229>;
|
|
phandle = <0x23a>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x22a>;
|
|
phandle = <0x23d>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x22b>;
|
|
phandle = <0x243>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x22c>;
|
|
phandle = <0x247>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x08>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x22d>;
|
|
phandle = <0x24a>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <0x0a>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x22e>;
|
|
phandle = <0x24b>;
|
|
};
|
|
};
|
|
|
|
port@9 {
|
|
reg = <0x0b>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x22f>;
|
|
phandle = <0x24c>;
|
|
};
|
|
};
|
|
|
|
port@10 {
|
|
reg = <0x0c>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x230>;
|
|
phandle = <0x24d>;
|
|
};
|
|
};
|
|
|
|
port@11 {
|
|
reg = <0x0d>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x231>;
|
|
phandle = <0x24e>;
|
|
};
|
|
};
|
|
|
|
port@12 {
|
|
reg = <0x0e>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x232>;
|
|
phandle = <0x250>;
|
|
};
|
|
};
|
|
|
|
port@13 {
|
|
reg = <0x0f>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x233>;
|
|
phandle = <0x24f>;
|
|
};
|
|
};
|
|
|
|
port@14 {
|
|
reg = <0x11>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x234>;
|
|
phandle = <0x235>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6006000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6006000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-qdss";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x431>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x235>;
|
|
phandle = <0x234>;
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@69C3000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x69c3000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-dl-mm";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x432>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x236>;
|
|
phandle = <0x227>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x237>;
|
|
phandle = <0x238>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@69c0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x69c0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dl-mm";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x433>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x238>;
|
|
phandle = <0x237>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6c28000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6c28000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dl-center";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
qcom,msr-fix-req;
|
|
phandle = <0x434>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x239>;
|
|
phandle = <0x228>;
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6b53000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6b53000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-dl-south";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x435>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23a>;
|
|
phandle = <0x229>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x23b>;
|
|
phandle = <0x23c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6b52000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6b52000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dl-south";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x436>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23c>;
|
|
phandle = <0x23b>;
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6861000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6861000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-turing";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x437>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23d>;
|
|
phandle = <0x22a>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x23e>;
|
|
phandle = <0x242>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel_1@6861000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6867010 0x10 0x6861000 0x1000>;
|
|
reg-names = "funnel-base-dummy\0funnel-base-real";
|
|
coresight-name = "coresight-funnel-turing1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
qcom,duplicate-funnel;
|
|
phandle = <0x438>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23f>;
|
|
phandle = <0x221>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x240>;
|
|
phandle = <0x241>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
turing_etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-turing-etm0";
|
|
qcom,inst-id = <0x0d>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x241>;
|
|
phandle = <0x240>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6860000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6860000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-turing";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
qcom,msr-fix-req;
|
|
phandle = <0x439>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x242>;
|
|
phandle = <0x23e>;
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6a05000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6a05000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-ddr-0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x43a>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x243>;
|
|
phandle = <0x22b>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x244>;
|
|
phandle = <0x245>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6a00000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6a00000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
qcom,msr-fix-req;
|
|
phandle = <0x43b>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x245>;
|
|
phandle = <0x244>;
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6943000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b908>;
|
|
reg = <0x6943000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-gfx";
|
|
clocks = <0x19 0x00 0x2b 0x08>;
|
|
clock-names = "apb_pclk\0gpu_apb_clk";
|
|
qcom,proxy-clks = "gpu_apb_clk";
|
|
status = "disabled";
|
|
regulator-names = "vddcx\0vdd";
|
|
vddcx-supply = <0x1bd>;
|
|
vdd-supply = <0x246>;
|
|
qcom,proxy-regs = "vddcx\0vdd";
|
|
phandle = <0x43c>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x247>;
|
|
phandle = <0x22c>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x248>;
|
|
phandle = <0x249>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6940000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6940000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-gpu";
|
|
clocks = <0x19 0x00 0x2b 0x08>;
|
|
clock-names = "apb_pclk\0gpu_apb_clk";
|
|
qcom,tpdm-clks = "gpu_apb_clk";
|
|
status = "disabled";
|
|
regulator-names = "vddcx\0vdd";
|
|
vddcx-supply = <0x1bd>;
|
|
vdd-supply = <0x246>;
|
|
qcom,tpdm-regs = "vddcx\0vdd";
|
|
qcom,msr-fix-req;
|
|
phandle = <0x43d>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x249>;
|
|
phandle = <0x248>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6840000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6840000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-vsense";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x43e>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24a>;
|
|
phandle = <0x22d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@684c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x684c000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-prng";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x43f>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24b>;
|
|
phandle = <0x22e>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6b48000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6b48000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-north";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x440>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24c>;
|
|
phandle = <0x22f>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@69d0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x69d0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-qm";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x441>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24d>;
|
|
phandle = <0x230>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6850000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6850000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-pimem";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x442>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24e>;
|
|
phandle = <0x231>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@6b44000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x6b44000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-center";
|
|
qcom,msr-fix-req;
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x443>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24f>;
|
|
phandle = <0x233>;
|
|
};
|
|
};
|
|
};
|
|
|
|
hwevent@0x014066f0 {
|
|
compatible = "qcom,coresight-hwevent";
|
|
reg = <0x14066f0 0x04 0x14166f0 0x04 0x1406038 0x04 0x1416038 0x04>;
|
|
reg-names = "ddr-ch0-cfg\0ddr-ch23-cfg\0ddr-ch0-ctrl\0ddr-ch23-ctrl";
|
|
coresight-csr = <0x1ce>;
|
|
coresight-name = "coresight-hwevent";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x444>;
|
|
};
|
|
|
|
cti@78e0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x78e0000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-apss_cti0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x445>;
|
|
};
|
|
|
|
cti@78f0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x78f0000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-apss_cti1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x446>;
|
|
};
|
|
|
|
cti@7900000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x7900000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-apss_cti2";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x447>;
|
|
};
|
|
|
|
cti@6a02000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6a02000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-ddr_dl_0_cti0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x448>;
|
|
};
|
|
|
|
cti@6a03000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6a03000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-ddr_dl_0_cti1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x449>;
|
|
};
|
|
|
|
cti@6a10000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6a10000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-ddr_dl_1_cti0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x44a>;
|
|
};
|
|
|
|
cti@6a11000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6a11000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-ddr_dl_1_cti1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x44b>;
|
|
};
|
|
|
|
cti@6a12000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6a12000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-ddr_dl_1_cti2";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x44c>;
|
|
};
|
|
|
|
cti@69C1000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x69c1000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-dlmm_cti0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x44d>;
|
|
};
|
|
|
|
cti@69C2000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x69c2000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-dlmm_cti1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x44e>;
|
|
};
|
|
|
|
cti@6c29000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6c29000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-dlct_cti0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x44f>;
|
|
};
|
|
|
|
cti@6c2a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6c2a000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-dlct_cti1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x450>;
|
|
};
|
|
|
|
cti@69a4000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x69a4000 0x1000>;
|
|
reg-names = "cti-base";
|
|
status = "disabled";
|
|
coresight-name = "coresight-cti-wcss_cti0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x451>;
|
|
};
|
|
|
|
cti@69a5000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x69a5000 0x1000>;
|
|
reg-names = "cti-base";
|
|
status = "disabled";
|
|
coresight-name = "coresight-cti-wcss_cti1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x452>;
|
|
};
|
|
|
|
cti@69a6000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x69a6000 0x1000>;
|
|
reg-names = "cti-base";
|
|
status = "disabled";
|
|
coresight-name = "coresight-cti-wcss_cti2";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x453>;
|
|
};
|
|
|
|
cti@683b000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x683b000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-mss-q6";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x454>;
|
|
};
|
|
|
|
cti@6867000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6867000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-turing";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x455>;
|
|
};
|
|
|
|
cti@6b04000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6b04000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-swao_cti0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x456>;
|
|
};
|
|
|
|
cti@6b05000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6b05000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-swao_cti1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x457>;
|
|
};
|
|
|
|
cti@6b06000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6b06000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-swao_cti2";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x458>;
|
|
};
|
|
|
|
cti@6b07000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6b07000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-swao_cti3";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x459>;
|
|
};
|
|
|
|
cti@6b21000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6b21000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-aop-m3";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x45a>;
|
|
};
|
|
|
|
cti@6c13000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6c13000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-titan";
|
|
status = "disabled";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x45b>;
|
|
};
|
|
|
|
cti@6c20000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6c20000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti-venus-arm9";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x45c>;
|
|
};
|
|
|
|
cti@6010000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6010000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti0";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x1cd>;
|
|
};
|
|
|
|
cti@6011000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6011000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti1";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x45d>;
|
|
};
|
|
|
|
cti@6012000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6012000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti2";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x45e>;
|
|
};
|
|
|
|
cti@6013000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6013000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti3";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x45f>;
|
|
};
|
|
|
|
cti@6014000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6014000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti4";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x460>;
|
|
};
|
|
|
|
cti@6015000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6015000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti5";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x461>;
|
|
};
|
|
|
|
cti@6016000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6016000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti6";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x462>;
|
|
};
|
|
|
|
cti@6017000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6017000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti7";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x463>;
|
|
};
|
|
|
|
cti@6018000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6018000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti8";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x464>;
|
|
};
|
|
|
|
cti@6019000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x6019000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti9";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x465>;
|
|
};
|
|
|
|
cti@601a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x601a000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti10";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x466>;
|
|
};
|
|
|
|
cti@601b000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x601b000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti11";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x467>;
|
|
};
|
|
|
|
cti@601c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x601c000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti12";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x468>;
|
|
};
|
|
|
|
cti@601d000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x601d000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti13";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x469>;
|
|
};
|
|
|
|
cti@601e000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x601e000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti14";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x46a>;
|
|
};
|
|
|
|
cti@601f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b966>;
|
|
reg = <0x601f000 0x1000>;
|
|
reg-names = "cti-base";
|
|
coresight-name = "coresight-cti15";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x46b>;
|
|
};
|
|
|
|
tgu@6b0c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b999>;
|
|
reg = <0x6b0c000 0x1000>;
|
|
reg-names = "tgu-base";
|
|
tgu-steps = <0x03>;
|
|
tgu-conditions = <0x04>;
|
|
tgu-regs = <0x04>;
|
|
tgu-timer-counters = <0x08>;
|
|
coresight-name = "coresight-tgu-ipcb";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x46c>;
|
|
};
|
|
|
|
tpdm@69e1000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x3b968>;
|
|
reg = <0x69e1000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-npu";
|
|
clocks = <0x19 0x00 0x2c 0x0c 0x2c 0x0d 0x2c 0x0e 0x2c 0x0f 0x2c 0x10>;
|
|
clock-names = "apb_pclk\0npu_core_apb_clk\0npu_core_atb_clk\0npu_core_clk\0npu_core_clk_src\0npu_core_cti_clk";
|
|
qcom,tpdm-clks = "npu_core_apb_clk\0npu_core_atb_clk\0npu_core_clk\0npu_core_clk_src\0npu_core_cti_clk";
|
|
vdd-supply = <0x23>;
|
|
vdd_cx-supply = <0x1d>;
|
|
qcom,tpdm-regs = "vdd\0vdd_cx";
|
|
phandle = <0x46d>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x250>;
|
|
phandle = <0x232>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ssusb@a600000 {
|
|
compatible = "qcom,dwc-usb3-msm";
|
|
reg = <0xa600000 0x100000>;
|
|
reg-names = "core_base";
|
|
iommus = <0x30 0x540 0x00>;
|
|
qcom,smmu-s1-bypass;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
interrupts = <0x00 0x1e9 0x00 0x00 0x82 0x00 0x00 0x1e6 0x00 0x00 0x1e8 0x00>;
|
|
interrupt-names = "dp_hs_phy_irq\0pwr_event_irq\0ss_phy_irq\0dm_hs_phy_irq";
|
|
USB3_GDSC-supply = <0x251>;
|
|
dpdm-supply = <0x252>;
|
|
qcom,use-pdc-interrupts;
|
|
clocks = <0x27 0x8d 0x27 0x15 0x27 0x0b 0x27 0x8f 0x27 0x91 0x27 0x92>;
|
|
clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk\0xo";
|
|
resets = <0x27 0x04>;
|
|
reset-names = "core_reset";
|
|
qcom,core-clk-rate = <0x7f28155>;
|
|
qcom,core-clk-rate-hs = <0x3f940ab>;
|
|
qcom,num-gsi-evt-buffs = <0x03>;
|
|
qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>;
|
|
qcom,gsi-disable-io-coherency;
|
|
qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>;
|
|
qcom,pm-qos-latency = <0x3e>;
|
|
qcom,msm-bus,name = "usb0";
|
|
qcom,msm-bus,num-cases = <0x04>;
|
|
qcom,msm-bus,num-paths = <0x03>;
|
|
qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x00 0x00 0x3d 0x2a4 0x00 0x00 0x01 0x247 0x00 0x00 0x3d 0x200 0xf4240 0x2625a0 0x3d 0x2a4 0x00 0x960 0x01 0x247 0x00 0x9c40 0x3d 0x200 0x3a980 0xaae60 0x3d 0x2a4 0x00 0x960 0x01 0x247 0x00 0x9c40 0x3d 0x200 0x01 0x01 0x3d 0x2a4 0x01 0x01 0x01 0x247 0x01 0x01>;
|
|
extcon = <0x253 0x80 0x254>;
|
|
phandle = <0x46e>;
|
|
|
|
dwc3@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0xa600000 0xcd00>;
|
|
interrupts = <0x00 0x85 0x00>;
|
|
usb-phy = <0x252 0x46f>;
|
|
linux,sysdev_is_parent;
|
|
snps,disable-clk-gating;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
snps,has-lpm-erratum;
|
|
snps,hird-threshold = [10];
|
|
snps,usb3_lpm_capable;
|
|
usb-core-id = <0x00>;
|
|
tx-fifo-resize;
|
|
maximum-speed = "high-speed";
|
|
dr_mode = "otg";
|
|
};
|
|
|
|
qcom,usbbam@a704000 {
|
|
compatible = "qcom,usb-bam-msm";
|
|
reg = <0xa704000 0x17000>;
|
|
interrupts = <0x00 0x84 0x00>;
|
|
qcom,usb-bam-fifo-baseaddr = <0x146a6000>;
|
|
qcom,usb-bam-num-pipes = <0x04>;
|
|
qcom,disable-clk-gating;
|
|
qcom,usb-bam-override-threshold = <0x4001>;
|
|
qcom,usb-bam-max-mbps-highspeed = <0x190>;
|
|
qcom,usb-bam-max-mbps-superspeed = <0xe10>;
|
|
qcom,reset-bam-on-connect;
|
|
|
|
qcom,pipe0 {
|
|
label = "ssusb-qdss-in-0";
|
|
qcom,usb-bam-mem-type = <0x02>;
|
|
qcom,dir = <0x01>;
|
|
qcom,pipe-num = <0x00>;
|
|
qcom,peer-bam = <0x00>;
|
|
qcom,peer-bam-physical-address = <0x6064000>;
|
|
qcom,src-bam-pipe-index = <0x00>;
|
|
qcom,dst-bam-pipe-index = <0x00>;
|
|
qcom,data-fifo-offset = <0x00>;
|
|
qcom,data-fifo-size = <0x1800>;
|
|
qcom,descriptor-fifo-offset = <0x1800>;
|
|
qcom,descriptor-fifo-size = <0x800>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qusb@88e2000 {
|
|
compatible = "qcom,qusb2phy-v2";
|
|
reg = <0x88e2000 0x400 0x780200 0x04 0x88e7014 0x04>;
|
|
reg-names = "qusb_phy_base\0efuse_addr\0refgen_north_bg_reg_addr";
|
|
qcom,efuse-bit-pos = <0x19>;
|
|
qcom,efuse-num-bits = <0x03>;
|
|
vdd-supply = <0x1a1>;
|
|
vdda18-supply = <0x1c7>;
|
|
vdda33-supply = <0x9c>;
|
|
qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>;
|
|
qcom,qusb-phy-reg-offset = <0x240 0x1a0 0x210 0x230 0xa8 0x254 0x198 0x27c 0x280 0x284 0x288 0x2a0>;
|
|
qcom,qusb-phy-init-seq = <0x23 0x210 0x03 0x04 0x7c 0x18c 0x80 0x2c 0x0a 0x184 0x19 0xb4 0x40 0x194 0x1c 0x198 0x21 0x214 0x08 0x220 0x58 0x224 0x72 0x240 0x2b 0x244 0xca 0x248 0x02 0x24c 0x03 0x250 0x30 0x23c 0x22 0x210>;
|
|
qcom,qusb-phy-host-init-seq = <0x23 0x210 0x03 0x04 0x7c 0x18c 0x80 0x2c 0x0a 0x184 0x19 0xb4 0x40 0x194 0x1c 0x198 0x21 0x214 0x08 0x220 0x58 0x224 0xf2 0x240 0x2b 0x244 0xca 0x248 0x02 0x24c 0x03 0x250 0x30 0x23c 0x22 0x210>;
|
|
phy_type = "utmi";
|
|
clocks = <0x2f 0x00 0x27 0x97>;
|
|
clock-names = "ref_clk_src\0cfg_ahb_clk";
|
|
resets = <0x27 0x09>;
|
|
reset-names = "phy_reset";
|
|
phandle = <0x252>;
|
|
qcom,diff_tune_host = <0x02>;
|
|
qcom,diff_tune_device = <0x04>;
|
|
};
|
|
|
|
ssphy@88e8000 {
|
|
compatible = "qcom,usb-ssphy-qmp-dp-combo";
|
|
reg = <0x88e8000 0x3000>;
|
|
reg-names = "qmp_phy_base";
|
|
vdd-supply = <0x1a1>;
|
|
qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>;
|
|
core-supply = <0x1a0>;
|
|
qcom,vbus-valid-override;
|
|
qcom,qmp-phy-init-seq = <0x1048 0x07 0x00 0x1080 0x14 0x00 0x1034 0x08 0x00 0x1138 0x30 0x00 0x103c 0x02 0x00 0x108c 0x08 0x00 0x115c 0x16 0x00 0x1164 0x01 0x00 0x113c 0x80 0x00 0x10b0 0x82 0x00 0x10b8 0xab 0x00 0x10bc 0xea 0x00 0x10c0 0x02 0x00 0x1060 0x06 0x00 0x1068 0x16 0x00 0x1070 0x36 0x00 0x10dc 0x00 0x00 0x10d8 0x3f 0x00 0x10f8 0x01 0x00 0x10f4 0xc9 0x00 0x1148 0x0a 0x00 0x10a0 0x00 0x00 0x109c 0x34 0x00 0x1098 0x15 0x00 0x1090 0x04 0x00 0x1154 0x00 0x00 0x1094 0x00 0x00 0x10f0 0x00 0x00 0x1040 0x0a 0x00 0x1010 0x01 0x00 0x101c 0x31 0x00 0x1020 0x01 0x00 0x1014 0x00 0x00 0x1018 0x00 0x00 0x1024 0x85 0x00 0x1028 0x07 0x00 0x1430 0x0b 0x00 0x14d4 0x0f 0x00 0x14d8 0x4e 0x00 0x14dc 0x18 0x00 0x14f8 0x77 0x00 0x14fc 0x80 0x00 0x1504 0x03 0x00 0x150c 0x16 0x00 0x1564 0x05 0x00 0x14c0 0x03 0x00 0x1830 0x0b 0x00 0x18d4 0x0f 0x00 0x18d8 0x4e 0x00 0x18dc 0x18 0x00 0x18f8 0x77 0x00 0x18fc 0x80 0x00 0x1904 0x03 0x00 0x190c 0x16 0x00 0x1964 0x05 0x00 0x18c0 0x03 0x00 0x1260 0x10 0x00 0x12a4 0x12 0x00 0x128c 0x16 0x00 0x1248 0x09 0x00 0x1244 0x06 0x00 0x1660 0x10 0x00 0x16a4 0x12 0x00 0x168c 0x16 0x00 0x1648 0x09 0x00 0x1644 0x06 0x00 0x1cc8 0x83 0x00 0x1ccc 0x09 0x00 0x1cd0 0xa2 0x00 0x1cd4 0x40 0x00 0x1cc4 0x02 0x00 0x1c80 0xd1 0x00 0x1c84 0x1f 0x00 0x1c88 0x47 0x00 0x1c64 0x1b 0x00 0x1434 0x75 0x00 0x1834 0x75 0x00 0x1dd8 0xba 0x00 0x1c0c 0x9f 0x00 0x1c10 0x9f 0x00 0x1c14 0xb7 0x00 0x1c18 0x4e 0x00 0x1c1c 0x65 0x00 0x1c20 0x6b 0x00 0x1c24 0x15 0x00 0x1c28 0x0d 0x00 0x1c2c 0x15 0x00 0x1c30 0x0d 0x00 0x1c34 0x15 0x00 0x1c38 0x0d 0x00 0x1c3c 0x15 0x00 0x1c40 0x1d 0x00 0x1c44 0x15 0x00 0x1c48 0x0d 0x00 0x1c4c 0x15 0x00 0x1c50 0x0d 0x00 0x1e0c 0x21 0x00 0x1e10 0x60 0x00 0x1c5c 0x02 0x00 0x1ca0 0x04 0x00 0x1c8c 0x44 0x00 0x1c70 0xe7 0x00 0x1c74 0x03 0x00 0x1c78 0x40 0x00 0x1c7c 0x00 0x00 0x1cb8 0x75 0x00 0x1cb0 0x86 0x00 0x1cbc 0x13 0x00 0x1cac 0x04 0x00 0xffffffff 0xffffffff 0x00>;
|
|
qcom,qmp-phy-reg-offset = <0x1d74 0x1cd8 0x1cdc 0x1c04 0x1c00 0x1c08 0xffff 0x2a18 0x08 0x04 0x1c 0x00 0x10 0x0c 0x1a0c>;
|
|
clocks = <0x27 0x93 0x27 0x96 0x2f 0x00 0x27 0x92 0x27 0x95 0x27 0x97>;
|
|
clock-names = "aux_clk\0pipe_clk\0ref_clk_src\0ref_clk\0com_aux_clk\0cfg_ahb_clk";
|
|
resets = <0x27 0x05 0x27 0x07>;
|
|
reset-names = "global_phy_reset\0phy_reset";
|
|
phandle = <0x255>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_audio_qmi_dev {
|
|
compatible = "qcom,usb-audio-qmi-dev";
|
|
iommus = <0x30 0x1b2f 0x00>;
|
|
qcom,usb-audio-stream-id = <0x0f>;
|
|
qcom,usb-audio-intr-num = <0x02>;
|
|
};
|
|
|
|
usb_nop_phy {
|
|
compatible = "usb-nop-xceiv";
|
|
phandle = <0x46f>;
|
|
};
|
|
|
|
qmi-tmd-devices {
|
|
compatible = "qcom,qmi-cooling-devices";
|
|
|
|
modem {
|
|
qcom,instance-id = <0x00>;
|
|
|
|
modem_pa {
|
|
qcom,qmi-dev-name = "pa";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x7a>;
|
|
};
|
|
|
|
modem_proc {
|
|
qcom,qmi-dev-name = "modem";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x7e>;
|
|
};
|
|
|
|
modem_current {
|
|
qcom,qmi-dev-name = "modem_current";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x470>;
|
|
};
|
|
|
|
modem_skin {
|
|
qcom,qmi-dev-name = "modem_skin";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x471>;
|
|
};
|
|
|
|
modem_vdd {
|
|
qcom,qmi-dev-name = "cpuv_restriction_cold";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x6c>;
|
|
};
|
|
};
|
|
|
|
adsp {
|
|
qcom,instance-id = <0x01>;
|
|
|
|
adsp_vdd {
|
|
qcom,qmi-dev-name = "cpuv_restriction_cold";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x6d>;
|
|
};
|
|
};
|
|
|
|
cdsp {
|
|
qcom,instance-id = <0x43>;
|
|
|
|
cdsp_vdd {
|
|
qcom,qmi-dev-name = "cpuv_restriction_cold";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x6e>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cxip-cdev@1fed000 {
|
|
compatible = "qcom,cxip-lm-cooling-device";
|
|
reg = <0x1fed000 0x8004>;
|
|
qcom,thermal-client-offset = <0x8000>;
|
|
qcom,bypass-client-list = <0x3004>;
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x72>;
|
|
};
|
|
|
|
qcom,msm-pcm {
|
|
compatible = "qcom,msm-pcm-dsp";
|
|
qcom,msm-pcm-dsp-id = <0x00>;
|
|
phandle = <0x256>;
|
|
};
|
|
|
|
qcom,msm-pcm-routing {
|
|
compatible = "qcom,msm-pcm-routing";
|
|
phandle = <0x260>;
|
|
};
|
|
|
|
qcom,msm-compr-dsp {
|
|
compatible = "qcom,msm-compr-dsp";
|
|
phandle = <0x261>;
|
|
};
|
|
|
|
qcom,msm-pcm-low-latency {
|
|
compatible = "qcom,msm-pcm-dsp";
|
|
qcom,msm-pcm-dsp-id = <0x01>;
|
|
qcom,msm-pcm-low-latency;
|
|
qcom,latency-level = "regular";
|
|
phandle = <0x257>;
|
|
};
|
|
|
|
qcom,msm-ultra-low-latency {
|
|
compatible = "qcom,msm-pcm-dsp";
|
|
qcom,msm-pcm-dsp-id = <0x02>;
|
|
qcom,msm-pcm-low-latency;
|
|
qcom,latency-level = "ultra";
|
|
phandle = <0x258>;
|
|
};
|
|
|
|
qcom,msm-pcm-dsp-noirq {
|
|
compatible = "qcom,msm-pcm-dsp-noirq";
|
|
qcom,msm-pcm-low-latency;
|
|
qcom,latency-level = "ultra";
|
|
phandle = <0x262>;
|
|
};
|
|
|
|
qcom,msm-transcode-loopback {
|
|
compatible = "qcom,msm-transcode-loopback";
|
|
phandle = <0x472>;
|
|
};
|
|
|
|
qcom,msm-compress-dsp {
|
|
compatible = "qcom,msm-compress-dsp";
|
|
phandle = <0x25c>;
|
|
};
|
|
|
|
qcom,msm-voip-dsp {
|
|
compatible = "qcom,msm-voip-dsp";
|
|
phandle = <0x259>;
|
|
};
|
|
|
|
qcom,msm-pcm-voice {
|
|
compatible = "qcom,msm-pcm-voice";
|
|
qcom,destroy-cvd;
|
|
phandle = <0x25a>;
|
|
};
|
|
|
|
qcom,msm-stub-codec {
|
|
compatible = "qcom,msm-stub-codec";
|
|
phandle = <0x473>;
|
|
};
|
|
|
|
qcom,msm-dai-fe {
|
|
compatible = "qcom,msm-dai-fe";
|
|
};
|
|
|
|
qcom,msm-pcm-afe {
|
|
compatible = "qcom,msm-pcm-afe";
|
|
phandle = <0x25e>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-hdmi {
|
|
compatible = "qcom,msm-dai-q6-hdmi";
|
|
qcom,msm-dai-q6-dev-id = <0x08>;
|
|
phandle = <0x474>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-hdmi_ms {
|
|
compatible = "qcom,msm-dai-q6-hdmi";
|
|
qcom,msm-dai-q6-dev-id = <0x6002>;
|
|
phandle = <0x475>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-dp {
|
|
compatible = "qcom,msm-dai-q6-hdmi";
|
|
qcom,msm-dai-q6-dev-id = <0x6020>;
|
|
phandle = <0x263>;
|
|
};
|
|
|
|
qcom,msm-pcm-loopback {
|
|
compatible = "qcom,msm-pcm-loopback";
|
|
phandle = <0x25b>;
|
|
};
|
|
|
|
qcom,msm-pcm-loopback-low-latency {
|
|
compatible = "qcom,msm-pcm-loopback";
|
|
qcom,msm-pcm-loopback-low-latency;
|
|
phandle = <0x476>;
|
|
};
|
|
|
|
qcom,msm-pcm-dtmf {
|
|
compatible = "qcom,msm-pcm-dtmf";
|
|
phandle = <0x477>;
|
|
};
|
|
|
|
qcom,msm-dai-mi2s {
|
|
compatible = "qcom,msm-dai-mi2s";
|
|
phandle = <0x478>;
|
|
|
|
qcom,msm-dai-q6-mi2s-prim {
|
|
compatible = "qcom,msm-dai-q6-mi2s";
|
|
qcom,msm-dai-q6-mi2s-dev-id = <0x00>;
|
|
qcom,msm-mi2s-rx-lines = <0x03>;
|
|
qcom,msm-mi2s-tx-lines = <0x00>;
|
|
phandle = <0x264>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-mi2s-sec {
|
|
compatible = "qcom,msm-dai-q6-mi2s";
|
|
qcom,msm-dai-q6-mi2s-dev-id = <0x01>;
|
|
qcom,msm-mi2s-rx-lines = <0x02>;
|
|
qcom,msm-mi2s-tx-lines = <0x01>;
|
|
phandle = <0x265>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-mi2s-tert {
|
|
compatible = "qcom,msm-dai-q6-mi2s";
|
|
qcom,msm-dai-q6-mi2s-dev-id = <0x02>;
|
|
qcom,msm-mi2s-rx-lines = <0x00>;
|
|
qcom,msm-mi2s-tx-lines = <0x03>;
|
|
phandle = <0x266>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-mi2s-quat {
|
|
compatible = "qcom,msm-dai-q6-mi2s";
|
|
qcom,msm-dai-q6-mi2s-dev-id = <0x03>;
|
|
qcom,msm-mi2s-rx-lines = <0x01>;
|
|
qcom,msm-mi2s-tx-lines = <0x02>;
|
|
phandle = <0x267>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-mi2s-quin {
|
|
compatible = "qcom,msm-dai-q6-mi2s";
|
|
qcom,msm-dai-q6-mi2s-dev-id = <0x04>;
|
|
qcom,msm-mi2s-rx-lines = <0x01>;
|
|
qcom,msm-mi2s-tx-lines = <0x02>;
|
|
phandle = <0x268>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-mi2s-senary {
|
|
compatible = "qcom,msm-dai-q6-mi2s";
|
|
qcom,msm-dai-q6-mi2s-dev-id = <0x06>;
|
|
qcom,msm-mi2s-rx-lines = <0x00>;
|
|
qcom,msm-mi2s-tx-lines = <0x03>;
|
|
phandle = <0x479>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-q6-meta-mi2s-prim {
|
|
compatible = "qcom,msm-dai-q6-meta-mi2s";
|
|
qcom,msm-dai-q6-meta-mi2s-dev-id = <0x1300>;
|
|
qcom,msm-mi2s-num-members = <0x04>;
|
|
qcom,msm-mi2s-member-id = <0x00 0x01 0x02 0x03>;
|
|
qcom,msm-mi2s-rx-lines = <0xff 0x0f 0x03 0x03>;
|
|
phandle = <0x47a>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-meta-mi2s-sec {
|
|
compatible = "qcom,msm-dai-q6-meta-mi2s";
|
|
qcom,msm-dai-q6-meta-mi2s-dev-id = <0x1302>;
|
|
qcom,msm-mi2s-num-members = <0x04>;
|
|
qcom,msm-mi2s-member-id = <0x00 0x01 0x02 0x03>;
|
|
qcom,msm-mi2s-rx-lines = <0xff 0x0f 0x03 0x03>;
|
|
phandle = <0x47b>;
|
|
};
|
|
|
|
qcom,msm-dai-cdc-dma {
|
|
compatible = "qcom,msm-dai-cdc-dma";
|
|
phandle = <0x47c>;
|
|
|
|
qcom,msm-dai-wsa-cdc-dma-0-rx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb000>;
|
|
phandle = <0x288>;
|
|
};
|
|
|
|
qcom,msm-dai-wsa-cdc-dma-0-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb001>;
|
|
phandle = <0x289>;
|
|
};
|
|
|
|
qcom,msm-dai-wsa-cdc-dma-1-rx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb002>;
|
|
phandle = <0x28a>;
|
|
};
|
|
|
|
qcom,msm-dai-wsa-cdc-dma-1-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb003>;
|
|
phandle = <0x28b>;
|
|
};
|
|
|
|
qcom,msm-dai-wsa-cdc-dma-2-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb005>;
|
|
phandle = <0x28c>;
|
|
};
|
|
|
|
qcom,msm-dai-va-cdc-dma-0-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb021>;
|
|
phandle = <0x47d>;
|
|
};
|
|
|
|
qcom,msm-dai-va-cdc-dma-1-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb023>;
|
|
phandle = <0x47e>;
|
|
};
|
|
|
|
qcom,msm-dai-va-cdc-dma-2-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb025>;
|
|
phandle = <0x47f>;
|
|
};
|
|
|
|
qcom,msm-dai-rx-cdc-dma-0-rx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb030>;
|
|
phandle = <0x28d>;
|
|
};
|
|
|
|
qcom,msm-dai-rx-cdc-dma-1-rx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb032>;
|
|
phandle = <0x28f>;
|
|
};
|
|
|
|
qcom,msm-dai-rx-cdc-dma-2-rx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb034>;
|
|
phandle = <0x291>;
|
|
};
|
|
|
|
qcom,msm-dai-rx-cdc-dma-3-rx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb036>;
|
|
phandle = <0x293>;
|
|
};
|
|
|
|
qcom,msm-dai-rx-cdc-dma-4-rx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb038>;
|
|
phandle = <0x295>;
|
|
};
|
|
|
|
qcom,msm-dai-rx-cdc-dma-5-rx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb03a>;
|
|
phandle = <0x297>;
|
|
};
|
|
|
|
qcom,msm-dai-rx-cdc-dma-6-rx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb03c>;
|
|
phandle = <0x299>;
|
|
};
|
|
|
|
qcom,msm-dai-rx-cdc-dma-7-rx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb03e>;
|
|
phandle = <0x29a>;
|
|
};
|
|
|
|
qcom,msm-dai-tx-cdc-dma-0-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb031>;
|
|
phandle = <0x28e>;
|
|
};
|
|
|
|
qcom,msm-dai-tx-cdc-dma-1-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb033>;
|
|
phandle = <0x290>;
|
|
};
|
|
|
|
qcom,msm-dai-tx-cdc-dma-2-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb035>;
|
|
phandle = <0x292>;
|
|
};
|
|
|
|
qcom,msm-dai-tx-cdc-dma-3-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb037>;
|
|
phandle = <0x294>;
|
|
};
|
|
|
|
qcom,msm-dai-tx-cdc-dma-4-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb039>;
|
|
phandle = <0x296>;
|
|
};
|
|
|
|
qcom,msm-dai-tx-cdc-dma-5-tx {
|
|
compatible = "qcom,msm-dai-cdc-dma-dev";
|
|
qcom,msm-dai-cdc-dma-dev-id = <0xb03b>;
|
|
phandle = <0x298>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-lsm-client {
|
|
compatible = "qcom,msm-lsm-client";
|
|
phandle = <0x25f>;
|
|
};
|
|
|
|
qcom,msm-dai-q6 {
|
|
compatible = "qcom,msm-dai-q6";
|
|
|
|
qcom,msm-dai-q6-sb-0-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4000>;
|
|
phandle = <0x480>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-0-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4001>;
|
|
phandle = <0x481>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-1-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4002>;
|
|
phandle = <0x482>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-1-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4003>;
|
|
phandle = <0x483>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-2-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4004>;
|
|
phandle = <0x484>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-2-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4005>;
|
|
phandle = <0x485>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-3-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4006>;
|
|
phandle = <0x486>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-3-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4007>;
|
|
phandle = <0x487>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-4-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4008>;
|
|
phandle = <0x488>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-4-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4009>;
|
|
phandle = <0x489>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-5-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x400b>;
|
|
phandle = <0x48a>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-5-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x400a>;
|
|
phandle = <0x48b>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-6-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x400c>;
|
|
phandle = <0x48c>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-7-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x400e>;
|
|
phandle = <0x276>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-7-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x400f>;
|
|
qcom,msm-dai-q6-slim-dev-id = <0x00>;
|
|
phandle = <0x277>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-8-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4010>;
|
|
phandle = <0x279>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-8-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4011>;
|
|
qcom,msm-dai-q6-slim-dev-id = <0x00>;
|
|
phandle = <0x278>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-9-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4012>;
|
|
phandle = <0x48d>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-sb-9-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x4013>;
|
|
phandle = <0x48e>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-bt-sco-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x3000>;
|
|
phandle = <0x48f>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-bt-sco-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x3001>;
|
|
phandle = <0x490>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-int-fm-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x3004>;
|
|
phandle = <0x491>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-int-fm-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x3005>;
|
|
phandle = <0x492>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-be-afe-pcm-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0xe0>;
|
|
phandle = <0x26e>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-be-afe-pcm-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0xe1>;
|
|
phandle = <0x26f>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-afe-proxy-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0xf1>;
|
|
phandle = <0x270>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-afe-proxy-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0xf0>;
|
|
phandle = <0x271>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-incall-record-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x8003>;
|
|
phandle = <0x272>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-incall-record-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x8004>;
|
|
phandle = <0x273>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-incall-music-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x8005>;
|
|
phandle = <0x274>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-incall-music-2-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x8002>;
|
|
phandle = <0x275>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-proxy-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x2002>;
|
|
phandle = <0x27a>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-proxy-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x2003>;
|
|
phandle = <0x27b>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-usb-audio-rx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x7000>;
|
|
phandle = <0x27c>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-usb-audio-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x7001>;
|
|
phandle = <0x27d>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-pcm-hostless {
|
|
compatible = "qcom,msm-pcm-hostless";
|
|
phandle = <0x25d>;
|
|
};
|
|
|
|
qcom,msm-audio-apr {
|
|
compatible = "qcom,msm-audio-apr";
|
|
qcom,subsys-name = "apr_adsp";
|
|
phandle = <0x493>;
|
|
|
|
qcom,msm-audio-ion {
|
|
compatible = "qcom,msm-audio-ion";
|
|
qcom,smmu-version = <0x02>;
|
|
qcom,smmu-enabled;
|
|
iommus = <0x30 0x1b21 0x00>;
|
|
qcom,smmu-sid-mask = <0x00 0x0f>;
|
|
phandle = <0x494>;
|
|
};
|
|
|
|
qcom,q6core-audio {
|
|
compatible = "qcom,q6core-audio";
|
|
phandle = <0x495>;
|
|
|
|
bolero-cdc {
|
|
compatible = "qcom,bolero-codec";
|
|
phandle = <0x496>;
|
|
qcom,num-macros = <0x03>;
|
|
qcom,va-without-decimation;
|
|
slew_rate_reg1 = <0x62b6f000 0x00>;
|
|
slew_rate_reg2 = <0x62b6f004 0x00>;
|
|
slew_rate_val1 = <0x3333 0x00>;
|
|
slew_rate_val2 = <0x0f 0x00>;
|
|
|
|
va-macro@62f20000 {
|
|
phandle = <0x5aa>;
|
|
compatible = "qcom,va-macro";
|
|
reg = <0x62f20000 0x00>;
|
|
clock-names = "va_core_clk";
|
|
clocks = <0x507 0x00>;
|
|
};
|
|
|
|
tx-macro@62ec0000 {
|
|
phandle = <0x5a4>;
|
|
compatible = "qcom,tx-macro";
|
|
reg = <0x62ec0000 0x00>;
|
|
clock-names = "tx_core_clk\0tx_npl_clk";
|
|
clocks = <0x4fc 0x00 0x4fd 0x00>;
|
|
qcom,tx-swr-gpios = <0x4fe>;
|
|
qcom,tx-dmic-sample-rate = <0x249f00>;
|
|
|
|
tx_swr_master {
|
|
phandle = <0x5a5>;
|
|
compatible = "qcom,swr-mstr";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,swr_master_id = <0x03>;
|
|
swrm-io-base = <0x62ed0000 0x00>;
|
|
interrupts = <0x00 0x128 0x00 0x00 0x1f4 0x00>;
|
|
interrupt-names = "swr_master_irq\0swr_wake_irq";
|
|
qcom,swr-wakeup-required = <0x00>;
|
|
qcom,swr-num-ports = <0x05>;
|
|
qcom,swr-port-mapping = <0x01 0x21 0x0f 0x02 0x12 0x01 0x02 0x13 0x02 0x03 0x14 0x01 0x03 0x15 0x02 0x04 0x16 0x01 0x04 0x17 0x02 0x04 0x18 0x04 0x04 0x19 0x08 0x05 0x1a 0x01 0x05 0x1b 0x02 0x05 0x1c 0x04 0x05 0x1d 0x08>;
|
|
qcom,swr-num-dev = <0x01>;
|
|
qcom,swr-clock-stop-mode0 = <0x01>;
|
|
qcom,swr-mstr-irq-wakeup-capable = <0x01>;
|
|
|
|
wcd937x-tx-slave {
|
|
compatible = "qcom,wcd937x-slave";
|
|
reg = <0x00 0x1170223>;
|
|
phandle = <0x50a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
rx-macro@62ee0000 {
|
|
phandle = <0x5a6>;
|
|
compatible = "qcom,rx-macro";
|
|
reg = <0x62ee0000 0x00>;
|
|
clock-names = "rx_core_clk\0rx_npl_clk";
|
|
clocks = <0x4ff 0x00 0x500 0x00>;
|
|
qcom,rx-swr-gpios = <0x501>;
|
|
qcom,rx_mclk_mode_muxsel = <0x62c25020>;
|
|
qcom,rx-bcl-pmic-params = [00 00 1e];
|
|
|
|
rx_swr_master {
|
|
phandle = <0x5a7>;
|
|
compatible = "qcom,swr-mstr";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,swr_master_id = <0x02>;
|
|
swrm-io-base = <0x62ef0000 0x00>;
|
|
interrupts = <0x00 0x129 0x00>;
|
|
interrupt-names = "swr_master_irq";
|
|
qcom,swr-num-ports = <0x05>;
|
|
qcom,swr-port-mapping = <0x01 0x09 0x01 0x01 0x0a 0x02 0x02 0x0d 0x01 0x03 0x0b 0x01 0x03 0x0c 0x02 0x04 0x0e 0x01 0x05 0x0f 0x01 0x05 0x10 0x02>;
|
|
qcom,swr-num-dev = <0x01>;
|
|
qcom,swr-clock-stop-mode0 = <0x01>;
|
|
|
|
wcd937x-rx-slave {
|
|
compatible = "qcom,wcd937x-slave";
|
|
reg = <0x00 0x1170224>;
|
|
phandle = <0x509>;
|
|
};
|
|
};
|
|
};
|
|
|
|
wsa-macro@62f00000 {
|
|
phandle = <0x5a8>;
|
|
compatible = "qcom,wsa-macro";
|
|
reg = <0x62f00000 0x00>;
|
|
clock-names = "wsa_core_clk\0wsa_npl_clk";
|
|
clocks = <0x502 0x00 0x503 0x00>;
|
|
qcom,wsa-swr-gpios = <0x504>;
|
|
qcom,wsa-bcl-pmic-params = [00 00 1e];
|
|
status = "disabled";
|
|
|
|
wsa_swr_master {
|
|
phandle = <0x5a9>;
|
|
compatible = "qcom,swr-mstr";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,swr_master_id = <0x01>;
|
|
swrm-io-base = <0x62f10000 0x00>;
|
|
interrupts = <0x00 0x127 0x00>;
|
|
interrupt-names = "swr_master_irq";
|
|
qcom,swr-num-ports = <0x08>;
|
|
qcom,swr-port-mapping = <0x01 0x01 0x01 0x02 0x03 0x0f 0x03 0x02 0x03 0x04 0x05 0x01 0x05 0x07 0x0f 0x06 0x06 0x03 0x07 0x04 0x03 0x08 0x08 0x03>;
|
|
qcom,swr-num-dev = <0x02>;
|
|
status = "disabled";
|
|
|
|
wsa881x@20170211 {
|
|
compatible = "qcom,wsa881x";
|
|
reg = <0x00 0x20170211>;
|
|
qcom,spkr-sd-n-node = <0x505>;
|
|
qcom,bolero-handle = <0x496>;
|
|
phandle = <0x50e>;
|
|
};
|
|
|
|
wsa881x@20170212 {
|
|
compatible = "qcom,wsa881x";
|
|
reg = <0x00 0x20170212>;
|
|
qcom,spkr-sd-n-node = <0x506>;
|
|
qcom,bolero-handle = <0x496>;
|
|
phandle = <0x50f>;
|
|
};
|
|
|
|
wsa881x@21170213 {
|
|
compatible = "qcom,wsa881x";
|
|
reg = <0x00 0x21170213>;
|
|
qcom,spkr-sd-n-node = <0x505>;
|
|
qcom,bolero-handle = <0x496>;
|
|
phandle = <0x510>;
|
|
};
|
|
|
|
wsa881x@21170214 {
|
|
compatible = "qcom,wsa881x";
|
|
reg = <0x00 0x21170214>;
|
|
qcom,spkr-sd-n-node = <0x506>;
|
|
qcom,bolero-handle = <0x496>;
|
|
phandle = <0x511>;
|
|
};
|
|
};
|
|
};
|
|
|
|
wcd937x-codec {
|
|
compatible = "qcom,wcd937x-codec";
|
|
qcom,rx_swr_ch_map = <0x00 0x09 0x01 0x00 0x09 0x00 0x0a 0x02 0x00 0x0a 0x01 0x0d 0x01 0x00 0x0d 0x02 0x0b 0x01 0x00 0x0b 0x02 0x0c 0x02 0x00 0x0c 0x03 0x0e 0x01 0x00 0x0e 0x04 0x0f 0x01 0x00 0x0f 0x04 0x10 0x02 0x00 0x10>;
|
|
qcom,tx_swr_ch_map = <0x00 0x12 0x01 0x00 0x12 0x01 0x13 0x01 0x00 0x14 0x01 0x14 0x02 0x00 0x15 0x02 0x16 0x01 0x00 0x16 0x02 0x17 0x02 0x00 0x17 0x02 0x11 0x04 0x00 0x18 0x03 0x18 0x01 0x00 0x1a 0x03 0x19 0x02 0x00 0x1b 0x03 0x1a 0x04 0x00 0x1c 0x03 0x1b 0x08 0x00 0x1d>;
|
|
qcom,wcd-rst-gpio-node = <0x508>;
|
|
qcom,rx-slave = <0x509>;
|
|
qcom,tx-slave = <0x50a>;
|
|
cdc-vdd-ldo-rxtx-supply = <0x31>;
|
|
qcom,cdc-vdd-ldo-rxtx-voltage = <0x1b7740 0x1b7740>;
|
|
qcom,cdc-vdd-ldo-rxtx-current = <0x61a8>;
|
|
cdc-vddpx-1-supply = <0x31>;
|
|
qcom,cdc-vddpx-1-voltage = <0x1b7740 0x1b7740>;
|
|
qcom,cdc-vddpx-1-current = <0x2710>;
|
|
cdc-vdd-buck-supply = <0x3f1>;
|
|
qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>;
|
|
qcom,cdc-vdd-buck-current = <0x9eb10>;
|
|
cdc-vdd-mic-bias-supply = <0x3fc>;
|
|
qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K";
|
|
qcom,cdc-vdd-mic-bias-current = <0x61a8>;
|
|
qcom,cdc-micbias1-mv = <0x708>;
|
|
qcom,cdc-micbias2-mv = <0xaf0>;
|
|
qcom,cdc-micbias3-mv = <0x708>;
|
|
qcom,cdc-static-supplies = "cdc-vdd-ldo-rxtx\0cdc-vddpx-1\0cdc-vdd-mic-bias";
|
|
qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
|
|
imp-table = <0x50b 0x00 0x05 0x06 0x50b 0x06 0x15 0x06 0x50b 0x16 0x24 0x06 0x50b 0x25 0x64 0x06 0x50b 0x65 0xa0 0x0a 0x50b 0xa1 0x190 0x0b 0x50b 0x191 0x7d0 0x0b 0x50b 0x7d1 0x7fffffff 0x06>;
|
|
phandle = <0x512>;
|
|
};
|
|
|
|
imp_list {
|
|
#list-imp-cells = <0x03>;
|
|
phandle = <0x50b>;
|
|
};
|
|
};
|
|
|
|
sound {
|
|
compatible = "qcom,sm6150-asoc-snd";
|
|
qcom,mi2s-audio-intf = <0x01>;
|
|
qcom,auxpcm-audio-intf = <0x01>;
|
|
qcom,wcn-btfm = <0x01>;
|
|
asoc-platform = <0x256 0x257 0x258 0x259 0x25a 0x25b 0x25c 0x25d 0x25e 0x25f 0x260 0x261 0x262 0x531>;
|
|
asoc-platform-names = "msm-pcm-dsp.0\0msm-pcm-dsp.1\0msm-pcm-dsp.2\0msm-voip-dsp\0msm-pcm-voice\0msm-pcm-loopback\0msm-compress-dsp\0msm-pcm-hostless\0msm-pcm-afe\0msm-lsm-client\0msm-pcm-routing\0msm-compr-dsp\0msm-pcm-dsp-noirq\0q6audio-adaptation";
|
|
asoc-cpu = <0x263 0x264 0x265 0x266 0x267 0x268 0x269 0x26a 0x26b 0x26c 0x26d 0x26e 0x26f 0x270 0x271 0x272 0x273 0x274 0x275 0x276 0x277 0x278 0x279 0x27a 0x27b 0x27c 0x27d 0x27e 0x27f 0x280 0x281 0x282 0x283 0x284 0x285 0x286 0x287 0x288 0x289 0x28a 0x28b 0x28c 0x28d 0x28e 0x28f 0x290 0x291 0x292 0x293 0x294 0x295 0x296 0x297 0x298 0x299 0x29a>;
|
|
asoc-cpu-names = "msm-dai-q6-dp.24608\0msm-dai-q6-mi2s.0\0msm-dai-q6-mi2s.1\0msm-dai-q6-mi2s.2\0msm-dai-q6-mi2s.3\0msm-dai-q6-mi2s.4\0msm-dai-q6-auxpcm.1\0msm-dai-q6-auxpcm.2\0msm-dai-q6-auxpcm.3\0msm-dai-q6-auxpcm.4\0msm-dai-q6-auxpcm.5\0msm-dai-q6-dev.224\0msm-dai-q6-dev.225\0msm-dai-q6-dev.241\0msm-dai-q6-dev.240\0msm-dai-q6-dev.32771\0msm-dai-q6-dev.32772\0msm-dai-q6-dev.32773\0msm-dai-q6-dev.32770\0msm-dai-q6-dev.16398\0msm-dai-q6-dev.16399\0msm-dai-q6-dev.16401\0msm-dai-q6-dev.16400\0msm-dai-q6-dev.8194\0msm-dai-q6-dev.8195\0msm-dai-q6-dev.28672\0msm-dai-q6-dev.28673\0msm-dai-q6-tdm.36864\0msm-dai-q6-tdm.36865\0msm-dai-q6-tdm.36880\0msm-dai-q6-tdm.36881\0msm-dai-q6-tdm.36896\0msm-dai-q6-tdm.36897\0msm-dai-q6-tdm.36912\0msm-dai-q6-tdm.36913\0msm-dai-q6-tdm.36928\0msm-dai-q6-tdm.36929\0msm-dai-cdc-dma-dev.45056\0msm-dai-cdc-dma-dev.45057\0msm-dai-cdc-dma-dev.45058\0msm-dai-cdc-dma-dev.45059\0msm-dai-cdc-dma-dev.45061\0msm-dai-cdc-dma-dev.45104\0msm-dai-cdc-dma-dev.45105\0msm-dai-cdc-dma-dev.45106\0msm-dai-cdc-dma-dev.45107\0msm-dai-cdc-dma-dev.45108\0msm-dai-cdc-dma-dev.45109\0msm-dai-cdc-dma-dev.45110\0msm-dai-cdc-dma-dev.45111\0msm-dai-cdc-dma-dev.45112\0msm-dai-cdc-dma-dev.45113\0msm-dai-cdc-dma-dev.45114\0msm-dai-cdc-dma-dev.45115\0msm-dai-cdc-dma-dev.45116\0msm-dai-cdc-dma-dev.45118";
|
|
fsa4480-i2c-handle = <0x29b>;
|
|
phandle = <0x49e>;
|
|
qcom,model = "sm6150-idp-snd-card";
|
|
qcom,msm-mi2s-master = <0x01 0x01 0x01 0x01 0x01>;
|
|
qcom,ext-disp-audio-rx = <0x01>;
|
|
qcom,audio-routing = "AMIC1\0MIC BIAS1\0MIC BIAS1\0Analog Mic1\0AMIC2\0MIC BIAS2\0MIC BIAS2\0Analog Mic2\0AMIC3\0MIC BIAS3\0MIC BIAS3\0Analog Mic3\0IN1_HPHL\0HPHL_OUT\0IN2_HPHR\0HPHR_OUT\0IN3_AUX\0AUX_OUT\0TX SWR_ADC0\0ADC1_OUTPUT\0TX SWR_ADC2\0ADC2_OUTPUT\0RX_TX DEC0_INP\0TX DEC0 MUX\0RX_TX DEC1_INP\0TX DEC1 MUX\0RX_TX DEC2_INP\0TX DEC2 MUX\0RX_TX DEC3_INP\0TX DEC3 MUX";
|
|
qcom,msm-mbhc-hphl-swh = <0x01>;
|
|
qcom,msm-mbhc-gnd-swh = <0x00>;
|
|
qcom,cdc-dmic01-gpios = <0x00>;
|
|
qcom,cdc-dmic23-gpios = <0x00>;
|
|
asoc-codec = <0x473 0x496 0x369>;
|
|
asoc-codec-names = "msm-stub-codec.1\0bolero_codec\0msm-ext-disp-audio-codec-rx";
|
|
qcom,wsa-max-devs = <0x00>;
|
|
qcom,wsa-devs = <0x50e 0x50f 0x510 0x511>;
|
|
qcom,wsa-aux-dev-prefix = "SpkrLeft\0SpkrRight\0SpkrLeft\0SpkrRight";
|
|
qcom,codec-max-aux-devs = <0x01>;
|
|
qcom,codec-aux-devs = <0x512>;
|
|
qcom,msm_audio_ssr_devs = <0x493 0x495 0x513 0x496>;
|
|
qcom,msm-mbhc-hs-mic-max-threshold-mv = <0x270f>;
|
|
qcom,msm-mbhc-hs-mic-min-threshold-mv = <0x280>;
|
|
qcom,fm-lna-gpios = <0x16c 0x15 0x00>;
|
|
mbhc-button-thres = <0x532 0x0d 0x3f 0x532 0x58 0x8a 0x532 0x7d 0x7d 0x532 0xe1 0xe1 0x532 0x1db 0x1db 0x532 0x26c 0x26c 0x532 0x26c 0x26c 0x532 0x26c 0x26c>;
|
|
qcom,sec-mi2s-gpios = <0x533>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,msm-pri-auxpcm {
|
|
compatible = "qcom,msm-auxpcm-dev";
|
|
qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;
|
|
qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;
|
|
qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;
|
|
qcom,msm-auxpcm-interface = "primary";
|
|
qcom,msm-cpudai-afe-clk-ver = <0x02>;
|
|
phandle = <0x269>;
|
|
};
|
|
|
|
qcom,msm-sec-auxpcm {
|
|
compatible = "qcom,msm-auxpcm-dev";
|
|
qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;
|
|
qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;
|
|
qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;
|
|
qcom,msm-auxpcm-interface = "secondary";
|
|
qcom,msm-cpudai-afe-clk-ver = <0x02>;
|
|
phandle = <0x26a>;
|
|
};
|
|
|
|
qcom,msm-tert-auxpcm {
|
|
compatible = "qcom,msm-auxpcm-dev";
|
|
qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;
|
|
qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;
|
|
qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;
|
|
qcom,msm-auxpcm-interface = "tertiary";
|
|
qcom,msm-cpudai-afe-clk-ver = <0x02>;
|
|
phandle = <0x26b>;
|
|
};
|
|
|
|
qcom,msm-quat-auxpcm {
|
|
compatible = "qcom,msm-auxpcm-dev";
|
|
qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;
|
|
qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;
|
|
qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;
|
|
qcom,msm-auxpcm-interface = "quaternary";
|
|
qcom,msm-cpudai-afe-clk-ver = <0x02>;
|
|
phandle = <0x26c>;
|
|
};
|
|
|
|
qcom,msm-quin-auxpcm {
|
|
compatible = "qcom,msm-auxpcm-dev";
|
|
qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;
|
|
qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;
|
|
qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;
|
|
qcom,msm-auxpcm-interface = "quinary";
|
|
qcom,msm-cpudai-afe-clk-ver = <0x02>;
|
|
phandle = <0x26d>;
|
|
};
|
|
|
|
qcom,msm-sen-auxpcm {
|
|
compatible = "qcom,msm-auxpcm-dev";
|
|
qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>;
|
|
qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>;
|
|
qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>;
|
|
qcom,msm-cpudai-auxpcm-data = <0x00 0x00>;
|
|
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;
|
|
qcom,msm-auxpcm-interface = "senary";
|
|
qcom,msm-cpudai-afe-clk-ver = <0x02>;
|
|
phandle = <0x49f>;
|
|
};
|
|
|
|
qcom,msm-hdmi-dba-codec-rx {
|
|
compatible = "qcom,msm-hdmi-dba-codec-rx";
|
|
qcom,dba-bridge-chip = "adv7533";
|
|
phandle = <0x4a0>;
|
|
};
|
|
|
|
qcom,msm-adsp-loader {
|
|
status = "ok";
|
|
compatible = "qcom,adsp-loader";
|
|
qcom,adsp-state = <0x00>;
|
|
};
|
|
|
|
qcom,msm-dai-tdm-pri-rx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9100>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9000>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4a1>;
|
|
|
|
qcom,msm-dai-q6-tdm-pri-rx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9000>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x27e>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-pri-tx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9101>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9001>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4a2>;
|
|
|
|
qcom,msm-dai-q6-tdm-pri-tx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9001>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x27f>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-sec-rx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9110>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9010>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4a3>;
|
|
|
|
qcom,msm-dai-q6-tdm-sec-rx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9010>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x280>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-sec-tx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9111>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9011>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4a4>;
|
|
|
|
qcom,msm-dai-q6-tdm-sec-tx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9011>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x281>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-tert-rx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9120>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9020>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4a5>;
|
|
|
|
qcom,msm-dai-q6-tdm-tert-rx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9020>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x282>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-tert-tx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9121>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9021>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4a6>;
|
|
|
|
qcom,msm-dai-q6-tdm-tert-tx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9021>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x283>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-quat-rx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9130>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9030>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4a7>;
|
|
|
|
qcom,msm-dai-q6-tdm-quat-rx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9030>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x284>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-quat-tx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9131>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9031>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4a8>;
|
|
|
|
qcom,msm-dai-q6-tdm-quat-tx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9031>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x285>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-quin-rx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9140>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9040>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4a9>;
|
|
|
|
qcom,msm-dai-q6-tdm-quin-rx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9040>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x286>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-quin-tx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9141>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9041>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4aa>;
|
|
|
|
qcom,msm-dai-q6-tdm-quin-tx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9041>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x287>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-sen-rx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9150>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9050>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4ab>;
|
|
|
|
qcom,msm-dai-q6-tdm-sen-rx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9050>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x4ac>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-tdm-sen-tx {
|
|
compatible = "qcom,msm-dai-tdm";
|
|
qcom,msm-cpudai-tdm-group-id = <0x9151>;
|
|
qcom,msm-cpudai-tdm-group-num-ports = <0x01>;
|
|
qcom,msm-cpudai-tdm-group-port-id = <0x9051>;
|
|
qcom,msm-cpudai-tdm-clk-rate = <0x177000>;
|
|
qcom,msm-cpudai-tdm-clk-internal = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-mode = <0x01>;
|
|
qcom,msm-cpudai-tdm-sync-src = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-out = <0x00>;
|
|
qcom,msm-cpudai-tdm-invert-sync = <0x01>;
|
|
qcom,msm-cpudai-tdm-data-delay = <0x01>;
|
|
phandle = <0x4ad>;
|
|
|
|
qcom,msm-dai-q6-tdm-sen-tx-0 {
|
|
compatible = "qcom,msm-dai-q6-tdm";
|
|
qcom,msm-cpudai-tdm-dev-id = <0x9051>;
|
|
qcom,msm-cpudai-tdm-data-align = <0x00>;
|
|
phandle = <0x4ae>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-dai-q6-spdif-pri-rx {
|
|
compatible = "qcom,msm-dai-q6-spdif";
|
|
qcom,msm-dai-q6-dev-id = <0x5000>;
|
|
phandle = <0x4af>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-spdif-pri-tx {
|
|
compatible = "qcom,msm-dai-q6-spdif";
|
|
qcom,msm-dai-q6-dev-id = <0x5001>;
|
|
phandle = <0x4b0>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-spdif-sec-rx {
|
|
compatible = "qcom,msm-dai-q6-spdif";
|
|
qcom,msm-dai-q6-dev-id = <0x5002>;
|
|
phandle = <0x4b1>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-spdif-sec-tx {
|
|
compatible = "qcom,msm-dai-q6-spdif";
|
|
qcom,msm-dai-q6-dev-id = <0x5003>;
|
|
phandle = <0x4b2>;
|
|
};
|
|
|
|
qcom,msm-dai-q6-afe-loopback-tx {
|
|
compatible = "qcom,msm-dai-q6-dev";
|
|
qcom,msm-dai-q6-dev-id = <0x6001>;
|
|
phandle = <0x4b3>;
|
|
};
|
|
|
|
qcom,avtimer@62CF7000 {
|
|
compatible = "qcom,avtimer";
|
|
reg = <0x62cf700c 0x04 0x62cf7010 0x04>;
|
|
reg-names = "avtimer_lsb_addr\0avtimer_msb_addr";
|
|
qcom,clk-div = <0xc0>;
|
|
qcom,clk-mult = <0x0a>;
|
|
};
|
|
|
|
lpass_core_hw_vote {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <0x09>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x4b4>;
|
|
};
|
|
|
|
qcom,kgsl-hyp {
|
|
compatible = "qcom,pil-tz-generic";
|
|
qcom,pas-id = <0x0d>;
|
|
qcom,firmware-name = "a615_zap";
|
|
phandle = <0x4b5>;
|
|
};
|
|
|
|
qcom,kgsl-busmon {
|
|
label = "kgsl-busmon";
|
|
compatible = "qcom,kgsl-busmon";
|
|
phandle = <0x4b6>;
|
|
};
|
|
|
|
gpu-bw-tbl {
|
|
compatible = "operating-points-v2";
|
|
phandle = <0x29c>;
|
|
|
|
opp-0 {
|
|
opp-hz = <0x00 0x00>;
|
|
};
|
|
|
|
opp-100 {
|
|
opp-hz = <0x00 0x17d>;
|
|
};
|
|
|
|
opp-200 {
|
|
opp-hz = <0x00 0x2fa>;
|
|
};
|
|
|
|
opp-300 {
|
|
opp-hz = <0x00 0x478>;
|
|
};
|
|
|
|
opp-451 {
|
|
opp-hz = <0x00 0x6b8>;
|
|
};
|
|
|
|
opp-547 {
|
|
opp-hz = <0x00 0x826>;
|
|
};
|
|
|
|
opp-681 {
|
|
opp-hz = <0x00 0xa25>;
|
|
};
|
|
|
|
opp-825 {
|
|
opp-hz = <0x00 0xc4b>;
|
|
};
|
|
|
|
opp-1017 {
|
|
opp-hz = <0x00 0xf27>;
|
|
};
|
|
|
|
opp-1353 {
|
|
opp-hz = <0x00 0x1429>;
|
|
};
|
|
|
|
opp-1555 {
|
|
opp-hz = <0x00 0x172b>;
|
|
};
|
|
|
|
opp-1804 {
|
|
opp-hz = <0x00 0x1ae1>;
|
|
};
|
|
};
|
|
|
|
qcom,gpubw {
|
|
compatible = "qcom,devbw";
|
|
governor = "bw_vbif";
|
|
qcom,src-dst-ports = <0x1a 0x200>;
|
|
operating-points-v2 = <0x29c>;
|
|
phandle = <0x29d>;
|
|
};
|
|
|
|
qcom,kgsl-3d0@5000000 {
|
|
label = "kgsl-3d0";
|
|
compatible = "qcom,kgsl-3d0\0qcom,kgsl-3d";
|
|
status = "ok";
|
|
reg = <0x5000000 0x40000 0x5061000 0x800 0x509e000 0x1000 0x780000 0x6300>;
|
|
reg-names = "kgsl_3d0_reg_memory\0cx_dbgc\0cx_misc\0qfprom_memory";
|
|
interrupts = <0x00 0x12c 0x04>;
|
|
interrupt-names = "kgsl_3d0_irq";
|
|
qcom,id = <0x00>;
|
|
qcom,chipid = <0x6010800>;
|
|
qcom,gpu-quirk-hfi-use-reg;
|
|
qcom,gpu-quirk-secvid-set-once;
|
|
qcom,idle-timeout = <0x50>;
|
|
qcom,no-nap;
|
|
qcom,highest-bank-bit = <0x0e>;
|
|
qcom,min-access-length = <0x20>;
|
|
qcom,ubwc-mode = <0x02>;
|
|
qcom,snapshot-size = <0x200000>;
|
|
qcom,gpu-qdss-stm = <0x161c0000 0x40000>;
|
|
#cooling-cells = <0x02>;
|
|
clocks = <0x2b 0x11 0x2b 0x0e 0x27 0x1b 0x27 0x2b 0x2b 0x0b>;
|
|
clock-names = "core_clk\0rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk";
|
|
qcom,gpubw-dev = <0x29d>;
|
|
qcom,bus-control;
|
|
qcom,msm-bus,name = "grp3d";
|
|
qcom,bus-width = <0x20>;
|
|
qcom,msm-bus,num-cases = <0x0c>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x00 0x00 0x1a 0x200 0x00 0x61a80 0x1a 0x200 0x00 0xc3500 0x1a 0x200 0x00 0x124f80 0x1a 0x200 0x00 0x1b86e0 0x1a 0x200 0x00 0x2162e0 0x1a 0x200 0x00 0x2990a0 0x1a 0x200 0x00 0x325aa0 0x1a 0x200 0x00 0x3e12a0 0x1a 0x200 0x00 0x5294a0 0x1a 0x200 0x00 0x5ee8e0 0x1a 0x200 0x00 0x6e1b80>;
|
|
regulator-names = "vddcx\0vdd";
|
|
vddcx-supply = <0x1bd>;
|
|
vdd-supply = <0x246>;
|
|
cache-slice-names = "gpu\0gpuhtw";
|
|
cache-slices = <0x19f 0x0c 0x19f 0x0b>;
|
|
qcom,pm-qos-active-latency = <0x43>;
|
|
qcom,pm-qos-wakeup-latency = <0x43>;
|
|
qcom,enable-ca-jump;
|
|
qcom,ca-busy-penalty = <0x2ee0>;
|
|
qcom,gpu-speed-bin = <0x41a0 0x1fe00000 0x15>;
|
|
phandle = <0x21>;
|
|
|
|
qcom,gpu-mempools {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "qcom,gpu-mempools";
|
|
|
|
qcom,gpu-mempool@0 {
|
|
reg = <0x00>;
|
|
qcom,mempool-page-size = <0x1000>;
|
|
qcom,mempool-allocate;
|
|
};
|
|
|
|
qcom,gpu-mempool@1 {
|
|
reg = <0x01>;
|
|
qcom,mempool-page-size = <0x2000>;
|
|
qcom,mempool-allocate;
|
|
};
|
|
|
|
qcom,gpu-mempool@2 {
|
|
reg = <0x02>;
|
|
qcom,mempool-page-size = <0x10000>;
|
|
qcom,mempool-reserved = <0x100>;
|
|
};
|
|
|
|
qcom,gpu-mempool@3 {
|
|
reg = <0x03>;
|
|
qcom,mempool-page-size = <0x100000>;
|
|
qcom,mempool-reserved = <0x20>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevel-bins {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "qcom,gpu-pwrlevel-bins";
|
|
|
|
qcom,gpu-pwrlevels-0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
qcom,speed-bin = <0x00>;
|
|
qcom,initial-pwrlevel = <0x07>;
|
|
qcom,ca-target-pwrlevel = <0x05>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0x00>;
|
|
qcom,gpu-freq = <0x312c8040>;
|
|
qcom,bus-freq = <0x0b>;
|
|
qcom,bus-min = <0x0a>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <0x01>;
|
|
qcom,gpu-freq = <0x2faf0800>;
|
|
qcom,bus-freq = <0x0b>;
|
|
qcom,bus-min = <0x0a>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <0x02>;
|
|
qcom,gpu-freq = <0x26be3680>;
|
|
qcom,bus-freq = <0x0a>;
|
|
qcom,bus-min = <0x08>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <0x03>;
|
|
qcom,gpu-freq = <0x21ad3740>;
|
|
qcom,bus-freq = <0x09>;
|
|
qcom,bus-min = <0x08>;
|
|
qcom,bus-max = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <0x04>;
|
|
qcom,gpu-freq = <0x19a14780>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-max = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
reg = <0x05>;
|
|
qcom,gpu-freq = <0x1528dec0>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,bus-min = <0x05>;
|
|
qcom,bus-max = <0x08>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
reg = <0x06>;
|
|
qcom,gpu-freq = <0xfea18c0>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,bus-min = <0x04>;
|
|
qcom,bus-max = <0x07>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@7 {
|
|
reg = <0x07>;
|
|
qcom,gpu-freq = <0xaba9500>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,bus-min = <0x03>;
|
|
qcom,bus-max = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@8 {
|
|
reg = <0x08>;
|
|
qcom,gpu-freq = <0x00>;
|
|
qcom,bus-freq = <0x00>;
|
|
qcom,bus-min = <0x00>;
|
|
qcom,bus-max = <0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-1 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
qcom,speed-bin = <0xac>;
|
|
qcom,initial-pwrlevel = <0x07>;
|
|
qcom,ca-target-pwrlevel = <0x05>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0x00>;
|
|
qcom,gpu-freq = <0x312c8040>;
|
|
qcom,bus-freq = <0x0b>;
|
|
qcom,bus-min = <0x0a>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <0x01>;
|
|
qcom,gpu-freq = <0x2faf0800>;
|
|
qcom,bus-freq = <0x0b>;
|
|
qcom,bus-min = <0x0a>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <0x02>;
|
|
qcom,gpu-freq = <0x26be3680>;
|
|
qcom,bus-freq = <0x0a>;
|
|
qcom,bus-min = <0x08>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <0x03>;
|
|
qcom,gpu-freq = <0x21ad3740>;
|
|
qcom,bus-freq = <0x09>;
|
|
qcom,bus-min = <0x08>;
|
|
qcom,bus-max = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <0x04>;
|
|
qcom,gpu-freq = <0x19a14780>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-max = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
reg = <0x05>;
|
|
qcom,gpu-freq = <0x1528dec0>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,bus-min = <0x05>;
|
|
qcom,bus-max = <0x08>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
reg = <0x06>;
|
|
qcom,gpu-freq = <0xfea18c0>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,bus-min = <0x04>;
|
|
qcom,bus-max = <0x07>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@7 {
|
|
reg = <0x07>;
|
|
qcom,gpu-freq = <0xaba9500>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,bus-min = <0x03>;
|
|
qcom,bus-max = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@8 {
|
|
reg = <0x08>;
|
|
qcom,gpu-freq = <0x00>;
|
|
qcom,bus-freq = <0x00>;
|
|
qcom,bus-min = <0x00>;
|
|
qcom,bus-max = <0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-2 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
qcom,speed-bin = <0x92>;
|
|
qcom,initial-pwrlevel = <0x06>;
|
|
qcom,ca-target-pwrlevel = <0x04>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0x00>;
|
|
qcom,gpu-freq = <0x29b92700>;
|
|
qcom,bus-freq = <0x0b>;
|
|
qcom,bus-min = <0x0a>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <0x01>;
|
|
qcom,gpu-freq = <0x26be3680>;
|
|
qcom,bus-freq = <0x0a>;
|
|
qcom,bus-min = <0x08>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <0x02>;
|
|
qcom,gpu-freq = <0x21ad3740>;
|
|
qcom,bus-freq = <0x09>;
|
|
qcom,bus-min = <0x08>;
|
|
qcom,bus-max = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <0x03>;
|
|
qcom,gpu-freq = <0x19a14780>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-max = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <0x04>;
|
|
qcom,gpu-freq = <0x1528dec0>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,bus-min = <0x05>;
|
|
qcom,bus-max = <0x08>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
reg = <0x05>;
|
|
qcom,gpu-freq = <0xfea18c0>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,bus-min = <0x04>;
|
|
qcom,bus-max = <0x07>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
reg = <0x06>;
|
|
qcom,gpu-freq = <0xaba9500>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,bus-min = <0x03>;
|
|
qcom,bus-max = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@7 {
|
|
reg = <0x07>;
|
|
qcom,gpu-freq = <0x00>;
|
|
qcom,bus-freq = <0x00>;
|
|
qcom,bus-min = <0x00>;
|
|
qcom,bus-max = <0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-3 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
qcom,speed-bin = <0x80>;
|
|
qcom,initial-pwrlevel = <0x05>;
|
|
qcom,ca-target-pwrlevel = <0x03>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0x00>;
|
|
qcom,gpu-freq = <0x245bdc80>;
|
|
qcom,bus-freq = <0x0b>;
|
|
qcom,bus-min = <0x0a>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <0x01>;
|
|
qcom,gpu-freq = <0x21ad3740>;
|
|
qcom,bus-freq = <0x09>;
|
|
qcom,bus-min = <0x08>;
|
|
qcom,bus-max = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <0x02>;
|
|
qcom,gpu-freq = <0x19a14780>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-max = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <0x03>;
|
|
qcom,gpu-freq = <0x1528dec0>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,bus-min = <0x05>;
|
|
qcom,bus-max = <0x08>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <0x04>;
|
|
qcom,gpu-freq = <0xfea18c0>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,bus-min = <0x04>;
|
|
qcom,bus-max = <0x07>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
reg = <0x05>;
|
|
qcom,gpu-freq = <0xaba9500>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,bus-min = <0x03>;
|
|
qcom,bus-max = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
reg = <0x06>;
|
|
qcom,gpu-freq = <0x00>;
|
|
qcom,bus-freq = <0x00>;
|
|
qcom,bus-min = <0x00>;
|
|
qcom,bus-max = <0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-4 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
qcom,speed-bin = <0xa7>;
|
|
qcom,initial-pwrlevel = <0x06>;
|
|
qcom,ca-target-pwrlevel = <0x04>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0x00>;
|
|
qcom,gpu-freq = <0x2faf0800>;
|
|
qcom,bus-freq = <0x0b>;
|
|
qcom,bus-min = <0x0a>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <0x01>;
|
|
qcom,gpu-freq = <0x26be3680>;
|
|
qcom,bus-freq = <0x0a>;
|
|
qcom,bus-min = <0x08>;
|
|
qcom,bus-max = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <0x02>;
|
|
qcom,gpu-freq = <0x21ad3740>;
|
|
qcom,bus-freq = <0x09>;
|
|
qcom,bus-min = <0x08>;
|
|
qcom,bus-max = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <0x03>;
|
|
qcom,gpu-freq = <0x19a14780>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-max = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <0x04>;
|
|
qcom,gpu-freq = <0x1528dec0>;
|
|
qcom,bus-freq = <0x07>;
|
|
qcom,bus-min = <0x05>;
|
|
qcom,bus-max = <0x08>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
reg = <0x05>;
|
|
qcom,gpu-freq = <0xfea18c0>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,bus-min = <0x04>;
|
|
qcom,bus-max = <0x07>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
reg = <0x06>;
|
|
qcom,gpu-freq = <0xaba9500>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,bus-min = <0x03>;
|
|
qcom,bus-max = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@7 {
|
|
reg = <0x07>;
|
|
qcom,gpu-freq = <0x00>;
|
|
qcom,bus-freq = <0x00>;
|
|
qcom,bus-min = <0x00>;
|
|
qcom,bus-max = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,kgsl-iommu@5040000 {
|
|
compatible = "qcom,kgsl-smmu-v2";
|
|
reg = <0x5040000 0x10000>;
|
|
qcom,protect = <0x40000 0x10000>;
|
|
qcom,micro-mmu-control = <0x6000>;
|
|
clocks = <0x27 0x28 0x27 0x1b 0x27 0x2b>;
|
|
clock-names = "iface_clk\0mem_clk\0mem_iface_clk";
|
|
qcom,secure_align_mask = <0xfff>;
|
|
qcom,retention;
|
|
qcom,hyp_secure_alloc;
|
|
phandle = <0x4b7>;
|
|
|
|
gfx3d_user {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
label = "gfx3d_user";
|
|
iommus = <0x1c5 0x00>;
|
|
qcom,gpu-offset = <0x48000>;
|
|
phandle = <0x4b8>;
|
|
};
|
|
|
|
gfx3d_secure {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
iommus = <0x1c5 0x02>;
|
|
phandle = <0x4b9>;
|
|
};
|
|
};
|
|
|
|
qcom,gmu@506a000 {
|
|
label = "kgsl-gmu";
|
|
compatible = "qcom,gpu-gmu";
|
|
reg = <0x506a000 0x31000 0xb290000 0x10000 0xb490000 0x10000>;
|
|
reg-names = "kgsl_gmu_reg\0kgsl_gmu_pdc_cfg\0kgsl_gmu_pdc_seq";
|
|
interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>;
|
|
interrupt-names = "kgsl_hfi_irq\0kgsl_gmu_irq";
|
|
qcom,msm-bus,name = "cnoc";
|
|
qcom,msm-bus,num-cases = <0x02>;
|
|
qcom,msm-bus,num-paths = <0x01>;
|
|
qcom,msm-bus,vectors-KBps = <0x1a 0x2734 0x00 0x00 0x1a 0x2734 0x00 0x64>;
|
|
regulator-names = "vddcx\0vdd";
|
|
vddcx-supply = <0x1bd>;
|
|
vdd-supply = <0x246>;
|
|
clocks = <0x2b 0x0b 0x2b 0x0e 0x27 0x1b 0x27 0x2b>;
|
|
clock-names = "gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk";
|
|
phandle = <0x22>;
|
|
|
|
qcom,gmu-pwrlevels {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "qcom,gmu-pwrlevels";
|
|
|
|
qcom,gmu-pwrlevel@0 {
|
|
reg = <0x00>;
|
|
qcom,gmu-freq = <0x00>;
|
|
};
|
|
|
|
qcom,gmu-pwrlevel@1 {
|
|
reg = <0x01>;
|
|
qcom,gmu-freq = <0xbebc200>;
|
|
};
|
|
};
|
|
|
|
gmu_user {
|
|
compatible = "qcom,smmu-gmu-user-cb";
|
|
iommus = <0x1c5 0x04>;
|
|
phandle = <0x4ba>;
|
|
};
|
|
|
|
gmu_kernel {
|
|
compatible = "qcom,smmu-gmu-kernel-cb";
|
|
iommus = <0x1c5 0x05>;
|
|
phandle = <0x4bb>;
|
|
};
|
|
};
|
|
|
|
qcom,msm_npu@9800000 {
|
|
compatible = "qcom,msm-npu";
|
|
reg = <0x9800000 0x40000 0x9900000 0x10000 0x9960200 0x600 0x780000 0x7000>;
|
|
reg-names = "tcm\0core\0bwmon\0qfprom_physical";
|
|
interrupts = <0x00 0x247 0x01 0x00 0x249 0x01 0x00 0x24b 0x01>;
|
|
interrupt-names = "error_irq\0wdg_bite_irq\0ipc_irq";
|
|
iommus = <0x30 0x1461 0x00>;
|
|
cache-slice-names = "npu";
|
|
cache-slices = <0x19f 0x17>;
|
|
clocks = <0x19 0x00 0x2c 0x04 0x2c 0x08 0x2c 0x07 0x2c 0x0b 0x2c 0x0a 0x2c 0x0e 0x2c 0x10 0x2c 0x0c 0x2c 0x0d 0x2c 0x11 0x2c 0x12 0x2c 0x14 0x2c 0x15 0x2c 0x06 0x2c 0x13 0x2c 0x05 0x2c 0x16>;
|
|
clock-names = "qdss_clk\0armwic_core_clk\0cal_dp_clk\0cal_dp_cdc_clk\0conf_noc_ahb_clk\0comp_noc_axi_clk\0npu_core_clk\0npu_core_cti_clk\0npu_core_apb_clk\0npu_core_atb_clk\0npu_cpc_clk\0npu_cpc_timer_clk\0qtimer_core_clk\0sleep_clk\0bwmon_clk\0perf_cnt_clk\0bto_core_clk\0xo_clk";
|
|
vdd-supply = <0x23>;
|
|
vdd_cx-supply = <0x1d>;
|
|
qcom,proxy-reg-names = "vdd\0vdd_cx";
|
|
qcom,vdd_cx-uV-uA = <0x181 0x186a0>;
|
|
mboxes = <0x29e 0x00 0x29f 0x00>;
|
|
mbox-names = "npu_low\0npu_high";
|
|
#cooling-cells = <0x02>;
|
|
qcom,npubw-dev = <0xc0>;
|
|
qcom,npu-cxlimit-enable;
|
|
phandle = <0x70>;
|
|
|
|
qcom,npu-pwrlevels {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "qcom,npu-pwrlevels";
|
|
initial-pwrlevel = <0x04>;
|
|
|
|
qcom,npu-pwrlevel@0 {
|
|
reg = <0x00>;
|
|
vreg = <0x01>;
|
|
clk-freq = <0x00 0x5f5e100 0x11e1a300 0x11e1a300 0x1c9c380 0x8f0d180 0x5f5e100 0x23c3460 0x124f800 0x3938700 0x5f5e100 0x124f800 0x124f800 0x00 0x124f800 0x11e1a300 0x124f800 0x124f800>;
|
|
};
|
|
|
|
qcom,npu-pwrlevel@1 {
|
|
reg = <0x01>;
|
|
vreg = <0x02>;
|
|
clk-freq = <0x00 0x8f0d180 0x17d78400 0x17d78400 0x23c3460 0xbebc200 0x8f0d180 0x47868c0 0x124f800 0x7270e00 0x8f0d180 0x124f800 0x124f800 0x00 0x124f800 0x17d78400 0x124f800 0x124f800>;
|
|
};
|
|
|
|
qcom,npu-pwrlevel@2 {
|
|
reg = <0x02>;
|
|
vreg = <0x03>;
|
|
clk-freq = <0x00 0xbebc200 0x1bce39a0 0x1bce39a0 0x23c3460 0x11e1a300 0xbebc200 0x47868c0 0x124f800 0x7270e00 0xbebc200 0x124f800 0x124f800 0x00 0x124f800 0x1bce39a0 0x124f800 0x124f800>;
|
|
};
|
|
|
|
qcom,npu-pwrlevel@3 {
|
|
reg = <0x03>;
|
|
vreg = <0x04>;
|
|
clk-freq = <0x00 0x11e1a300 0x23c34600 0x23c34600 0x47868c0 0x18054ac0 0x11e1a300 0x8f0d180 0x124f800 0xe4e1c00 0x11e1a300 0x124f800 0x124f800 0x00 0x124f800 0x23c34600 0x124f800 0x124f800>;
|
|
};
|
|
|
|
qcom,npu-pwrlevel@4 {
|
|
reg = <0x04>;
|
|
vreg = <0x06>;
|
|
clk-freq = <0x00 0x17d78400 0x29b92700 0x29b92700 0x47868c0 0x1fc4ef40 0x17d78400 0x8f0d180 0x124f800 0x11e1a300 0x17d78400 0x124f800 0x124f800 0x00 0x124f800 0x29b92700 0x124f800 0x124f800>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dsi_panel_pwr_supply {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x58b>;
|
|
|
|
qcom,panel-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "vddio";
|
|
qcom,supply-min-voltage = <0x1b7740>;
|
|
qcom,supply-max-voltage = <0x1d0d80>;
|
|
qcom,supply-enable-load = <0x7d00>;
|
|
qcom,supply-disable-load = <0x50>;
|
|
};
|
|
|
|
qcom,panel-supply-entry@1 {
|
|
reg = <0x01>;
|
|
qcom,supply-name = "lab";
|
|
qcom,supply-min-voltage = <0x4630c0>;
|
|
qcom,supply-max-voltage = <0x5b8d80>;
|
|
qcom,supply-enable-load = <0x186a0>;
|
|
qcom,supply-disable-load = <0x64>;
|
|
};
|
|
|
|
qcom,panel-supply-entry@2 {
|
|
reg = <0x02>;
|
|
qcom,supply-name = "ibb";
|
|
qcom,supply-min-voltage = <0x4630c0>;
|
|
qcom,supply-max-voltage = <0x5b8d80>;
|
|
qcom,supply-enable-load = <0x186a0>;
|
|
qcom,supply-disable-load = <0x64>;
|
|
qcom,supply-post-on-sleep = <0x14>;
|
|
};
|
|
};
|
|
|
|
dsi_panel_pwr_supply_no_labibb {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x4ca>;
|
|
|
|
qcom,panel-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "vddio";
|
|
qcom,supply-min-voltage = <0x1b7740>;
|
|
qcom,supply-max-voltage = <0x1d0d80>;
|
|
qcom,supply-enable-load = <0x7d00>;
|
|
qcom,supply-disable-load = <0x50>;
|
|
};
|
|
};
|
|
|
|
dsi_panel_pwr_supply_labibb_amoled {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x4cb>;
|
|
|
|
qcom,panel-supply-entry@0 {
|
|
reg = <0x00>;
|
|
qcom,supply-name = "vddio";
|
|
qcom,supply-min-voltage = <0x1b7740>;
|
|
qcom,supply-max-voltage = <0x1d0d80>;
|
|
qcom,supply-enable-load = <0x7d00>;
|
|
qcom,supply-disable-load = <0x50>;
|
|
};
|
|
|
|
qcom,panel-supply-entry@1 {
|
|
reg = <0x01>;
|
|
qcom,supply-name = "vdda-3p3";
|
|
qcom,supply-min-voltage = <0x2dc6c0>;
|
|
qcom,supply-max-voltage = <0x2dc6c0>;
|
|
qcom,supply-enable-load = <0x3390>;
|
|
qcom,supply-disable-load = <0x50>;
|
|
};
|
|
};
|
|
|
|
qcom,dsi-display@0 {
|
|
label = "ss_dsi_panel_S6E3FA9_AMB667UM06_FHD";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0\0src_byte_clk0\0src_pixel_clk0\0shadow_byte_clk0\0shadow_pixel_clk0";
|
|
qcom,dsi-panel = <0x4cc>;
|
|
phandle = <0x5c0>;
|
|
};
|
|
|
|
qcom,dsi-display@1 {
|
|
label = "ss_dsi_panel_PBA_BOOTING_FHD";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4cd>;
|
|
phandle = <0x5c1>;
|
|
};
|
|
|
|
qcom,dsi-display@2 {
|
|
label = "dsi_sw43404_amoled_fhd_plus_cmd_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4ce>;
|
|
phandle = <0x58e>;
|
|
};
|
|
|
|
qcom,dsi-display@3 {
|
|
label = "dsi_sim_vid_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4cf>;
|
|
phandle = <0x58f>;
|
|
};
|
|
|
|
qcom,dsi-display@4 {
|
|
label = "dsi_dual_sim_vid_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00 0x01>;
|
|
qcom,dsi-phy-num = <0x00 0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4d0>;
|
|
phandle = <0x590>;
|
|
};
|
|
|
|
qcom,dsi-display@5 {
|
|
label = "dsi_sim_cmd_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4d1>;
|
|
phandle = <0x591>;
|
|
};
|
|
|
|
qcom,dsi-display@6 {
|
|
label = "dsi_dual_sim_cmd_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00 0x01>;
|
|
qcom,dsi-phy-num = <0x00 0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4d2>;
|
|
phandle = <0x592>;
|
|
};
|
|
|
|
qcom,dsi-display@7 {
|
|
label = "dsi_sim_dsc_375_cmd_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4d3>;
|
|
phandle = <0x593>;
|
|
};
|
|
|
|
qcom,dsi-display@8 {
|
|
label = "dsi_dual_sim_dsc_375_cmd_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00 0x01>;
|
|
qcom,dsi-phy-num = <0x00 0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4d4>;
|
|
phandle = <0x594>;
|
|
};
|
|
|
|
qcom,dsi-display@9 {
|
|
label = "dsi_dual_sharp_wqhd_video_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00 0x01>;
|
|
qcom,dsi-phy-num = <0x00 0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4d5>;
|
|
phandle = <0x595>;
|
|
};
|
|
|
|
qcom,dsi-display@10 {
|
|
label = "dsi_dual_sharp_wqhd_cmd_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00 0x01>;
|
|
qcom,dsi-phy-num = <0x00 0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4d6>;
|
|
phandle = <0x596>;
|
|
};
|
|
|
|
qcom,dsi-display@11 {
|
|
label = "dsi_rm69298_truly_amoled_vid_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4d7>;
|
|
phandle = <0x597>;
|
|
};
|
|
|
|
qcom,dsi-display@12 {
|
|
label = "dsi_rm69298_truly_amoled_cmd_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4d8>;
|
|
phandle = <0x598>;
|
|
};
|
|
|
|
qcom,dsi-display@13 {
|
|
label = "dsi_nt35695b_truly_fhd_video_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x01>;
|
|
qcom,dsi-phy-num = <0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk1\0mux_pixel_clk1";
|
|
qcom,dsi-panel = <0x4d9>;
|
|
phandle = <0x599>;
|
|
};
|
|
|
|
qcom,dsi-display@14 {
|
|
label = "dsi_nt35695b_truly_fhd_cmd_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x01>;
|
|
qcom,dsi-phy-num = <0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk1\0mux_pixel_clk1";
|
|
qcom,dsi-panel = <0x4da>;
|
|
phandle = <0x59a>;
|
|
};
|
|
|
|
qcom,dsi-display@15 {
|
|
label = "dsi_nt35695b_truly_fhd_video_sec_display";
|
|
qcom,display-type = "secondary";
|
|
qcom,dsi-ctrl-num = <0x01>;
|
|
qcom,dsi-phy-num = <0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk1\0mux_pixel_clk1";
|
|
qcom,dsi-panel = <0x4d9>;
|
|
phandle = <0x4ef>;
|
|
};
|
|
|
|
qcom,dsi-display@16 {
|
|
label = "dsi_nt35695b_truly_fhd_cmd_sec_display";
|
|
qcom,display-type = "secondary";
|
|
qcom,dsi-ctrl-num = <0x01>;
|
|
qcom,dsi-phy-num = <0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk1\0mux_pixel_clk1";
|
|
qcom,dsi-panel = <0x4da>;
|
|
phandle = <0x4f0>;
|
|
};
|
|
|
|
qcom,dsi-display@17 {
|
|
label = "dsi_rm69299_visionox_amoled_vid_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00>;
|
|
qcom,dsi-phy-num = <0x00>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4db>;
|
|
phandle = <0x59b>;
|
|
};
|
|
|
|
qcom,dsi-display@18 {
|
|
label = "dsi_sharp_qsync_wqhd_cmd_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00 0x01>;
|
|
qcom,dsi-phy-num = <0x00 0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4dc>;
|
|
phandle = <0x59c>;
|
|
};
|
|
|
|
qcom,dsi-display@19 {
|
|
label = "dsi_sharp_qsync_wqhd_video_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00 0x01>;
|
|
qcom,dsi-phy-num = <0x00 0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4dd>;
|
|
phandle = <0x59d>;
|
|
};
|
|
|
|
qcom,dsi-display@20 {
|
|
label = "dsi_sharp_qsync_fhd_video_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00 0x01>;
|
|
qcom,dsi-phy-num = <0x00 0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4de>;
|
|
phandle = <0x59e>;
|
|
};
|
|
|
|
qcom,dsi-display@21 {
|
|
label = "dsi_sharp_qsync_fhd_cmd_display";
|
|
qcom,display-type = "primary";
|
|
qcom,dsi-ctrl-num = <0x00 0x01>;
|
|
qcom,dsi-phy-num = <0x00 0x01>;
|
|
qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0";
|
|
qcom,dsi-panel = <0x4df>;
|
|
phandle = <0x59f>;
|
|
};
|
|
|
|
qcom,dsi-display {
|
|
compatible = "qcom,dsi-display";
|
|
qcom,dsi-ctrl = <0x365 0x366>;
|
|
qcom,dsi-phy = <0x367 0x368>;
|
|
clocks = <0x35d 0x06 0x35d 0x09 0x35e 0x20 0x35e 0x23 0x35d 0x03 0x35d 0x08 0x35d 0x11 0x35d 0x15>;
|
|
clock-names = "mux_byte_clk0\0mux_pixel_clk0\0mux_byte_clk1\0mux_pixel_clk1\0src_byte_clk0\0src_pixel_clk0\0shadow_byte_clk0\0shadow_pixel_clk0";
|
|
pinctrl-names = "panel_active\0panel_suspend";
|
|
pinctrl-0 = <0x4e0 0x4e1 0x4e2 0x4e3 0x4e4>;
|
|
pinctrl-1 = <0x4e5 0x4e6 0x4e7 0x4e8 0x4e9>;
|
|
qcom,platform-te-gpio = <0x16c 0x0a 0x00>;
|
|
qcom,panel-te-source = <0x00>;
|
|
vddio-supply = <0x3ef>;
|
|
vdda-3p3-supply = <0x4ea>;
|
|
lab-supply = <0x2e9>;
|
|
ibb-supply = <0x2ea>;
|
|
qcom,dsi-display-list = <0x4eb 0x4ec>;
|
|
vddi-supply = <0x4ed>;
|
|
vddr-supply = <0x4ee>;
|
|
phandle = <0x4f2>;
|
|
};
|
|
|
|
qcom,dsi-display-secondary {
|
|
compatible = "qcom,dsi-display";
|
|
label = "secondary";
|
|
qcom,dsi-ctrl = <0x365 0x366>;
|
|
qcom,dsi-phy = <0x367 0x368>;
|
|
clocks = <0x35d 0x06 0x35d 0x09 0x35e 0x20 0x35e 0x23>;
|
|
clock-names = "mux_byte_clk0\0mux_pixel_clk0\0mux_byte_clk1\0mux_pixel_clk1";
|
|
pinctrl-names = "panel_active\0panel_suspend";
|
|
pinctrl-0 = <0x3bc>;
|
|
pinctrl-1 = <0x3bd>;
|
|
qcom,platform-te-gpio = <0x16c 0x0b 0x00>;
|
|
qcom,panel-te-source = <0x01>;
|
|
vddio-supply = <0x3ef>;
|
|
vdda-3p3-supply = <0x4ea>;
|
|
lab-supply = <0x2e9>;
|
|
ibb-supply = <0x2ea>;
|
|
qcom,dsi-display-list = <0x4ef 0x4f0>;
|
|
phandle = <0x4f3>;
|
|
};
|
|
|
|
qcom,wb-display@0 {
|
|
compatible = "qcom,wb-display";
|
|
cell-index = <0x00>;
|
|
label = "wb_display";
|
|
phandle = <0x4f1>;
|
|
};
|
|
|
|
qcom,battery-data {
|
|
qcom,batt-id-range-pct = <0x0f>;
|
|
phandle = <0x4f6>;
|
|
|
|
qcom,alium_860_89032_0000_3600mAh {
|
|
qcom,max-voltage-uv = <0x426030>;
|
|
qcom,fg-cc-cv-threshold-uv = <0x423920>;
|
|
qcom,fastchg-current-ma = <0x1518>;
|
|
qcom,batt-id-kohm = <0x6b>;
|
|
qcom,battery-beta = <0x109a>;
|
|
qcom,battery-therm-kohm = <0x64>;
|
|
qcom,battery-type = "Alium_860_89032_0000_3600mAh_Jun15th2018";
|
|
qcom,qg-batt-profile-ver = <0x64>;
|
|
qcom,jeita-fcc-ranges = <0x00 0x32 0x2625a0 0x33 0x190 0x5265c0 0x191 0x1c2 0x2625a0>;
|
|
qcom,jeita-fv-ranges = <0x00 0x32 0x40d990 0x33 0x190 0x426030 0x191 0x1c2 0x40d990>;
|
|
qcom,step-chg-ranges = <0x36ee80 0x39fbc0 0x5265c0 0x39fbc1 0x419ce0 0x36ee80 0x419ce1 0x426030 0x2625a0>;
|
|
qcom,ocv-based-step-chg;
|
|
qcom,jeita-soft-thresholds = <0x5314 0x25e3>;
|
|
qcom,jeita-hard-thresholds = <0x58cd 0x20b8>;
|
|
qcom,jeita-soft-hys-thresholds = <0x4f5e 0x2943>;
|
|
qcom,jeita-soft-fcc-ua = <0x2625a0 0x2625a0>;
|
|
qcom,jeita-soft-fv-uv = <0x40d990 0x40d990>;
|
|
|
|
qcom,fcc1-temp-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-data = <0xd62 0xdbf 0xdfd 0xe1d 0xe2e>;
|
|
};
|
|
|
|
qcom,fcc2-temp-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-data = <0xdda 0xdf8 0xe02 0xe04 0xdff 0xdff>;
|
|
};
|
|
|
|
qcom,pc-temp-v1-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0xa846 0xa903 0xa965 0xa982 0xa987 0xa757 0xa82c 0xa88b 0xa8b2 0xa8bc 0xa671 0xa747 0xa7a8 0xa7d4 0xa7e5 0xa598 0xa65f 0xa6c5 0xa6f2 0xa707 0xa4ca 0xa582 0xa5e5 0xa611 0xa627 0xa3ff 0xa4af 0xa508 0xa531 0xa546 0xa330 0xa3e1 0xa430 0xa452 0xa465 0xa25d 0xa311 0xa35c 0xa377 0xa387 0xa1a0 0xa23e 0xa287 0xa29e 0xa2ad 0xa10a 0xa17a 0xa1b1 0xa1c4 0xa1d2 0xa07e 0xa0e5 0xa0f6 0xa0f5 0xa0fc 0x9fa9 0xa061 0xa067 0xa048 0xa036 0x9e4b 0x9f9a 0x9fd6 0x9fae 0x9f81 0x9cdb 0x9e3d 0x9ee8 0x9ee6 0x9ebf 0x9bed 0x9cd1 0x9d85 0x9dc6 0x9dd7 0x9b4d 0x9bf5 0x9c67 0x9cb4 0x9cf4 0x9ad6 0x9b65 0x9bd6 0x9c18 0x9c4a 0x9a75 0x9af5 0x9b63 0x9baa 0x9bc5 0x9a1f 0x9a9b 0x9ade 0x9b13 0x9b23 0x99c4 0x9a41 0x9a3f 0x9a2d 0x9a41 0x9962 0x99c6 0x998a 0x9943 0x9959 0x98fd 0x992a 0x98b8 0x9892 0x98a0 0x9894 0x9882 0x97f4 0x9800 0x9807 0x982b 0x97c6 0x976f 0x9780 0x9781 0x97cb 0x9713 0x970f 0x970c 0x970c 0x9775 0x9697 0x96b5 0x96a2 0x96a2 0x9724 0x963e 0x965a 0x9642 0x963e 0x96db 0x95fa 0x9603 0x95e9 0x95e1 0x9698 0x95c7 0x95b7 0x9598 0x958b 0x965b 0x959d 0x9571 0x954e 0x953b 0x9627 0x9575 0x9533 0x950c 0x94f4 0x95f8 0x9550 0x94fe 0x94d1 0x94b3 0x95cc 0x952e 0x94cf 0x949b 0x947a 0x95a2 0x9511 0x94a4 0x9465 0x9440 0x9579 0x94f7 0x947f 0x9432 0x9407 0x954f 0x94d6 0x9458 0x93fe 0x93cc 0x9525 0x94b2 0x942f 0x93c6 0x938b 0x94f0 0x9484 0x9402 0x938b 0x9345 0x94a6 0x943e 0x93bf 0x9343 0x92f7 0x944c 0x93da 0x935f 0x92ed 0x92a2 0x93e6 0x936c 0x92f1 0x9288 0x923f 0x936b 0x92f1 0x9276 0x920e 0x91c6 0x92e1 0x926f 0x91f1 0x9188 0x9141 0x9248 0x91ea 0x9165 0x90ff 0x90bc 0x91cf 0x9176 0x9100 0x909b 0x905b 0x9179 0x9129 0x90c1 0x9060 0x9022 0x9159 0x910e 0x90ab 0x904f 0x9011 0x913e 0x90f9 0x909a 0x903f 0x9001 0x911a 0x90de 0x907f 0x9020 0x8fdd 0x90ac 0x9070 0x8ff7 0x8f74 0x8f1a 0x8f68 0x8f1c 0x8e9e 0x8e14 0x8db6 0x8d9d 0x8d55 0x8cd8 0x8c4c 0x8beb 0x8b59 0x8b10 0x8a94 0x8a02 0x899f 0x8849 0x87fb 0x877d 0x86e5 0x867d 0x836c 0x8325 0x82aa 0x8209 0x8197 0x7530 0x7530 0x7530 0x7530 0x7530>;
|
|
};
|
|
|
|
qcom,pc-temp-v2-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0xa98d 0xa97e 0xa974 0xa960 0xa92e 0xa910 0xa7fb 0xa83a 0xa854 0xa856 0xa82f 0xa819 0xa6a3 0xa712 0xa747 0xa757 0xa738 0xa728 0xa594 0xa609 0xa64d 0xa665 0xa64a 0xa63c 0xa4c7 0xa51d 0xa566 0xa581 0xa565 0xa558 0xa3f4 0xa43e 0xa489 0xa4a2 0xa484 0xa478 0xa2af 0xa364 0xa3b3 0xa3c8 0xa3a5 0xa397 0xa162 0xa292 0xa2e4 0xa2f3 0xa2ca 0xa2b9 0xa11a 0xa1c1 0xa210 0xa21b 0xa1ef 0xa1de 0xa14f 0xa0ea 0xa131 0xa139 0xa110 0xa103 0xa17a 0xa03c 0xa071 0xa077 0xa047 0xa035 0xa046 0x9fd6 0x9ff5 0x9ff5 0x9fb3 0x9f87 0x9d6d 0x9f7f 0x9f85 0x9f81 0x9f2b 0x9ee2 0x9b88 0x9eab 0x9ea9 0x9ead 0x9e5e 0x9e1a 0x9a81 0x9c78 0x9cde 0x9d1e 0x9d16 0x9d22 0x99b8 0x9a96 0x9b46 0x9bd5 0x9bfe 0x9c3f 0x9913 0x99e8 0x9a78 0x9b4d 0x9b70 0x9b9c 0x9887 0x9977 0x99df 0x9aeb 0x9b04 0x9b0e 0x97f7 0x98f2 0x9948 0x9a53 0x9a64 0x9a58 0x975c 0x9856 0x98b5 0x9965 0x9971 0x9967 0x96c8 0x97b8 0x9827 0x987f 0x9885 0x9883 0x9649 0x9720 0x9799 0x97d3 0x97d8 0x97d6 0x95d8 0x968d 0x9711 0x9743 0x9748 0x9745 0x957d 0x9608 0x9697 0x96c6 0x96cb 0x96c8 0x9533 0x9591 0x9629 0x9658 0x965c 0x9658 0x94f4 0x952a 0x95c3 0x95f3 0x95f6 0x95f1 0x94bc 0x94d6 0x9565 0x9595 0x9598 0x9592 0x948a 0x9491 0x950e 0x953e 0x9540 0x9538 0x9458 0x9459 0x94bd 0x94f0 0x94ef 0x94e6 0x9429 0x942b 0x9471 0x94aa 0x94a5 0x949b 0x93fa 0x9403 0x942c 0x9467 0x9461 0x9456 0x93cb 0x93dc 0x93ed 0x9426 0x9422 0x9418 0x939a 0x93b7 0x93b6 0x93e7 0x93e7 0x93dd 0x9366 0x9390 0x9384 0x93a6 0x93a1 0x9392 0x9330 0x9367 0x935a 0x9364 0x9348 0x932b 0x92f5 0x933c 0x9330 0x9322 0x92ea 0x92bd 0x92b6 0x9309 0x9301 0x92e2 0x9296 0x925d 0x9274 0x92ce 0x92cf 0x92a2 0x9248 0x9208 0x922d 0x9289 0x9294 0x925e 0x91fe 0x91bc 0x91e4 0x9235 0x924a 0x9214 0x91b6 0x9173 0x919a 0x91d4 0x91f2 0x91c0 0x9166 0x9124 0x9151 0x916d 0x918d 0x9158 0x9101 0x90c0 0x910a 0x9104 0x9119 0x90da 0x9085 0x9045 0x90be 0x90a5 0x90a4 0x9064 0x9011 0x8fd4 0x9066 0x9055 0x9058 0x9026 0x8fde 0x8fa3 0x8ff1 0x9009 0x9027 0x900b 0x8fc1 0x8f87 0x8fa0 0x8fd7 0x9010 0x8ff6 0x8fb0 0x8f76 0x8f3a 0x8f9b 0x8ff2 0x8fd7 0x8f94 0x8f5b 0x8e9d 0x8f3c 0x8fa7 0x8f84 0x8f3f 0x8efc 0x8dbc 0x8e73 0x8ecd 0x8e86 0x8e46 0x8df2 0x8c72 0x8d0b 0x8d41 0x8ce7 0x8ca5 0x8c4f 0x8a95 0x8b0d 0x8b2a 0x8ad3 0x8a9a 0x8a45 0x87f8 0x8865 0x887d 0x881c 0x87ec 0x879d 0x841a 0x8496 0x84d3 0x8488 0x847e 0x8426 0x7eca 0x7f24 0x801b 0x8028 0x7f97 0x7ef0 0x6fcb 0x6e6e 0x6d71 0x6d74 0x6d50 0x6d1a>;
|
|
};
|
|
|
|
qcom,pc-temp-z1-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x38d1 0x33b6 0x2f09 0x2da0 0x2d49 0x38bb 0x337f 0x2f0d 0x2d9e 0x2d52 0x38c3 0x3376 0x2f0b 0x2da5 0x2d5c 0x38c7 0x337e 0x2f07 0x2da7 0x2d60 0x38d3 0x3382 0x2f03 0x2da8 0x2d62 0x38eb 0x337d 0x2f01 0x2da8 0x2d64 0x38ff 0x336c 0x2f02 0x2da9 0x2d67 0x38f6 0x335e 0x2f03 0x2dac 0x2d6a 0x38d7 0x335d 0x2f05 0x2dae 0x2d6d 0x38b6 0x3362 0x2f09 0x2db1 0x2d6f 0x3896 0x3360 0x2f0d 0x2db5 0x2d72 0x3874 0x334e 0x2f0f 0x2db8 0x2d77 0x3843 0x333c 0x2f0f 0x2dbb 0x2d7b 0x3810 0x332e 0x2f0b 0x2dbb 0x2d7c 0x37ee 0x3328 0x2f04 0x2db9 0x2d7c 0x37d3 0x3329 0x2f01 0x2db7 0x2d7c 0x37b6 0x3329 0x2f04 0x2dbb 0x2d7f 0x3792 0x332c 0x2f0a 0x2dc2 0x2d85 0x3772 0x3337 0x2f14 0x2dc9 0x2d8b 0x3765 0x3349 0x2f21 0x2dce 0x2d8f 0x3763 0x335e 0x2f2c 0x2dd3 0x2d93 0x376a 0x3374 0x2f35 0x2dd8 0x2d98 0x3773 0x3384 0x2f3d 0x2ddd 0x2d9c 0x377f 0x338b 0x2f45 0x2de1 0x2da1 0x3787 0x3391 0x2f4d 0x2de7 0x2da6 0x378c 0x339a 0x2f54 0x2dec 0x2daa 0x378f 0x33a6 0x2f5b 0x2df0 0x2daf 0x3794 0x33ad 0x2f62 0x2df4 0x2db3 0x379f 0x33b2 0x2f69 0x2df8 0x2db7 0x37af 0x33ba 0x2f6f 0x2dfc 0x2dbb 0x37c7 0x33c2 0x2f75 0x2e00 0x2dbf 0x37de 0x33c9 0x2f7a 0x2e04 0x2dc4 0x37e6 0x33d1 0x2f80 0x2e08 0x2dc8 0x37ea 0x33de 0x2f86 0x2e0d 0x2dcd 0x37f0 0x33f1 0x2f8e 0x2e12 0x2dd1 0x3807 0x3403 0x2f95 0x2e17 0x2dd5 0x383b 0x3415 0x2f9d 0x2e1a 0x2dd8 0x386b 0x3422 0x2fa5 0x2e1c 0x2dda 0x3891 0x3427 0x2faa 0x2e1f 0x2ddc 0x38b0 0x3429 0x2fad 0x2e21 0x2ddd 0x38b2 0x342d 0x2fb1 0x2e23 0x2dde 0x3888 0x3439 0x2fb9 0x2e25 0x2de0 0x3873 0x3448 0x2fbf 0x2e27 0x2de1 0x386e 0x3457 0x2fc0 0x2e28 0x2de2 0x3861 0x3449 0x2fc4 0x2e29 0x2de2 0x386f 0x3454 0x2fc7 0x2e2b 0x2de2 0x3869 0x3454 0x2fc8 0x2e2b 0x2de1 0x3868 0x345b 0x2fc9 0x2e2b 0x2de2 0x385f 0x3457 0x2fcf 0x2e2c 0x2de3 0x387c 0x3452 0x2fd1 0x2e30 0x2de6 0x3886 0x346f 0x2fdb 0x2e36 0x2deb 0x38aa 0x3476 0x2ff3 0x2e3f 0x2df0 0x3895 0x349e 0x3007 0x2e4a 0x2dfa 0x38d0 0x34c8 0x3032 0x2e5c 0x2e06 0x38d0 0x34c8 0x3032 0x2e5c 0x2e06 0x38d0 0x34c8 0x3032 0x2e5c 0x2e06>;
|
|
};
|
|
|
|
qcom,pc-temp-z2-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x2bb8 0x2632 0x2811 0x296b 0x2a9e 0x280d 0x2a3d 0x2824 0x28fa 0x293e 0x25fe 0x2926 0x282f 0x28bc 0x28c4 0x2606 0x274d 0x282a 0x28ad 0x28ac 0x2620 0x26d2 0x281d 0x2898 0x28a6 0x262f 0x26c3 0x2815 0x288c 0x28a4 0x2631 0x26b5 0x2811 0x2887 0x28a8 0x262c 0x26aa 0x2812 0x2882 0x28ac 0x2625 0x26a2 0x2816 0x2880 0x28ac 0x261b 0x269c 0x2819 0x2884 0x28b5 0x2612 0x2698 0x2813 0x2887 0x28cc 0x2616 0x2696 0x27f3 0x288e 0x28d4 0x2626 0x2699 0x27d7 0x28ae 0x28d3 0x262c 0x26a7 0x27e8 0x28bd 0x28d4 0x2618 0x26b3 0x2814 0x289f 0x28d2 0x25f5 0x26b6 0x282a 0x2883 0x28c7 0x25e5 0x26ba 0x2827 0x288f 0x28d1 0x25e1 0x26c3 0x281d 0x28b2 0x290a 0x25dd 0x26dd 0x2837 0x28e1 0x2937 0x25d6 0x26fd 0x2894 0x2931 0x293f 0x25c9 0x271e 0x28ce 0x296a 0x293f 0x25be 0x2742 0x28b3 0x2939 0x2923 0x25b7 0x2760 0x2883 0x28bd 0x28ee 0x25b1 0x2775 0x2863 0x288b 0x28cc 0x259f 0x2784 0x284c 0x289e 0x28b4 0x2574 0x278c 0x283f 0x28b6 0x28a5 0x2552 0x2793 0x283c 0x28a9 0x28a6 0x2544 0x2797 0x283d 0x2890 0x28af 0x250b 0x2796 0x2845 0x2888 0x28ba 0x24d2 0x2793 0x2859 0x2888 0x28cd 0x24c0 0x2792 0x286f 0x288c 0x28e8 0x24b3 0x2793 0x2885 0x289f 0x290a 0x24aa 0x2795 0x289c 0x28c5 0x2934 0x24a2 0x2799 0x28b4 0x28ea 0x2962 0x249c 0x27a2 0x28ce 0x290a 0x299b 0x2498 0x27aa 0x28df 0x2925 0x29c7 0x249e 0x27b2 0x28e4 0x293c 0x29d8 0x24a4 0x27b7 0x28e7 0x2954 0x29e2 0x24ad 0x27bb 0x28ef 0x2961 0x29ed 0x24b6 0x27c0 0x28fb 0x2964 0x29f9 0x24b5 0x27c2 0x2901 0x2965 0x2a01 0x24a8 0x27b9 0x28fa 0x2971 0x2a03 0x24a4 0x279c 0x28f3 0x2981 0x2a07 0x24aa 0x26ec 0x28f1 0x2987 0x2a1d 0x246c 0x26c6 0x28d6 0x2992 0x2a3b 0x2459 0x26cc 0x28c6 0x29ad 0x2a38 0x2447 0x26dc 0x28df 0x29c9 0x2a6a 0x2449 0x26cd 0x293d 0x29ca 0x2a89 0x243a 0x26ed 0x297e 0x2a06 0x2aa5 0x243e 0x26c3 0x2925 0x29d7 0x2a55 0x2464 0x269c 0x28de 0x298a 0x29c5 0x246e 0x264f 0x28b9 0x2971 0x29af 0x2445 0x25fc 0x289b 0x2927 0x295f 0x241d 0x258f 0x282d 0x28da 0x2904 0x241d 0x258f 0x282d 0x28da 0x2904 0x241d 0x258f 0x282d 0x28da 0x2904>;
|
|
};
|
|
|
|
qcom,pc-temp-z3-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x4c45 0x4be7 0x4bad 0x4bb7 0x4b9b 0x4d48 0x4c26 0x4bd0 0x4baa 0x4b96 0x4dd0 0x4c76 0x4bee 0x4bac 0x4b97 0x4de1 0x4cc3 0x4bfa 0x4bb4 0x4b9c 0x4dce 0x4cd9 0x4bff 0x4bb6 0x4b9f 0x4db7 0x4cdc 0x4c00 0x4bb7 0x4ba2 0x4dac 0x4cdd 0x4bfe 0x4bb5 0x4ba2 0x4da7 0x4cdd 0x4bfb 0x4bb0 0x4b9f 0x4da5 0x4ce0 0x4bf8 0x4bac 0x4b9b 0x4da2 0x4ce2 0x4bf6 0x4bac 0x4b99 0x4da0 0x4cd4 0x4bf0 0x4bac 0x4b98 0x4da5 0x4cac 0x4bdf 0x4ba7 0x4b98 0x4db6 0x4c9a 0x4bc8 0x4b9b 0x4b95 0x4dc5 0x4cb6 0x4bce 0x4b96 0x4b91 0x4db4 0x4cd7 0x4bef 0x4ba3 0x4b93 0x4d83 0x4cd1 0x4c01 0x4bb3 0x4b97 0x4d54 0x4cac 0x4bec 0x4bad 0x4b94 0x4d30 0x4c8a 0x4bd0 0x4b9c 0x4b8a 0x4d0e 0x4c6f 0x4bcf 0x4b98 0x4b87 0x4cf1 0x4c5e 0x4be1 0x4ba6 0x4b8e 0x4cd8 0x4c62 0x4bee 0x4bb3 0x4b97 0x4cc6 0x4c75 0x4bef 0x4bb3 0x4b9d 0x4cbc 0x4c87 0x4bef 0x4bae 0x4ba1 0x4cb4 0x4c93 0x4bed 0x4bad 0x4ba2 0x4cac 0x4c9c 0x4bea 0x4bb4 0x4ba0 0x4ca3 0x4c9d 0x4be9 0x4bba 0x4b9e 0x4c97 0x4c9b 0x4bef 0x4bb7 0x4b9c 0x4c8c 0x4c97 0x4bf5 0x4bb2 0x4b9a 0x4c7f 0x4c91 0x4bf6 0x4bae 0x4b98 0x4c6f 0x4c8a 0x4bf4 0x4ba9 0x4b96 0x4c5d 0x4c84 0x4bf2 0x4ba5 0x4b94 0x4c4a 0x4c7f 0x4bef 0x4ba2 0x4b91 0x4c3a 0x4c7a 0x4bea 0x4ba0 0x4b8e 0x4c2b 0x4c73 0x4be7 0x4b9f 0x4b8a 0x4c1e 0x4c6b 0x4be5 0x4b9e 0x4b86 0x4c17 0x4c65 0x4be2 0x4b9e 0x4b84 0x4c1b 0x4c5f 0x4bde 0x4b9e 0x4b84 0x4c23 0x4c5a 0x4bda 0x4b9d 0x4b86 0x4c39 0x4c56 0x4bd7 0x4b9c 0x4b86 0x4c4f 0x4c53 0x4bd6 0x4b97 0x4b83 0x4c46 0x4c4f 0x4bd4 0x4b93 0x4b81 0x4c28 0x4c4a 0x4bd2 0x4b93 0x4b82 0x4c1b 0x4c3f 0x4bd0 0x4b93 0x4b82 0x4c19 0x4bfb 0x4bcc 0x4b93 0x4b83 0x4bac 0x4bb3 0x4bb6 0x4b90 0x4b7f 0x4b91 0x4b94 0x4ba0 0x4b89 0x4b78 0x4b89 0x4b8c 0x4b9e 0x4b80 0x4b70 0x4b8b 0x4b87 0x4b8e 0x4b7e 0x4b70 0x4b74 0x4b76 0x4b83 0x4b7c 0x4b6d 0x4b78 0x4b75 0x4b98 0x4b87 0x4b7c 0x4bab 0x4b91 0x4b9b 0x4b8b 0x4b83 0x4bda 0x4b96 0x4b9d 0x4b8e 0x4b84 0x4bf2 0x4b94 0x4b99 0x4b92 0x4b87 0x4c08 0x4ba0 0x4b9f 0x4b95 0x4b8c 0x4c08 0x4ba0 0x4b9f 0x4b95 0x4b8c 0x4c08 0x4ba0 0x4b9f 0x4b95 0x4b8c>;
|
|
};
|
|
|
|
qcom,pc-temp-z4-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x4001 0x3c8d 0x3a72 0x3978 0x397b 0x40ed 0x3c83 0x3a6f 0x39c6 0x39b9 0x40da 0x3c60 0x3a4a 0x39d2 0x39c2 0x4086 0x3c0a 0x3a21 0x39c0 0x39b5 0x4000 0x3ba1 0x39fb 0x39a7 0x399e 0x3f71 0x3b4a 0x39dc 0x3990 0x3986 0x3ef7 0x3b02 0x39c2 0x3981 0x3976 0x3e89 0x3acb 0x39ac 0x3976 0x396c 0x3e16 0x3aa0 0x39a0 0x3970 0x3966 0x3d82 0x3a79 0x399a 0x396d 0x3961 0x3cf4 0x3a50 0x3998 0x396a 0x395d 0x3cc5 0x3a2f 0x3998 0x3965 0x3959 0x3cdb 0x3a29 0x3999 0x395f 0x3951 0x3cf0 0x3a35 0x399d 0x3961 0x394e 0x3cc2 0x3a3c 0x39a2 0x3970 0x395b 0x3c4c 0x3a29 0x39a0 0x397b 0x3968 0x3beb 0x39fe 0x398c 0x396b 0x395e 0x3bb2 0x39dd 0x3979 0x394d 0x3947 0x3b8d 0x39c9 0x3978 0x394f 0x3946 0x3b7e 0x39bd 0x3982 0x3988 0x3974 0x3b75 0x39bc 0x3996 0x39ba 0x39a6 0x3b71 0x39bf 0x39ca 0x39be 0x39ab 0x3b75 0x39c9 0x39fe 0x39b9 0x399f 0x3b7b 0x39fa 0x39fe 0x39ae 0x3991 0x3b80 0x3a38 0x39df 0x3993 0x3982 0x3b85 0x3a46 0x39bf 0x397d 0x3975 0x3b8c 0x3a43 0x39a7 0x3973 0x396c 0x3b92 0x3a3e 0x3994 0x396e 0x3965 0x3b9e 0x3a2f 0x3989 0x3969 0x395f 0x3bab 0x3a18 0x3982 0x3965 0x395a 0x3bb3 0x3a05 0x397d 0x3962 0x3955 0x3bba 0x39f5 0x397b 0x395e 0x3951 0x3bbe 0x39e5 0x397a 0x395a 0x394e 0x3bbc 0x39d6 0x3979 0x395a 0x394d 0x3bb5 0x39c8 0x3979 0x395c 0x3950 0x3ba1 0x39ba 0x3978 0x395e 0x3955 0x3b72 0x39ac 0x3976 0x3961 0x395b 0x3b43 0x39a1 0x3973 0x3963 0x3961 0x3afc 0x399e 0x3970 0x3963 0x3963 0x3abc 0x399c 0x396d 0x3963 0x3960 0x3ab4 0x3999 0x396a 0x3962 0x395d 0x3abb 0x3994 0x3967 0x3960 0x395c 0x3ab9 0x3995 0x3962 0x395d 0x395b 0x3aa3 0x39d0 0x395a 0x3959 0x3958 0x3abd 0x39eb 0x3957 0x394b 0x394c 0x3ac6 0x39f6 0x3953 0x3935 0x3934 0x3acb 0x39f8 0x394d 0x3931 0x392d 0x3ac3 0x39fa 0x3959 0x3929 0x3920 0x3ad0 0x3a03 0x3961 0x3925 0x391e 0x3ac0 0x39ff 0x394e 0x392e 0x392c 0x3a9b 0x39f7 0x3956 0x3935 0x3930 0x3a8e 0x39fe 0x3959 0x3936 0x3935 0x3a94 0x3a0e 0x3963 0x3937 0x3936 0x3aa9 0x3a1d 0x3967 0x393a 0x3936 0x3aa9 0x3a1d 0x3967 0x393a 0x3936 0x3aa9 0x3a1d 0x3967 0x393a 0x3936>;
|
|
};
|
|
|
|
qcom,pc-temp-z5-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x2b3c 0x2daa 0x3498 0x4a8d 0x45cc 0x2ef0 0x3052 0x39fb 0x4721 0x484e 0x3117 0x343d 0x3f9f 0x4802 0x4a61 0x31df 0x385f 0x430e 0x4b83 0x4d9f 0x326a 0x3a69 0x44ec 0x4e02 0x5124 0x32f3 0x3bab 0x4673 0x5049 0x55e1 0x33c6 0x3ce5 0x4810 0x514c 0x5936 0x34d0 0x3e95 0x49be 0x511b 0x5a23 0x35db 0x4119 0x4b35 0x5160 0x5a1d 0x36fa 0x4312 0x4c4c 0x5327 0x5b6b 0x3859 0x42b6 0x4bad 0x5424 0x5e2c 0x3a2d 0x3f5c 0x45e6 0x5167 0x6138 0x3c44 0x3ed3 0x3ee4 0x49ed 0x6100 0x3d63 0x47a6 0x4250 0x472f 0x5e7d 0x3d9a 0x506d 0x5049 0x50b3 0x5f98 0x3db5 0x5016 0x57f1 0x5c40 0x639a 0x3dda 0x4c6d 0x532f 0x5d14 0x64bc 0x3dd6 0x4a75 0x4bb9 0x59b9 0x646c 0x3d86 0x49e6 0x55e6 0x5b90 0x6454 0x3cdc 0x49b6 0x76e4 0x6b24 0x646b 0x3bcd 0x5034 0x875d 0x7705 0x6492 0x3ad1 0x649b 0x78a4 0x6a60 0x5e9c 0x3a04 0x7968 0x6282 0x5014 0x511e 0x3939 0x8c1a 0x56c4 0x4873 0x4bc7 0x3846 0x9a39 0x4fd8 0x5026 0x4d8e 0x3716 0x9aa6 0x4dfb 0x5780 0x5074 0x35e9 0x91df 0x53c1 0x5aa0 0x53ba 0x34ed 0x87db 0x5d83 0x5d20 0x57f1 0x33ea 0x7eb5 0x65eb 0x5e8b 0x5cc6 0x32dd 0x764e 0x6eb9 0x601d 0x628a 0x31ca 0x720c 0x75c6 0x61b9 0x67fc 0x30bf 0x6fd5 0x79eb 0x63f1 0x6c9c 0x2ffa 0x6e15 0x7d26 0x6810 0x7085 0x2f5e 0x6c28 0x8068 0x6dc5 0x7165 0x2ed6 0x6a83 0x83d1 0x7653 0x6fdc 0x2e78 0x6a47 0x8529 0x7b5b 0x6e81 0x2ea9 0x6b32 0x8003 0x7adf 0x6f61 0x2f11 0x6ca0 0x7890 0x796f 0x710e 0x303e 0x6e9b 0x7749 0x7672 0x709c 0x317f 0x7119 0x77a9 0x6cad 0x6a94 0x3162 0x71bd 0x77df 0x65cc 0x65f5 0x300b 0x6c45 0x7771 0x66c4 0x66af 0x2fb0 0x60cd 0x7669 0x680b 0x6789 0x3015 0x4018 0x70b0 0x6813 0x6600 0x2ca4 0x3328 0x596b 0x6764 0x62b7 0x2bbe 0x3022 0x477d 0x6688 0x6215 0x2b68 0x2f70 0x4725 0x57da 0x5967 0x2b6c 0x2f09 0x3dd8 0x58e5 0x64be 0x2ab7 0x2db9 0x398d 0x5bd2 0x6460 0x2ae0 0x2ded 0x457f 0x6bcd 0x75c0 0x2cb0 0x2ff3 0x438f 0x6311 0x7110 0x2d80 0x2fa5 0x439f 0x6129 0x668d 0x2d89 0x2ebe 0x3ec3 0x61e3 0x62ca 0x2d50 0x2e6c 0x3eb4 0x5b72 0x6005 0x2d50 0x2e6c 0x3eb4 0x5b72 0x6005 0x2d50 0x2e6c 0x3eb4 0x5b72 0x6005>;
|
|
};
|
|
|
|
qcom,pc-temp-z6-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x409a 0x3c2e 0x39dd 0x392f 0x3913 0x416d 0x3c48 0x39ee 0x394b 0x392d 0x419b 0x3c57 0x39ee 0x3952 0x3933 0x4181 0x3c50 0x39e4 0x394f 0x3931 0x413b 0x3c33 0x39d5 0x3947 0x392a 0x40e4 0x3c0c 0x39c7 0x393d 0x3921 0x409c 0x3be5 0x39bb 0x3935 0x391b 0x4062 0x3bcb 0x39b0 0x392e 0x3915 0x4027 0x3bb9 0x39aa 0x392a 0x3910 0x3fe0 0x3ba7 0x39a7 0x3929 0x390e 0x3f9a 0x3b8a 0x39a3 0x3928 0x390c 0x3f73 0x3b64 0x399a 0x3924 0x390b 0x3f65 0x3b56 0x398e 0x391c 0x3906 0x3f55 0x3b62 0x3992 0x3919 0x3903 0x3f1e 0x3b70 0x39a4 0x3927 0x390a 0x3ec0 0x3b64 0x39ac 0x3933 0x3912 0x3e70 0x3b3f 0x3999 0x392a 0x390c 0x3e3a 0x3b22 0x3982 0x3915 0x38fe 0x3e0f 0x3b10 0x3982 0x3914 0x38fc 0x3df2 0x3b06 0x3991 0x3936 0x3915 0x3ddc 0x3b09 0x39a5 0x3953 0x3930 0x3dd2 0x3b19 0x39c1 0x3956 0x3934 0x3dd2 0x3b2e 0x39d7 0x3953 0x3934 0x3dd7 0x3b4e 0x39d6 0x394f 0x3932 0x3ddc 0x3b6d 0x39c9 0x3948 0x392b 0x3de1 0x3b75 0x39be 0x3942 0x3924 0x3de6 0x3b75 0x39b8 0x393d 0x391f 0x3dea 0x3b74 0x39b4 0x3938 0x391c 0x3dee 0x3b6e 0x39b1 0x3935 0x3919 0x3df0 0x3b64 0x39ae 0x3931 0x3916 0x3df0 0x3b5c 0x39ab 0x392e 0x3913 0x3df0 0x3b54 0x39a9 0x392b 0x3910 0x3def 0x3b4c 0x39a8 0x3928 0x390d 0x3ded 0x3b46 0x39a7 0x3928 0x390c 0x3deb 0x3b40 0x39a7 0x3929 0x390c 0x3deb 0x3b3c 0x39a6 0x392a 0x390c 0x3ded 0x3b38 0x39a4 0x392c 0x390f 0x3def 0x3b35 0x39a2 0x392d 0x3913 0x3def 0x3b35 0x39a0 0x392d 0x3914 0x3dee 0x3b36 0x399f 0x392a 0x3912 0x3deb 0x3b36 0x399e 0x3928 0x3910 0x3de2 0x3b35 0x399d 0x3927 0x3910 0x3dd8 0x3b34 0x399b 0x3927 0x390f 0x3dcd 0x3b2c 0x3997 0x3926 0x390f 0x3da1 0x3b16 0x398b 0x391d 0x3908 0x3d94 0x3b10 0x397f 0x3911 0x38f9 0x3d93 0x3b0a 0x397c 0x390a 0x38f2 0x3d8f 0x3b0c 0x3979 0x3906 0x38ec 0x3d8d 0x3b07 0x3977 0x3903 0x38ea 0x3d95 0x3b0c 0x397c 0x390d 0x38f8 0x3da1 0x3b20 0x3983 0x3914 0x38ff 0x3dbd 0x3b30 0x398c 0x3918 0x3902 0x3de0 0x3b45 0x3993 0x391d 0x3906 0x3e15 0x3b6d 0x39a2 0x3924 0x390d 0x3e15 0x3b6d 0x39a2 0x3924 0x390d 0x3e15 0x3b6d 0x39a2 0x3924 0x390d>;
|
|
};
|
|
|
|
qcom,pc-temp-y1-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x1dae 0x1a6c 0x17b7 0x1540 0x1467 0x143b 0x1db4 0x1a6f 0x17c3 0x153f 0x1466 0x143d 0x1dc0 0x1a74 0x17ca 0x153e 0x1466 0x143e 0x1dcd 0x1a7a 0x17ce 0x153c 0x1466 0x1440 0x1dd8 0x1a7e 0x17d0 0x153b 0x1467 0x1441 0x1ddd 0x1a80 0x17d0 0x153a 0x1467 0x1443 0x1ddc 0x1a80 0x17cc 0x153a 0x1468 0x1443 0x1dda 0x1a80 0x17c6 0x153a 0x146a 0x1444 0x1dd3 0x1a7d 0x17c5 0x153b 0x146c 0x1445 0x1dbc 0x1a76 0x17c8 0x153c 0x146d 0x1446 0x1daa 0x1a70 0x17ca 0x153d 0x146f 0x1448 0x1db3 0x1a6e 0x17c6 0x153d 0x1470 0x1449 0x1dc8 0x1a6f 0x17c0 0x153d 0x1472 0x144b 0x1ddc 0x1a74 0x17c1 0x153e 0x1474 0x144d 0x1df4 0x1a85 0x17d0 0x1545 0x1479 0x1452 0x1e03 0x1a97 0x17db 0x154d 0x147c 0x1454 0x1dfa 0x1aa4 0x17df 0x154f 0x147c 0x1455 0x1de7 0x1aaf 0x17e3 0x1552 0x147d 0x1455 0x1dd8 0x1ab0 0x17e4 0x1554 0x147e 0x1456 0x1dca 0x1aa1 0x17e2 0x1555 0x1480 0x1459 0x1dc3 0x1a95 0x17e2 0x1558 0x1483 0x145c 0x1dd6 0x1a97 0x17ed 0x155c 0x1487 0x1460 0x1df9 0x1a9f 0x17fb 0x1560 0x148b 0x1463 0x1e01 0x1aa5 0x17fd 0x1565 0x148e 0x1467 0x1e00 0x1aa8 0x17f8 0x1569 0x1491 0x146a 0x1e04 0x1aac 0x17f7 0x156d 0x1493 0x146e 0x1e09 0x1ab8 0x1800 0x1571 0x1496 0x1472 0x1e0c 0x1acc 0x180b 0x1576 0x149a 0x1475 0x1e0a 0x1ad7 0x180e 0x157b 0x149d 0x1478 0x1df8 0x1adc 0x1812 0x1581 0x14a0 0x147a 0x1de0 0x1ade 0x1817 0x1586 0x14a3 0x147d 0x1dd9 0x1adb 0x181b 0x158b 0x14a7 0x1480 0x1ddb 0x1ad7 0x181f 0x1590 0x14aa 0x1484 0x1ddd 0x1ad7 0x1820 0x1593 0x14ad 0x1487 0x1de1 0x1ad5 0x1821 0x1596 0x14b0 0x1489 0x1de8 0x1ad3 0x1823 0x1599 0x14b2 0x148b 0x1df7 0x1adf 0x1827 0x159b 0x14b4 0x148c 0x1e0a 0x1aef 0x182c 0x159d 0x14b5 0x148d 0x1e0d 0x1aef 0x1831 0x159e 0x14b5 0x148e 0x1dff 0x1ae3 0x1835 0x159f 0x14b6 0x148e 0x1df5 0x1adf 0x183a 0x15a1 0x14b7 0x148f 0x1df6 0x1ae5 0x1841 0x15a5 0x14b9 0x1491 0x1df6 0x1aeb 0x184c 0x15a8 0x14ba 0x1492 0x1df6 0x1af2 0x1849 0x15aa 0x14bb 0x1493 0x1dfa 0x1af8 0x1850 0x15af 0x14be 0x1495 0x1e04 0x1b0b 0x1850 0x15b1 0x14be 0x1496 0x1e09 0x1b08 0x1859 0x15b4 0x14be 0x1496 0x1e26 0x1b0e 0x1863 0x15b4 0x14be 0x1496 0x1e37 0x1b0b 0x186b 0x15b6 0x14bf 0x1496 0x1e2c 0x1b1e 0x1867 0x15b9 0x14c2 0x1498 0x1e29 0x1b3f 0x1879 0x15c2 0x14c5 0x149b 0x1e38 0x1b5b 0x1895 0x15d1 0x14cc 0x14a0 0x1e61 0x1b5f 0x18a8 0x15e4 0x14d3 0x14a6 0x1eb6 0x1b7e 0x18ca 0x15f7 0x14dc 0x14ac 0x1eb6 0x1b7e 0x18ca 0x15f7 0x14dc 0x14ac 0x1eb6 0x1b7e 0x18ca 0x15f7 0x14dc 0x14ac>;
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|
};
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|
|
|
qcom,pc-temp-y2-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x25d6 0x28a1 0x29b8 0x2b2a 0x2b60 0x2c89 0x2638 0x287f 0x299b 0x2b15 0x2b62 0x2c51 0x2674 0x286a 0x297a 0x2afb 0x2b61 0x2bfc 0x2693 0x285f 0x2959 0x2ade 0x2b5e 0x2ba2 0x269f 0x285b 0x293d 0x2abd 0x2b58 0x2b5a 0x26a2 0x285a 0x292b 0x2a9a 0x2b51 0x2b3c 0x266c 0x2867 0x2922 0x2a6d 0x2b48 0x2b43 0x260b 0x287d 0x291b 0x2a3f 0x2b3b 0x2b4e 0x25f2 0x2878 0x2916 0x2a29 0x2b28 0x2b4d 0x25fe 0x283e 0x2912 0x2a1c 0x2b09 0x2b3a 0x2615 0x2814 0x2910 0x2a13 0x2ae5 0x2b24 0x2698 0x2862 0x291a 0x2a04 0x2ab6 0x2afb 0x2784 0x28ea 0x2933 0x29f0 0x2a85 0x2ac3 0x27ba 0x2909 0x295a 0x29f2 0x2a7a 0x2abc 0x26d8 0x28f6 0x29a8 0x2a1d 0x2a90 0x2af0 0x2601 0x28e9 0x29e0 0x2a53 0x2ab0 0x2b19 0x25e5 0x28ff 0x29fa 0x2a91 0x2aec 0x2b1b 0x25de 0x2924 0x2a0e 0x2ad0 0x2b33 0x2b18 0x25d8 0x292d 0x2a1d 0x2aef 0x2b47 0x2b23 0x25d2 0x292c 0x2a2b 0x2afc 0x2b48 0x2b59 0x25cd 0x2929 0x2a36 0x2b0a 0x2b4a 0x2b9b 0x25ca 0x28f3 0x2a3f 0x2b29 0x2b78 0x2bd9 0x25c8 0x2849 0x2a48 0x2b54 0x2bc0 0x2c13 0x25c6 0x27d1 0x2a4b 0x2b74 0x2be2 0x2c3d 0x25c3 0x275f 0x2a50 0x2b8f 0x2bf6 0x2c5c 0x25c0 0x271c 0x2a54 0x2ba1 0x2c07 0x2c71 0x25bf 0x270e 0x2a52 0x2bac 0x2c19 0x2c83 0x25be 0x2700 0x2a4a 0x2bb0 0x2c2d 0x2c96 0x25bd 0x26ed 0x2a46 0x2ba7 0x2c35 0x2cb5 0x25bc 0x26d4 0x2a44 0x2b8e 0x2c41 0x2cec 0x25bb 0x26b9 0x2a3f 0x2b80 0x2c4d 0x2d11 0x25bb 0x26a1 0x29e9 0x2b83 0x2c40 0x2d02 0x25ba 0x268b 0x294e 0x2b8f 0x2c2f 0x2cda 0x25b9 0x2672 0x290b 0x2b9c 0x2c33 0x2cca 0x25b8 0x2655 0x28fa 0x2b99 0x2c39 0x2cd1 0x25b8 0x263a 0x28ee 0x2b84 0x2c35 0x2cd6 0x25b7 0x2622 0x28e6 0x2b68 0x2c34 0x2cdc 0x25b7 0x2604 0x290b 0x2b59 0x2c39 0x2ce8 0x25b6 0x25ec 0x293c 0x2b5f 0x2c3b 0x2ce7 0x25b6 0x25de 0x291d 0x2b60 0x2c36 0x2cd1 0x25b6 0x25d4 0x28ba 0x2b5f 0x2c32 0x2cc5 0x25b6 0x25cb 0x289c 0x2b62 0x2c34 0x2ccc 0x25b6 0x25c4 0x28a6 0x2b5d 0x2c32 0x2ccf 0x25b5 0x25be 0x281b 0x2b46 0x2c13 0x2cc8 0x25b5 0x25bb 0x27d7 0x2b34 0x2c13 0x2cb0 0x25b5 0x25bb 0x27c4 0x2b11 0x2c20 0x2c82 0x25b5 0x25ba 0x2810 0x2b0d 0x2c0a 0x2c51 0x25b5 0x25b9 0x2851 0x2b23 0x2be8 0x2c48 0x25b5 0x25b8 0x2853 0x2b28 0x2bef 0x2c50 0x25b4 0x25b8 0x2837 0x2ae6 0x2c1e 0x2c3a 0x25b4 0x25b6 0x2800 0x2acc 0x2bf7 0x2bfd 0x25b4 0x25b5 0x27bc 0x2aa1 0x2b7e 0x2ba7 0x25b4 0x25b4 0x2786 0x2a49 0x2b0f 0x2b35 0x25b2 0x25b4 0x2773 0x2a1c 0x2a4f 0x2a4a 0x25b2 0x25b4 0x2773 0x2a1c 0x2a4f 0x2a4a 0x25b2 0x25b4 0x2773 0x2a1c 0x2a4f 0x2a4a>;
|
|
};
|
|
|
|
qcom,pc-temp-y3-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x347a 0x3456 0x3421 0x33e5 0x33e0 0x33d8 0x356b 0x345f 0x341a 0x33e4 0x33e0 0x33da 0x35ff 0x346c 0x3416 0x33e3 0x33e0 0x33db 0x364d 0x3479 0x3416 0x33e3 0x33e0 0x33dd 0x366b 0x3484 0x3418 0x33e3 0x33e0 0x33de 0x3670 0x3489 0x341c 0x33e5 0x33e0 0x33de 0x35ec 0x3489 0x3423 0x33e8 0x33e0 0x33de 0x34fc 0x3488 0x342b 0x33ed 0x33e1 0x33de 0x34bb 0x348b 0x342e 0x33ef 0x33e1 0x33de 0x34ba 0x349e 0x342f 0x33f0 0x33e1 0x33dd 0x34bb 0x34ac 0x3430 0x33f0 0x33e1 0x33dd 0x34d3 0x349e 0x343d 0x33f7 0x33e4 0x33df 0x3504 0x3481 0x3450 0x3401 0x33e9 0x33e2 0x3510 0x3471 0x3451 0x3402 0x33ea 0x33e3 0x34ec 0x3468 0x343b 0x33fe 0x33e8 0x33e2 0x34cc 0x3462 0x3427 0x33fb 0x33e6 0x33e2 0x34d0 0x345f 0x3422 0x33fd 0x33e8 0x33e2 0x34e0 0x345d 0x341f 0x3401 0x33ec 0x33e3 0x34e7 0x345a 0x341b 0x3401 0x33ec 0x33e3 0x34e9 0x3455 0x3416 0x33f9 0x33e7 0x33e0 0x34ea 0x344f 0x3411 0x33f0 0x33e3 0x33dd 0x34ec 0x3445 0x340c 0x33e8 0x33e1 0x33dc 0x34f0 0x3435 0x3407 0x33e3 0x33e0 0x33db 0x34f5 0x3427 0x3406 0x33e2 0x33df 0x33db 0x3500 0x341c 0x3405 0x33e3 0x33de 0x33db 0x3512 0x3417 0x3405 0x33e4 0x33de 0x33da 0x3525 0x3418 0x3405 0x33e3 0x33de 0x33da 0x3539 0x341b 0x3405 0x33e3 0x33dd 0x33da 0x354f 0x341f 0x3405 0x33e5 0x33dd 0x33da 0x356b 0x3423 0x3405 0x33e9 0x33dd 0x33d9 0x358d 0x3428 0x3405 0x33ec 0x33dd 0x33d9 0x35b2 0x342d 0x3400 0x33ed 0x33de 0x33d9 0x35da 0x3434 0x33f9 0x33ec 0x33de 0x33da 0x360a 0x343c 0x33f6 0x33ec 0x33df 0x33da 0x3641 0x3449 0x33f7 0x33ea 0x33de 0x33da 0x3680 0x3458 0x33f8 0x33e8 0x33de 0x33d9 0x36c1 0x3468 0x33fb 0x33e6 0x33de 0x33d9 0x3702 0x347a 0x3402 0x33e4 0x33dd 0x33d9 0x3742 0x3490 0x3408 0x33e3 0x33dd 0x33d9 0x3781 0x34b0 0x340c 0x33e3 0x33dd 0x33d9 0x37c1 0x34dc 0x340f 0x33e3 0x33dd 0x33d9 0x3803 0x3511 0x3415 0x33e3 0x33de 0x33da 0x3845 0x3550 0x341e 0x33e3 0x33de 0x33da 0x3892 0x35a3 0x3421 0x33e4 0x33de 0x33da 0x38ea 0x3613 0x3429 0x33e3 0x33de 0x33da 0x390d 0x3642 0x3430 0x33eb 0x33df 0x33dc 0x393f 0x363e 0x3435 0x33ec 0x33e1 0x33dd 0x395c 0x3658 0x3442 0x33f0 0x33e3 0x33e0 0x398d 0x36b9 0x3451 0x33f2 0x33e2 0x33e0 0x3a0b 0x3718 0x3452 0x33ee 0x33e1 0x33dd 0x3a97 0x37a6 0x345a 0x33f0 0x33e0 0x33dd 0x3b31 0x3888 0x346f 0x33f5 0x33e3 0x33e1 0x3c10 0x3978 0x3492 0x33f9 0x33e6 0x33e4 0x3f2c 0x3a7b 0x34ca 0x3403 0x33ea 0x33e6 0x3f2c 0x3a7b 0x34ca 0x3403 0x33ea 0x33e6 0x3f2c 0x3a7b 0x34ca 0x3403 0x33ea 0x33e6>;
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|
};
|
|
|
|
qcom,pc-temp-y4-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x45b5 0x41d2 0x40f2 0x406d 0x4045 0x4044 0x452b 0x41db 0x40ef 0x4073 0x4045 0x4042 0x44eb 0x41eb 0x40ef 0x4078 0x4047 0x4041 0x44e9 0x4200 0x40f2 0x407b 0x4048 0x4040 0x4515 0x421b 0x40f7 0x407d 0x404a 0x4040 0x4561 0x4239 0x40fe 0x407e 0x404b 0x4040 0x4627 0x4263 0x4106 0x407c 0x404d 0x4041 0x478b 0x428e 0x4111 0x407a 0x404e 0x4044 0x4914 0x42a4 0x411c 0x407a 0x4051 0x4046 0x4b24 0x42ad 0x4127 0x4081 0x4055 0x4049 0x4c74 0x42bc 0x4138 0x408c 0x405b 0x404d 0x4a3e 0x4407 0x419f 0x409e 0x4069 0x4059 0x4560 0x4626 0x4237 0x40b4 0x407d 0x4068 0x437a 0x4642 0x4251 0x40bd 0x4081 0x406c 0x4347 0x43a8 0x4203 0x40bf 0x407d 0x406b 0x432d 0x41b1 0x41aa 0x40c3 0x407b 0x406a 0x4320 0x41b5 0x416e 0x40ec 0x4091 0x407a 0x430d 0x41e2 0x413b 0x4129 0x40ba 0x4098 0x42ef 0x41ed 0x4117 0x412a 0x40c0 0x409d 0x42b4 0x41c5 0x40fa 0x40d1 0x4094 0x407d 0x4274 0x4198 0x40e3 0x4085 0x4066 0x405b 0x4249 0x4180 0x40d4 0x4078 0x4054 0x404d 0x4228 0x416e 0x40c8 0x4072 0x4049 0x4043 0x421f 0x416b 0x40c2 0x406f 0x4048 0x4042 0x4223 0x415f 0x40be 0x406b 0x4048 0x4042 0x422b 0x414f 0x40bb 0x4069 0x4049 0x4043 0x4231 0x4143 0x40ba 0x406b 0x404b 0x4045 0x423b 0x4137 0x40ba 0x406d 0x404e 0x4048 0x4246 0x4136 0x40b9 0x406e 0x4051 0x404c 0x4252 0x4142 0x40b4 0x4070 0x4057 0x4051 0x425e 0x4154 0x40b0 0x4072 0x405e 0x4058 0x426a 0x4167 0x40b4 0x4074 0x4068 0x4063 0x4276 0x417f 0x40bd 0x4076 0x4073 0x4070 0x4283 0x4198 0x40c4 0x4074 0x4075 0x4072 0x4290 0x41b2 0x40c9 0x4069 0x4064 0x4061 0x429c 0x41cd 0x40cd 0x405e 0x404f 0x404c 0x42a8 0x41ef 0x40d2 0x405b 0x4044 0x4043 0x42b5 0x421f 0x40d8 0x4059 0x403e 0x403f 0x42c7 0x4244 0x40dc 0x405a 0x403e 0x4040 0x42e1 0x4252 0x40e9 0x405d 0x4042 0x4045 0x4308 0x425c 0x40fd 0x4060 0x4047 0x404a 0x433b 0x4262 0x410c 0x4063 0x4048 0x404b 0x437e 0x4270 0x4118 0x4064 0x4046 0x4048 0x43d3 0x4287 0x4129 0x4061 0x403d 0x403b 0x442a 0x42c2 0x4147 0x406b 0x4041 0x403e 0x441b 0x42ef 0x4160 0x4075 0x4057 0x405a 0x441e 0x4307 0x4166 0x4084 0x4070 0x4078 0x43ed 0x432a 0x4193 0x40a2 0x4099 0x40a2 0x43d0 0x436e 0x41e6 0x40be 0x409c 0x4098 0x43e5 0x4383 0x41de 0x409e 0x406e 0x4064 0x43f6 0x4384 0x41d8 0x409e 0x4060 0x4059 0x4411 0x43a0 0x41fb 0x40bd 0x4070 0x4067 0x4463 0x43f1 0x4266 0x40fb 0x4090 0x4085 0x470a 0x44a2 0x432d 0x41de 0x4141 0x4118 0x470a 0x44a2 0x432d 0x41de 0x4141 0x4118 0x470a 0x44a2 0x432d 0x41de 0x4141 0x4118>;
|
|
};
|
|
|
|
qcom,pc-temp-y5-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x2208 0x348a 0x3ab0 0x3545 0x4573 0x3634 0x2208 0x34aa 0x3839 0x3326 0x4393 0x3e82 0x269f 0x34e2 0x3660 0x31db 0x419b 0x43da 0x2f8b 0x3522 0x3519 0x3130 0x3fbf 0x46e0 0x3428 0x3557 0x345a 0x30f0 0x3e34 0x4838 0x3590 0x3572 0x341a 0x30e7 0x3d2f 0x4884 0x30ee 0x3576 0x34b3 0x32d3 0x3ca4 0x46c7 0x2869 0x3578 0x35a4 0x35e5 0x3c3f 0x4385 0x267f 0x34b6 0x35c2 0x3648 0x3b81 0x4119 0x2a54 0x3032 0x3545 0x34d0 0x3996 0x3e92 0x2ff6 0x2cf8 0x3494 0x33cf 0x387f 0x3ce5 0x37e1 0x2fd6 0x333d 0x3525 0x3964 0x3cfd 0x4112 0x360e 0x319c 0x3768 0x3acb 0x3dbd 0x4280 0x3a64 0x326c 0x37dc 0x3b0d 0x3dbf 0x373b 0x3dd4 0x395e 0x3745 0x3a7a 0x3cb2 0x2cf9 0x3f72 0x3eca 0x36d1 0x3a41 0x3bb0 0x2d03 0x3ec5 0x3f83 0x384b 0x3ae8 0x3b5d 0x2edc 0x3dc2 0x3fc3 0x3b9d 0x3c38 0x3b2b 0x2f8c 0x3d9a 0x3f92 0x3dc7 0x3e57 0x3b93 0x2f1e 0x3df3 0x3ecf 0x3f34 0x4225 0x3e9f 0x2e5c 0x3e54 0x3de6 0x3fc8 0x445b 0x4233 0x2d64 0x3c6d 0x3c08 0x3c17 0x4527 0x44e0 0x2c30 0x3697 0x3971 0x3578 0x4604 0x471b 0x2b6b 0x3248 0x38a0 0x33d2 0x4627 0x47ff 0x2b06 0x2f1a 0x38d8 0x353a 0x4512 0x484d 0x2ad4 0x2d6f 0x3925 0x3660 0x43d2 0x484f 0x2add 0x2d4c 0x3975 0x3678 0x4315 0x4790 0x2aec 0x2d55 0x39cc 0x366c 0x4294 0x45bc 0x2af3 0x2d44 0x3a34 0x38ed 0x427b 0x43ff 0x2b16 0x2d12 0x3b09 0x40ee 0x4270 0x426f 0x2b4e 0x2d07 0x3ba6 0x465a 0x4280 0x41aa 0x2b80 0x2d07 0x38cb 0x47e5 0x43ef 0x42bb 0x2ba9 0x2cec 0x3382 0x48db 0x472c 0x45f6 0x2bd0 0x2ce9 0x319e 0x48b8 0x4a98 0x495f 0x2bf8 0x2d41 0x31a4 0x45bb 0x4e8c 0x4c69 0x2c20 0x2daa 0x31b5 0x4185 0x51da 0x4ea9 0x2c45 0x2dd9 0x3221 0x3e14 0x52fb 0x508e 0x2c64 0x2d8a 0x34af 0x3aee 0x5257 0x524a 0x2c6c 0x2d32 0x3713 0x3918 0x50bc 0x5292 0x2c5a 0x2d52 0x36de 0x38bf 0x4e90 0x50e7 0x2c45 0x2d99 0x34f7 0x3913 0x4dbc 0x4f8f 0x2c53 0x2da9 0x354f 0x3906 0x4ea8 0x5136 0x2cb7 0x2d71 0x370b 0x3898 0x515e 0x56c7 0x2d6c 0x2d2c 0x33cd 0x3962 0x555b 0x5c52 0x2e6e 0x2cc8 0x325a 0x3610 0x4cc2 0x4ea4 0x2fc4 0x2d10 0x320a 0x3e49 0x4394 0x4373 0x30b0 0x2d1b 0x3431 0x3e08 0x42cc 0x40b6 0x322c 0x2e86 0x370e 0x4092 0x40be 0x3f21 0x3256 0x3099 0x3915 0x3fe1 0x3e27 0x3e5b 0x322c 0x3127 0x38b1 0x3e5f 0x428d 0x410e 0x3117 0x3039 0x38e1 0x4283 0x4414 0x4431 0x2f77 0x2f18 0x37f8 0x4528 0x4741 0x4a06 0x2e6f 0x2e5e 0x37ca 0x4396 0x477b 0x4ab1 0x2b65 0x2d9d 0x3932 0x4343 0x45a6 0x476b 0x2b65 0x2d9d 0x3932 0x4343 0x45a6 0x476b 0x2b65 0x2d9d 0x3932 0x4343 0x45a6 0x476b>;
|
|
};
|
|
|
|
qcom,pc-temp-y6-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x1af4 0x1607 0x1492 0x13c9 0x139d 0x1392 0x1afb 0x160e 0x148d 0x13c8 0x139d 0x1393 0x1aff 0x1616 0x148a 0x13c7 0x139d 0x1394 0x1aff 0x161e 0x148a 0x13c8 0x139d 0x1395 0x1afc 0x1626 0x148c 0x13c9 0x139e 0x1395 0x1af7 0x162e 0x148e 0x13ca 0x139f 0x1396 0x1ac7 0x1636 0x1494 0x13cc 0x139f 0x1397 0x1a78 0x163e 0x149c 0x13cf 0x13a1 0x1397 0x1a74 0x1646 0x14a1 0x13d2 0x13a2 0x1398 0x1aff 0x164c 0x14a3 0x13d4 0x13a3 0x1399 0x1b70 0x1657 0x14a8 0x13d7 0x13a5 0x139a 0x1af4 0x16ac 0x14cc 0x13e2 0x13ac 0x139f 0x19d3 0x172c 0x1503 0x13ef 0x13b5 0x13a6 0x1941 0x172c 0x150b 0x13f2 0x13b7 0x13a8 0x190e 0x1670 0x14e5 0x13f1 0x13b5 0x13a7 0x18f6 0x15e2 0x14be 0x13f0 0x13b3 0x13a7 0x18fb 0x15e4 0x14ab 0x13fd 0x13bb 0x13ac 0x1909 0x15f5 0x149c 0x1412 0x13c9 0x13b5 0x190d 0x15f9 0x148f 0x1412 0x13cb 0x13b7 0x190c 0x15ed 0x1483 0x13f3 0x13bb 0x13ab 0x190a 0x15e0 0x147a 0x13d6 0x13ab 0x139f 0x190d 0x15d6 0x1473 0x13cd 0x13a4 0x139a 0x191a 0x15ce 0x146e 0x13c8 0x13a1 0x1397 0x192c 0x15c9 0x146d 0x13c7 0x13a0 0x1397 0x1945 0x15c7 0x146e 0x13c7 0x13a0 0x1397 0x1964 0x15c6 0x146f 0x13c8 0x13a0 0x1398 0x1982 0x15cb 0x1470 0x13c9 0x13a1 0x1398 0x19a0 0x15d5 0x1473 0x13ca 0x13a2 0x1399 0x19c0 0x15e2 0x1475 0x13cc 0x13a3 0x139a 0x19e6 0x15f3 0x1476 0x13d0 0x13a5 0x139c 0x1a11 0x1607 0x1477 0x13d4 0x13a7 0x139e 0x1a3f 0x161d 0x1478 0x13d6 0x13ab 0x13a2 0x1a72 0x1638 0x1479 0x13d7 0x13af 0x13a6 0x1aa7 0x1655 0x147b 0x13d6 0x13b0 0x13a7 0x1ae0 0x1676 0x147f 0x13d2 0x13ab 0x13a2 0x1b1c 0x169b 0x1483 0x13ce 0x13a5 0x139c 0x1b59 0x16c6 0x1488 0x13cc 0x13a2 0x139a 0x1b96 0x16f8 0x1490 0x13cb 0x13a0 0x1398 0x1bd4 0x1732 0x149a 0x13ca 0x13a0 0x1399 0x1c13 0x1772 0x14a5 0x13cb 0x13a1 0x139a 0x1c51 0x17bc 0x14b0 0x13cd 0x13a3 0x139c 0x1c90 0x1811 0x14bf 0x13ce 0x13a4 0x139d 0x1cd3 0x1875 0x14d0 0x13cf 0x13a3 0x139c 0x1d22 0x18ef 0x14e0 0x13d0 0x13a1 0x1399 0x1d80 0x1984 0x14f9 0x13d2 0x13a3 0x139a 0x1da5 0x19b9 0x150c 0x13db 0x13a9 0x13a3 0x1dcf 0x19c4 0x1513 0x13e1 0x13b2 0x13ad 0x1dde 0x19e7 0x152f 0x13ec 0x13bf 0x13bb 0x1e04 0x1a57 0x155a 0x13f6 0x13c0 0x13b8 0x1e6d 0x1abf 0x1560 0x13eb 0x13b2 0x13a7 0x1edf 0x1b41 0x1573 0x13ee 0x13ae 0x13a5 0x1f66 0x1c0d 0x15ab 0x13fd 0x13b6 0x13ac 0x2034 0x1cdf 0x160e 0x1415 0x13c2 0x13b7 0x23c8 0x1de5 0x16a3 0x1461 0x13f8 0x13e4 0x23c8 0x1de5 0x16a3 0x1461 0x13f8 0x13e4 0x23c8 0x1de5 0x16a3 0x1461 0x13f8 0x13e4>;
|
|
};
|
|
};
|
|
|
|
qcom,mlp466076_3200mAh {
|
|
qcom,max-voltage-uv = <0x432380>;
|
|
qcom,fg-cc-cv-threshold-mv = <0x1126>;
|
|
qcom,fastchg-current-ma = <0x1770>;
|
|
qcom,batt-id-kohm = <0x85>;
|
|
qcom,battery-beta = <0x109a>;
|
|
qcom,battery-therm-kohm = <0x64>;
|
|
qcom,battery-type = "mlp466076_3200mAh_averaged_MasterSlave_Sept28th2018";
|
|
qcom,qg-batt-profile-ver = <0x64>;
|
|
qcom,jeita-fcc-ranges = <0x00 0x96 0x9eb10 0x97 0x1c2 0x4a62f8 0x1c3 0x226 0x18cba8>;
|
|
qcom,jeita-fv-ranges = <0x00 0x96 0x3f52f0 0x97 0x1c2 0x432380 0x1c3 0x226 0x3f52f0>;
|
|
qcom,jeita-soft-thresholds = <0x4621 0x20b8>;
|
|
qcom,jeita-hard-thresholds = <0x58cd 0x181d>;
|
|
qcom,jeita-soft-hys-thresholds = <0x4206 0x23c0>;
|
|
qcom,jeita-soft-fcc-ua = <0x9eb10 0x18cba8>;
|
|
qcom,jeita-soft-fv-uv = <0x3f52f0 0x3f52f0>;
|
|
|
|
qcom,fcc1-temp-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-data = <0xc85 0xcb0 0xcea 0xd00 0xd00>;
|
|
};
|
|
|
|
qcom,fcc2-temp-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-data = <0xc2e 0xc83 0xcb5 0xcf2 0xcff 0xd05>;
|
|
};
|
|
|
|
qcom,pc-temp-v1-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0xaa8e 0xaaf5 0xab33 0xab4e 0xab51 0xa9c9 0xaa48 0xaa80 0xaa9f 0xaaa0 0xa8ec 0xa96b 0xa9b1 0xa9d5 0xa9d2 0xa7fc 0xa887 0xa8d3 0xa8ff 0xa8f6 0xa722 0xa7a7 0xa7ef 0xa81f 0xa810 0xa66b 0xa6c4 0xa70a 0xa736 0xa726 0xa5b9 0xa5e0 0xa622 0xa648 0xa63d 0xa4e7 0xa4ff 0xa53d 0xa55a 0xa556 0xa3fc 0xa420 0xa459 0xa470 0xa475 0xa31f 0xa345 0xa379 0xa38a 0xa393 0xa255 0xa270 0xa29b 0xa2aa 0xa2b2 0xa192 0xa1a2 0xa1c3 0xa1d0 0xa1d4 0xa0cb 0xa0da 0xa0f2 0xa0f9 0xa0fa 0xa001 0xa011 0xa029 0xa027 0xa027 0x9f38 0x9f44 0x9f5f 0x9f5a 0x9f59 0x9e73 0x9e7a 0x9e92 0x9e95 0x9e95 0x9da6 0x9db4 0x9dcc 0x9dd5 0x9dd7 0x9cd1 0x9cf2 0x9d1d 0x9d21 0x9d22 0x9c09 0x9c42 0x9c75 0x9c75 0x9c72 0x9b6d 0x9bae 0x9ba7 0x9bb2 0x9bad 0x9ae6 0x9b1f 0x9a98 0x9abc 0x9ac4 0x9a6b 0x9a5f 0x99ab 0x99cf 0x99df 0x99f4 0x995f 0x9908 0x9916 0x9920 0x9972 0x988c 0x9880 0x9878 0x9877 0x98dd 0x9805 0x9807 0x97ec 0x97e4 0x9848 0x97a0 0x979c 0x976f 0x9766 0x97ca 0x9750 0x9738 0x96ff 0x96f5 0x9764 0x9710 0x96d6 0x9699 0x968d 0x970c 0x96d1 0x967c 0x963b 0x962c 0x96c3 0x9690 0x962d 0x95e6 0x95d2 0x9685 0x9653 0x95e6 0x9599 0x957e 0x964b 0x961d 0x95a6 0x9552 0x9533 0x961e 0x95eb 0x956d 0x9516 0x94f2 0x9601 0x95ba 0x9537 0x94db 0x94b3 0x95e9 0x958f 0x9509 0x94a1 0x9473 0x95ca 0x9562 0x94dd 0x9466 0x9430 0x958d 0x9532 0x94a9 0x9427 0x93eb 0x9544 0x94fd 0x946d 0x93e4 0x93a2 0x9500 0x94b6 0x9423 0x9397 0x9351 0x94b5 0x944c 0x93be 0x9335 0x92ec 0x9456 0x93cc 0x9342 0x92c3 0x9277 0x93cd 0x933b 0x92b8 0x923f 0x91ef 0x9329 0x92a1 0x921e 0x91a9 0x9156 0x927e 0x9221 0x9180 0x9112 0x90c8 0x91e1 0x91a4 0x9108 0x909f 0x905e 0x9176 0x9140 0x90ca 0x9069 0x9028 0x9154 0x911f 0x90ba 0x9055 0x9017 0x9133 0x9101 0x90a8 0x9044 0x9009 0x910e 0x90df 0x9087 0x9022 0x8fe3 0x90a1 0x9067 0x8ff2 0x8f78 0x8f22 0x8f5d 0x8f18 0x8e9d 0x8e1b 0x8dbd 0x8d8f 0x8d47 0x8cd0 0x8c4c 0x8bf0 0x8b41 0x8af8 0x8a84 0x89ff 0x89a4 0x8824 0x87da 0x876a 0x86e5 0x868b 0x8356 0x8319 0x82b6 0x8232 0x81d6 0x7530 0x7530 0x7530 0x7530 0x7530>;
|
|
};
|
|
|
|
qcom,pc-temp-v2-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0xa97e 0xaa7d 0xaae6 0xab27 0xab18 0xab13 0xa7e7 0xa8fa 0xa9b1 0xaa31 0xaa3a 0xaa3e 0xa670 0xa798 0xa88d 0xa93f 0xa95a 0xa966 0xa51e 0xa65c 0xa77d 0xa851 0xa879 0xa889 0xa3e9 0xa540 0xa67f 0xa768 0xa798 0xa7a9 0xa2d3 0xa43a 0xa589 0xa67f 0xa6b4 0xa6c6 0xa1de 0xa33f 0xa496 0xa597 0xa5ce 0xa5df 0xa116 0xa24a 0xa3a9 0xa4b0 0xa4e7 0xa4f8 0xa066 0xa165 0xa2c2 0xa3ce 0xa403 0xa413 0x9f8e 0xa099 0xa1de 0xa2ee 0xa320 0xa32f 0x9e79 0xa008 0xa103 0xa211 0xa241 0xa24e 0x9d7f 0x9f69 0xa03a 0xa136 0xa167 0xa171 0x9ca7 0x9e72 0x9f7b 0xa061 0xa090 0xa097 0x9ba4 0x9d43 0x9eb9 0x9f98 0x9fbf 0x9fc4 0x9a7a 0x9c11 0x9de5 0x9ed2 0x9ef1 0x9ef5 0x9988 0x9b41 0x9d08 0x9e07 0x9e2a 0x9e2e 0x98cd 0x9a96 0x9c2f 0x9d35 0x9d69 0x9d6e 0x982c 0x99d2 0x9b58 0x9c6b 0x9cab 0x9cb2 0x9789 0x98f4 0x9a7a 0x9bb5 0x9bf5 0x9bfd 0x96f4 0x981a 0x9993 0x9afc 0x9b37 0x9b3f 0x9677 0x9756 0x98be 0x9a16 0x9a4b 0x9a51 0x960b 0x96a6 0x97ff 0x990f 0x9942 0x994b 0x95b4 0x9615 0x975a 0x983d 0x9875 0x9881 0x9571 0x959e 0x96c8 0x97a1 0x97db 0x97e7 0x9537 0x9543 0x9645 0x971b 0x9755 0x9760 0x9502 0x9501 0x95cf 0x96a0 0x96d9 0x96e4 0x94d2 0x94cb 0x9565 0x9632 0x9669 0x9673 0x94a4 0x949d 0x9506 0x95cb 0x9600 0x9609 0x9476 0x9474 0x94b1 0x956d 0x95a0 0x95a7 0x9449 0x944c 0x9469 0x9513 0x9546 0x954b 0x941c 0x9425 0x9431 0x94c0 0x94f5 0x94f7 0x93ed 0x93fd 0x9401 0x9471 0x94a9 0x94a9 0x93bb 0x93d2 0x93d4 0x9426 0x9463 0x9461 0x9385 0x93a1 0x93a8 0x93df 0x941f 0x941a 0x934a 0x936f 0x9379 0x9398 0x93ca 0x93bb 0x9309 0x933c 0x9346 0x9354 0x935a 0x933a 0x92c4 0x9301 0x930a 0x930f 0x92e8 0x92bc 0x9277 0x92ba 0x92c5 0x92c1 0x9287 0x9255 0x9226 0x9264 0x9274 0x926e 0x922d 0x91f8 0x91d2 0x9206 0x9217 0x9217 0x91d6 0x919e 0x9179 0x919d 0x91aa 0x91bd 0x917f 0x9142 0x911e 0x912c 0x912f 0x914f 0x9113 0x90d1 0x90c5 0x90b3 0x90ad 0x90c9 0x9094 0x9054 0x906e 0x9041 0x9035 0x9036 0x9000 0x8fc3 0x900a 0x8fe4 0x8fe3 0x8ff2 0x8fcc 0x8f9a 0x8f98 0x8f8e 0x8f9e 0x8fd3 0x8fb4 0x8f82 0x8f52 0x8f5f 0x8f7f 0x8fbd 0x8f9f 0x8f71 0x8ef2 0x8f25 0x8f40 0x8f9d 0x8f86 0x8f55 0x8e59 0x8ec7 0x8ed3 0x8f4b 0x8f3d 0x8ef6 0x8d77 0x8e01 0x8dd9 0x8e72 0x8e51 0x8dd8 0x8c3d 0x8cb0 0x8c57 0x8cd2 0x8cb2 0x8c2e 0x8a66 0x8acc 0x8a5b 0x8ac2 0x8aa7 0x8a1c 0x87dd 0x884b 0x87bf 0x8822 0x8806 0x8772 0x845b 0x84d5 0x842f 0x8489 0x8486 0x8407 0x7f16 0x7f4e 0x7f37 0x7fd7 0x7fc8 0x7f48 0x753b 0x7534 0x7531 0x7530 0x7530 0x752f>;
|
|
};
|
|
|
|
qcom,pc-temp-z1-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x3418 0x31c1 0x2fd5 0x2f1f 0x2efc 0x3409 0x31ab 0x2faa 0x2efd 0x2ec9 0x340d 0x31a5 0x2fb8 0x2ed1 0x2e84 0x3448 0x3196 0x2f9a 0x2ec8 0x2dd0 0x34b8 0x3184 0x2f80 0x2ec1 0x2d77 0x3663 0x3173 0x2f7a 0x2e75 0x2d6f 0x380c 0x3169 0x2f77 0x2e00 0x2d6a 0x383e 0x3165 0x2f72 0x2de9 0x2d67 0x3845 0x315f 0x2f6a 0x2de8 0x2d64 0x3840 0x313e 0x2f63 0x2de7 0x2d61 0x381a 0x311b 0x2f5f 0x2de5 0x2d5f 0x37e0 0x3117 0x2f5e 0x2de1 0x2d5e 0x37b2 0x311b 0x2f5e 0x2dde 0x2d5d 0x3786 0x311c 0x2f5e 0x2ddc 0x2d5a 0x3767 0x312c 0x2f5c 0x2dda 0x2d59 0x373d 0x3199 0x2f55 0x2dd9 0x2d59 0x36fb 0x320a 0x2f51 0x2dd9 0x2d59 0x36bb 0x326a 0x2f54 0x2dd9 0x2d5a 0x368b 0x32ae 0x2f5b 0x2dda 0x2d5a 0x367a 0x32bf 0x2f5c 0x2ddc 0x2d5a 0x3673 0x32c5 0x2f5a 0x2dde 0x2d5a 0x366d 0x32bf 0x2f58 0x2de0 0x2d5c 0x366e 0x32c2 0x2f5f 0x2de3 0x2d5e 0x367a 0x32cd 0x2f69 0x2de6 0x2d61 0x3683 0x32cb 0x2f6c 0x2dea 0x2d64 0x367c 0x32c5 0x2f6c 0x2def 0x2d66 0x3682 0x32c3 0x2f6d 0x2df2 0x2d6a 0x3687 0x32c4 0x2f6f 0x2df4 0x2d6d 0x367e 0x32c5 0x2f72 0x2df5 0x2d71 0x3684 0x32c8 0x2f75 0x2df8 0x2d75 0x36a9 0x32ce 0x2f7b 0x2dff 0x2d79 0x36bf 0x32da 0x2f7d 0x2e04 0x2d7d 0x36c6 0x32eb 0x2f7e 0x2e07 0x2d81 0x36c0 0x32f1 0x2f80 0x2e0a 0x2d85 0x36b3 0x32f1 0x2f88 0x2e0d 0x2d88 0x36a7 0x32f4 0x2f93 0x2e11 0x2d8c 0x36af 0x3302 0x2f97 0x2e17 0x2d90 0x36d2 0x3318 0x2f98 0x2e21 0x2d95 0x36f2 0x3325 0x2f99 0x2e29 0x2d9a 0x370f 0x3335 0x2fa8 0x2e2c 0x2d9f 0x3727 0x3343 0x2fb8 0x2e2e 0x2da4 0x372a 0x3344 0x2fb6 0x2e2f 0x2da7 0x3710 0x3344 0x2fac 0x2e36 0x2daa 0x36fd 0x3343 0x2fae 0x2e37 0x2dad 0x370b 0x334b 0x2fb8 0x2e38 0x2daf 0x3734 0x334e 0x2fbc 0x2e3f 0x2db5 0x371f 0x335f 0x2fc2 0x2e42 0x2db7 0x3713 0x334b 0x2fc7 0x2e45 0x2dbb 0x3739 0x3372 0x2fce 0x2e48 0x2dbe 0x3721 0x336f 0x2fc9 0x2e58 0x2dc5 0x3754 0x3375 0x2fe1 0x2e56 0x2dc8 0x374f 0x339b 0x2fdc 0x2e6b 0x2dcf 0x3739 0x33bf 0x2ffe 0x2e6a 0x2dd8 0x3745 0x33e4 0x3002 0x2e70 0x2de1 0x3745 0x33e4 0x3002 0x2e70 0x2de1 0x3745 0x33e4 0x3002 0x2e70 0x2de1>;
|
|
};
|
|
|
|
qcom,pc-temp-z2-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x2592 0x2669 0x2821 0x295b 0x2975 0x25f5 0x2757 0x27fb 0x28b7 0x2852 0x2627 0x27d7 0x2878 0x28b0 0x2877 0x272b 0x2810 0x288e 0x28c0 0x28b1 0x27a2 0x2810 0x2897 0x28ba 0x28a3 0x267e 0x27fa 0x288c 0x28b0 0x2877 0x2544 0x27ea 0x2877 0x28a3 0x2849 0x258e 0x27e6 0x2869 0x28a0 0x283c 0x2693 0x27e1 0x285e 0x28af 0x2849 0x26ec 0x27dc 0x2859 0x28b7 0x285a 0x26e6 0x27dc 0x2863 0x289c 0x2860 0x26de 0x27e0 0x2871 0x286c 0x2862 0x26da 0x27e3 0x2877 0x2862 0x2863 0x26d7 0x27e8 0x287a 0x2876 0x2862 0x26b6 0x27e2 0x2880 0x2885 0x2861 0x260e 0x27a2 0x288c 0x2881 0x2867 0x25a6 0x277d 0x2896 0x2874 0x2875 0x2620 0x278b 0x2895 0x2871 0x2889 0x26cf 0x279b 0x288f 0x2875 0x289d 0x26ed 0x279e 0x2892 0x287d 0x28aa 0x26fc 0x279e 0x28a0 0x28a4 0x28b0 0x2718 0x27a0 0x28aa 0x28df 0x28b7 0x2698 0x27a6 0x2897 0x291f 0x28e3 0x25f8 0x27ad 0x287b 0x295c 0x2928 0x2633 0x27bb 0x2883 0x295c 0x2922 0x26f4 0x27ca 0x28b3 0x292a 0x28a2 0x2732 0x27cc 0x28ca 0x28fd 0x2847 0x272b 0x27c7 0x28b7 0x28ea 0x2845 0x2728 0x27c5 0x28a3 0x28de 0x2853 0x2726 0x27cc 0x28a3 0x28dc 0x2859 0x2725 0x27d5 0x28a6 0x28dc 0x2858 0x2724 0x27d9 0x28ab 0x28dd 0x285e 0x2723 0x27dd 0x28b9 0x28f2 0x287c 0x26b8 0x27e0 0x28c6 0x2917 0x289f 0x25f6 0x27e4 0x28cd 0x293d 0x28c4 0x25d6 0x27e8 0x28d2 0x2967 0x28f8 0x2690 0x27ec 0x28d9 0x2986 0x2910 0x2736 0x27f2 0x28e1 0x299d 0x290e 0x26f2 0x27f5 0x28e9 0x29ae 0x290e 0x25bd 0x27f8 0x28f8 0x29bd 0x2919 0x24d0 0x27fa 0x2905 0x29c7 0x292e 0x24a4 0x27f5 0x2901 0x29be 0x2955 0x2490 0x27ed 0x28f5 0x29a1 0x298b 0x2480 0x28a1 0x28f2 0x29a5 0x2971 0x2467 0x2bb2 0x28fb 0x29a5 0x2959 0x2459 0x3356 0x2908 0x2981 0x2975 0x2458 0x34f7 0x28ec 0x297c 0x2975 0x244d 0x2ee8 0x28e0 0x2974 0x2998 0x243f 0x2e57 0x28e2 0x299e 0x29fb 0x2432 0x2f53 0x293b 0x29d0 0x2965 0x241c 0x2ed8 0x295e 0x2997 0x28f9 0x2403 0x299d 0x2952 0x2957 0x28c8 0x23dc 0x2839 0x2964 0x2922 0x288e 0x23c2 0x26dd 0x291c 0x28e7 0x284d 0x23c2 0x26dd 0x291c 0x28e7 0x284d 0x23c2 0x26dd 0x291c 0x28e7 0x284d>;
|
|
};
|
|
|
|
qcom,pc-temp-z3-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x4baf 0x4ba3 0x4baf 0x4b92 0x4b94 0x4bc2 0x4baf 0x4bd4 0x4bb7 0x4bb2 0x4c0c 0x4c2c 0x4bff 0x4bd7 0x4bc0 0x4ca7 0x4c6d 0x4c14 0x4beb 0x4ba1 0x4cf4 0x4c7c 0x4c1e 0x4bf0 0x4b94 0x4cca 0x4c84 0x4c21 0x4bdc 0x4ba1 0x4c99 0x4c87 0x4c23 0x4bbb 0x4bac 0x4cce 0x4c87 0x4c22 0x4bb7 0x4baa 0x4d66 0x4c87 0x4c20 0x4bbd 0x4ba4 0x4d96 0x4c84 0x4c1d 0x4bbe 0x4b9f 0x4d87 0x4c7b 0x4c16 0x4bb8 0x4b9e 0x4d72 0x4c71 0x4c0f 0x4bb1 0x4b9d 0x4d63 0x4c69 0x4c0c 0x4bae 0x4b9d 0x4d58 0x4c64 0x4c09 0x4bae 0x4b9c 0x4d34 0x4c6b 0x4c07 0x4bae 0x4b9a 0x4c91 0x4c8f 0x4c07 0x4bac 0x4b96 0x4c25 0x4ca7 0x4c07 0x4baa 0x4b92 0x4c93 0x4cae 0x4c04 0x4ba9 0x4b8f 0x4d1c 0x4cb2 0x4c00 0x4ba8 0x4b8e 0x4d11 0x4cad 0x4c01 0x4ba7 0x4b8e 0x4d05 0x4ca6 0x4c0b 0x4baa 0x4b90 0x4cf4 0x4ca8 0x4c11 0x4bad 0x4b95 0x4c77 0x4cbc 0x4c06 0x4bb1 0x4ba0 0x4c33 0x4cc7 0x4bf7 0x4bb7 0x4baf 0x4cba 0x4cc6 0x4bf9 0x4bbd 0x4bb4 0x4d75 0x4cc4 0x4c08 0x4bca 0x4bb4 0x4db1 0x4cbf 0x4c13 0x4bd3 0x4bb4 0x4dac 0x4cb9 0x4c18 0x4bd0 0x4bb0 0x4da8 0x4cb7 0x4c1b 0x4bcb 0x4bab 0x4da1 0x4cb6 0x4c19 0x4bc6 0x4ba8 0x4d97 0x4cb6 0x4c13 0x4bc1 0x4ba5 0x4d8e 0x4cb4 0x4c0f 0x4bbc 0x4ba2 0x4d83 0x4cb2 0x4c0c 0x4bb9 0x4b9e 0x4d28 0x4cb0 0x4c09 0x4bb5 0x4b9b 0x4c8c 0x4caf 0x4c06 0x4bb3 0x4b98 0x4c69 0x4cad 0x4c03 0x4bb2 0x4b95 0x4cda 0x4caa 0x4c01 0x4bb1 0x4b94 0x4d3d 0x4ca3 0x4bff 0x4bb1 0x4b93 0x4cfd 0x4c9c 0x4bfd 0x4bb1 0x4b92 0x4c04 0x4c95 0x4bf9 0x4bb0 0x4b93 0x4b52 0x4c8e 0x4bf3 0x4bad 0x4b95 0x4b49 0x4c8a 0x4bf0 0x4baa 0x4b97 0x4b4a 0x4c85 0x4bee 0x4ba7 0x4b9a 0x4b4a 0x4bb7 0x4bea 0x4ba6 0x4b98 0x4b4b 0x4b3a 0x4be0 0x4ba3 0x4b91 0x4b4c 0x4b39 0x4bcb 0x4b90 0x4b84 0x4b4c 0x4b39 0x4bb7 0x4b90 0x4b83 0x4b4d 0x4b3a 0x4ba1 0x4b91 0x4b7c 0x4b4e 0x4b3a 0x4ba6 0x4b8e 0x4b77 0x4b4f 0x4b3a 0x4ba1 0x4b93 0x4b8d 0x4b51 0x4b3a 0x4b96 0x4b97 0x4b93 0x4b54 0x4b3b 0x4b92 0x4b9d 0x4b95 0x4b5b 0x4b3c 0x4b88 0x4ba0 0x4b97 0x4b60 0x4b3e 0x4b82 0x4ba2 0x4b9c 0x4b60 0x4b3e 0x4b82 0x4ba2 0x4b9c 0x4b60 0x4b3e 0x4b82 0x4ba2 0x4b9c>;
|
|
};
|
|
|
|
qcom,pc-temp-z4-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x3d0e 0x3ba9 0x3ac3 0x3a70 0x3a61 0x3d49 0x3c16 0x3ad9 0x3a73 0x3a71 0x3d6b 0x3bf2 0x3b35 0x3aac 0x3a7d 0x3d26 0x3b99 0x3ae8 0x3a99 0x3a1d 0x3d05 0x3b32 0x3a8c 0x3a53 0x39c8 0x3d7f 0x3acf 0x3a4f 0x3a0a 0x39a7 0x3ded 0x3a85 0x3a19 0x39c4 0x3991 0x3d8c 0x3a4a 0x39ed 0x39a0 0x3982 0x3cb2 0x3a1c 0x39c8 0x398d 0x397b 0x3c2c 0x39fc 0x39b1 0x3981 0x3975 0x3bec 0x39e3 0x39a7 0x397c 0x396e 0x3bbd 0x39cf 0x39a0 0x3979 0x3966 0x3b92 0x39bf 0x399a 0x3974 0x395e 0x3b6e 0x39b5 0x3994 0x396d 0x3958 0x3b7b 0x39b6 0x3993 0x3967 0x3954 0x3c09 0x39d1 0x3995 0x3964 0x3951 0x3c6c 0x39e4 0x3998 0x3962 0x394f 0x3c01 0x39ee 0x3992 0x3960 0x394e 0x3b61 0x39f0 0x3987 0x395d 0x394b 0x3b42 0x39df 0x3990 0x3962 0x3953 0x3b2f 0x39c5 0x39df 0x399e 0x3981 0x3b17 0x39d4 0x3a1d 0x39d6 0x39ac 0x3b73 0x3a25 0x3a2c 0x39d9 0x39ab 0x3bae 0x3a5a 0x3a34 0x39d2 0x399f 0x3b24 0x3a5c 0x3a28 0x39c7 0x3994 0x3a5d 0x3a57 0x39fd 0x39aa 0x3987 0x3a20 0x3a49 0x39dc 0x3991 0x397a 0x3a28 0x3a2e 0x39ca 0x3986 0x3972 0x3a2b 0x3a17 0x39be 0x3980 0x396c 0x3a2b 0x3a09 0x39bc 0x397c 0x3967 0x3a28 0x39fc 0x39bb 0x397b 0x3963 0x3a24 0x39f2 0x39bb 0x397a 0x3961 0x3a1f 0x39e9 0x39bd 0x397a 0x3960 0x3a69 0x39e2 0x39bf 0x397a 0x395f 0x3af7 0x39dd 0x39bf 0x397e 0x3964 0x3b0e 0x39d7 0x39be 0x3987 0x3970 0x3a82 0x39d1 0x39be 0x398b 0x3975 0x3a05 0x39cb 0x39bc 0x398c 0x3977 0x3a36 0x39c5 0x39ba 0x398d 0x3977 0x3b24 0x39c1 0x39b3 0x3989 0x3974 0x3bd3 0x39bc 0x39a9 0x3982 0x396f 0x3bd2 0x39b1 0x39a0 0x397d 0x396d 0x3bbb 0x39a6 0x3996 0x3978 0x396b 0x3b9b 0x3a56 0x398a 0x3972 0x3967 0x3b34 0x3aa5 0x3970 0x3965 0x395d 0x3ae6 0x3a65 0x394a 0x3945 0x393e 0x3ae3 0x3a61 0x3953 0x3937 0x3933 0x3adf 0x3a5e 0x3961 0x392a 0x392a 0x3ad7 0x3a57 0x3959 0x392b 0x392b 0x3ac9 0x3a4f 0x3966 0x3937 0x392d 0x3ad1 0x3a5a 0x3978 0x3939 0x3930 0x3adf 0x3a5e 0x397e 0x3936 0x3931 0x3aec 0x3a65 0x398b 0x3934 0x3930 0x3b01 0x3a6e 0x3996 0x3935 0x392e 0x3b01 0x3a6e 0x3996 0x3935 0x392e 0x3b01 0x3a6e 0x3996 0x3935 0x392e>;
|
|
};
|
|
|
|
qcom,pc-temp-z5-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x2f5c 0x2f28 0x3365 0x3376 0x3526 0x32c2 0x32c8 0x39d4 0x3aed 0x3b32 0x3513 0x38f7 0x3daf 0x400c 0x41e6 0x3632 0x3e5c 0x4184 0x4217 0x3db9 0x363c 0x422b 0x45af 0x43db 0x3ea9 0x33e8 0x45b9 0x497b 0x438a 0x4648 0x31d0 0x49c9 0x4d5e 0x433b 0x4e53 0x3363 0x4f1c 0x522b 0x4625 0x4f71 0x3783 0x54a6 0x584a 0x4d96 0x4e0c 0x3983 0x57cd 0x5c5e 0x51c7 0x4d15 0x3990 0x59a9 0x5e88 0x50c5 0x4e4a 0x3939 0x5a38 0x5ff8 0x4e1a 0x5188 0x3981 0x5b5a 0x609d 0x4d97 0x5520 0x39ec 0x5d84 0x61ff 0x50c8 0x5863 0x3938 0x62a8 0x6400 0x541a 0x59c3 0x3447 0x65e3 0x69a0 0x554b 0x5828 0x3114 0x6367 0x6e1c 0x562e 0x55a4 0x3872 0x617a 0x6d4e 0x57ef 0x55b1 0x41b9 0x6340 0x6b66 0x5abf 0x580e 0x415c 0x649d 0x6def 0x5b85 0x582f 0x3faf 0x668a 0x821e 0x584d 0x5258 0x3d5f 0x7091 0x8fab 0x54b5 0x4da7 0x36a9 0x8f59 0x7934 0x5016 0x4bb4 0x402d 0xa14b 0x5862 0x47ad 0x49ce 0x5b04 0x9906 0x549b 0x463e 0x4a30 0x730e 0x89ee 0x594a 0x5095 0x4ec5 0x7c7b 0x7f98 0x5f92 0x5ba2 0x532f 0x7e46 0x77ba 0x6b12 0x62a4 0x565f 0x7e60 0x7538 0x777a 0x688f 0x59ec 0x7bd2 0x77f9 0x7e84 0x6da1 0x5ef9 0x7785 0x7c19 0x83b3 0x71ef 0x65df 0x73c9 0x7f67 0x8856 0x7615 0x6bed 0x6f9a 0x8339 0x8d45 0x7b42 0x7252 0x624e 0x876c 0x9001 0x7ed5 0x762b 0x4ed8 0x8cb6 0x9000 0x7ec6 0x733c 0x4a17 0x9083 0x8fb2 0x7e07 0x6dd5 0x54e9 0x90a3 0x8eba 0x7d01 0x6ae1 0x5e35 0x8ff9 0x8b49 0x7b1a 0x6564 0x569f 0x8ec2 0x8759 0x7871 0x614a 0x3d53 0x8a9d 0x83ae 0x746c 0x6235 0x2bea 0x85be 0x7fdf 0x6f14 0x63ea 0x2ae9 0x834b 0x7b9d 0x68d2 0x65f0 0x2ae8 0x8052 0x77bb 0x6233 0x6965 0x2af6 0x4a8f 0x77f1 0x627e 0x63df 0x2b89 0x2beb 0x7779 0x61f5 0x5bcd 0x2bf9 0x2bf7 0x721b 0x5b64 0x5b3b 0x2bd0 0x2bd6 0x5648 0x680e 0x6664 0x2bd1 0x2bcb 0x41ff 0x76d0 0x6508 0x2bd7 0x2bdd 0x460d 0x6ff2 0x5893 0x2bfc 0x2c3b 0x42dd 0x5f51 0x6f7a 0x2c04 0x2c2d 0x3cb0 0x5b2f 0x6e4b 0x2bb2 0x2c0c 0x3a28 0x60f1 0x6841 0x2b6d 0x2bee 0x3680 0x60fa 0x67bd 0x2b41 0x2bb2 0x3454 0x5ea6 0x69c4 0x2b41 0x2bb2 0x3454 0x5ea6 0x69c4 0x2b41 0x2bb2 0x3454 0x5ea6 0x69c4>;
|
|
};
|
|
|
|
qcom,pc-temp-z6-lut {
|
|
qcom,lut-col-legend = <0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
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|
qcom,lut-data = <0x3e90 0x3c29 0x3ab4 0x3a16 0x3a00 0x3e7c 0x3c46 0x3ab8 0x3a1a 0x3a09 0x3e8d 0x3c44 0x3ae3 0x3a36 0x39fd 0x3ea1 0x3c2a 0x3abd 0x3a31 0x3981 0x3ed6 0x3bf0 0x3a8f 0x3a0f 0x393b 0x3fe9 0x3baa 0x3a6c 0x39c5 0x3934 0x40e9 0x3b77 0x3a4b 0x396d 0x392d 0x40c6 0x3b4d 0x3a30 0x3956 0x3925 0x407d 0x3b2a 0x3a17 0x394f 0x391e 0x4035 0x3b0c 0x3a06 0x3949 0x3918 0x3feb 0x3af3 0x39fb 0x3942 0x3913 0x3fa5 0x3adc 0x39f4 0x393c 0x390f 0x3f67 0x3ac8 0x39ee 0x3938 0x390b 0x3f2d 0x3ab9 0x39ea 0x3935 0x3908 0x3ef2 0x3abf 0x39e7 0x3932 0x3904 0x3eb7 0x3b00 0x39e5 0x392f 0x3901 0x3e8d 0x3b3e 0x39e3 0x392c 0x38fe 0x3e73 0x3b66 0x39df 0x392b 0x38fc 0x3e58 0x3b7f 0x39da 0x3929 0x38fb 0x3e37 0x3b7a 0x39df 0x392c 0x38fe 0x3e12 0x3b6f 0x3a08 0x3947 0x3913 0x3df0 0x3b78 0x3a26 0x3962 0x3928 0x3dd7 0x3ba8 0x3a28 0x3966 0x392f 0x3dcf 0x3bc6 0x3a26 0x3967 0x3932 0x3dd9 0x3bc8 0x3a22 0x3967 0x3932 0x3de7 0x3bc6 0x3a1a 0x3962 0x392d 0x3df0 0x3bc0 0x3a14 0x395c 0x3927 0x3df7 0x3bb4 0x3a10 0x3957 0x3921 0x3dfa 0x3bac 0x3a0e 0x3953 0x391d 0x3dfa 0x3ba8 0x3a0d 0x394f 0x3919 0x3df9 0x3ba5 0x3a0b 0x394c 0x3917 0x3df6 0x3ba3 0x3a0b 0x394a 0x3915 0x3df3 0x3ba1 0x3a0c 0x3949 0x3912 0x3dec 0x3ba1 0x3a0d 0x3948 0x3911 0x3de4 0x3ba4 0x3a0f 0x394a 0x3912 0x3de2 0x3ba7 0x3a11 0x394e 0x3916 0x3de8 0x3ba8 0x3a12 0x3951 0x3919 0x3ded 0x3ba8 0x3a14 0x3953 0x391a 0x3deb 0x3ba8 0x3a15 0x3954 0x391a 0x3de4 0x3bab 0x3a13 0x3953 0x391a 0x3ddf 0x3baf 0x3a10 0x3950 0x3919 0x3de2 0x3bb2 0x3a0f 0x394d 0x391a 0x3de6 0x3bb4 0x3a0e 0x394b 0x391c 0x3de5 0x3baa 0x3a0c 0x394a 0x391a 0x3dd1 0x3b95 0x3a03 0x3945 0x3913 0x3dba 0x3b8a 0x39ee 0x392e 0x3900 0x3dba 0x3b8b 0x39e9 0x3929 0x38fa 0x3dbc 0x3b8e 0x39e7 0x3925 0x38f3 0x3dc1 0x3b93 0x39ea 0x3925 0x38f2 0x3dc9 0x3b99 0x39f2 0x392e 0x38ff 0x3dd7 0x3ba8 0x39fa 0x3934 0x3906 0x3deb 0x3bb7 0x3a00 0x3938 0x3908 0x3e03 0x3bca 0x3a09 0x393c 0x390b 0x3e26 0x3be4 0x3a15 0x3941 0x3910 0x3e26 0x3be4 0x3a15 0x3941 0x3910 0x3e26 0x3be4 0x3a15 0x3941 0x3910>;
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|
};
|
|
|
|
qcom,pc-temp-y1-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
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|
qcom,lut-data = <0x1d2d 0x1a68 0x179a 0x1579 0x149a 0x144e 0x1d1f 0x1a33 0x1797 0x1577 0x149f 0x144e 0x1d16 0x1a12 0x1794 0x1575 0x14a2 0x144e 0x1d11 0x1a01 0x1791 0x1574 0x14a3 0x144c 0x1d0f 0x19fb 0x178e 0x1574 0x14a2 0x144a 0x1d0e 0x19fa 0x178d 0x1574 0x14a1 0x1447 0x1d0b 0x1a0f 0x178d 0x1572 0x149e 0x1444 0x1d21 0x1a26 0x178f 0x1570 0x149a 0x1440 0x1d45 0x1a23 0x1790 0x1570 0x1497 0x143e 0x1d63 0x1a11 0x1794 0x1571 0x1495 0x143b 0x1d6e 0x1a0b 0x1797 0x1571 0x1492 0x143a 0x1d6d 0x1a0e 0x179a 0x156e 0x148e 0x1438 0x1d55 0x1a12 0x179b 0x156c 0x148c 0x1437 0x1d26 0x1a11 0x1799 0x1570 0x148b 0x1436 0x1d06 0x1a0c 0x179b 0x1578 0x148a 0x1435 0x1d05 0x1a0e 0x179f 0x1579 0x1489 0x1435 0x1d10 0x1a1e 0x179e 0x1576 0x1487 0x1434 0x1d1b 0x1a29 0x179d 0x1573 0x1486 0x1434 0x1d25 0x1a21 0x17a3 0x1572 0x1486 0x1433 0x1d2e 0x1a20 0x17b0 0x1571 0x1486 0x1433 0x1d2b 0x1a35 0x17b9 0x1572 0x1486 0x1434 0x1d1d 0x1a52 0x17ba 0x1575 0x1488 0x1435 0x1d17 0x1a51 0x17b5 0x1576 0x1489 0x1436 0x1d2a 0x1a32 0x17a9 0x1575 0x148a 0x1436 0x1d40 0x1a1c 0x179d 0x1574 0x148b 0x1437 0x1d40 0x1a21 0x179d 0x1579 0x148c 0x1438 0x1d37 0x1a30 0x17a5 0x1580 0x148d 0x143b 0x1d39 0x1a32 0x17b1 0x1583 0x148f 0x143c 0x1d38 0x1a22 0x17b3 0x1581 0x1492 0x143c 0x1d32 0x1a16 0x17b4 0x1580 0x1495 0x143d 0x1d2e 0x1a1d 0x17b7 0x1582 0x1497 0x143f 0x1d33 0x1a2c 0x17b4 0x1586 0x1498 0x1442 0x1d3f 0x1a2d 0x17aa 0x1586 0x149a 0x1444 0x1d52 0x1a25 0x17a6 0x1587 0x149e 0x1446 0x1d51 0x1a20 0x17a5 0x158a 0x14a2 0x1449 0x1d37 0x1a29 0x17a6 0x1595 0x14a7 0x144c 0x1d25 0x1a35 0x17aa 0x159e 0x14aa 0x144e 0x1d32 0x1a32 0x17b1 0x159c 0x14aa 0x1451 0x1d55 0x1a24 0x17b7 0x1595 0x14a9 0x1454 0x1d6f 0x1a17 0x17b4 0x1593 0x14aa 0x1456 0x1d85 0x1a0e 0x17a4 0x159a 0x14ae 0x1457 0x1d8a 0x1a0b 0x17a5 0x159a 0x14b3 0x145a 0x1d4c 0x1a0c 0x17ac 0x1592 0x14b8 0x145f 0x1d21 0x1a30 0x17b8 0x159a 0x14bb 0x1460 0x1d1c 0x1a38 0x17b8 0x159b 0x14b9 0x1463 0x1d20 0x1a23 0x17a9 0x159a 0x14bd 0x1466 0x1d21 0x1a3b 0x17b6 0x15a4 0x14bf 0x1466 0x1d27 0x1a49 0x17b9 0x159f 0x14be 0x1469 0x1d5e 0x1a49 0x17bf 0x15a3 0x14cc 0x1465 0x1d9e 0x1a26 0x17c6 0x15ac 0x14c6 0x1466 0x1d9c 0x1a2c 0x17ae 0x15bf 0x14c4 0x146c 0x1df6 0x1a53 0x17b7 0x15c3 0x14cd 0x1472 0x1df9 0x1a50 0x17c7 0x15bf 0x14d9 0x1479 0x1e43 0x1a96 0x17db 0x15c4 0x14db 0x147d 0x1e43 0x1a96 0x17db 0x15c4 0x14db 0x147d 0x1e43 0x1a96 0x17db 0x15c4 0x14db 0x147d>;
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|
};
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|
|
qcom,pc-temp-y2-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
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|
qcom,lut-data = <0x25b6 0x25c6 0x2937 0x2b02 0x2b88 0x2b7c 0x25b6 0x25c0 0x294c 0x2afb 0x2b72 0x2b69 0x25b6 0x25c2 0x2964 0x2aea 0x2b5c 0x2b53 0x25b7 0x25ca 0x297a 0x2ad5 0x2b48 0x2b3b 0x25b7 0x25d5 0x298a 0x2ac3 0x2b36 0x2b22 0x25b7 0x25e4 0x298f 0x2aba 0x2b2a 0x2b06 0x25b7 0x2662 0x298b 0x2aa6 0x2b22 0x2ae3 0x25b7 0x26ea 0x2985 0x2a91 0x2b1a 0x2ac7 0x25b8 0x26c1 0x2981 0x2a8e 0x2afe 0x2abd 0x25b8 0x26b4 0x297c 0x2a89 0x2acf 0x2ab8 0x25b7 0x2724 0x2979 0x2a88 0x2abe 0x2ab9 0x25b7 0x27aa 0x298d 0x2a88 0x2abe 0x2abe 0x25b8 0x2790 0x29b1 0x2a89 0x2ac0 0x2ac2 0x25b7 0x26d6 0x29e1 0x2a87 0x2acc 0x2ac6 0x25b7 0x2615 0x2a20 0x2a86 0x2ae5 0x2ac9 0x25b7 0x25ea 0x2a3b 0x2a94 0x2afe 0x2ac4 0x25b7 0x25e9 0x2a47 0x2ac7 0x2b1d 0x2ab2 0x25b7 0x25e4 0x2a4c 0x2af8 0x2b3b 0x2ab2 0x25b7 0x25dc 0x2a3d 0x2b21 0x2b69 0x2b0f 0x25b7 0x25d5 0x2a27 0x2b3e 0x2b8c 0x2b6e 0x25b7 0x25d0 0x2a26 0x2b3a 0x2b85 0x2b77 0x25b7 0x25cc 0x2a37 0x2b27 0x2b72 0x2b79 0x25b7 0x25ca 0x2a48 0x2b1f 0x2b77 0x2b83 0x25b6 0x25ca 0x2a1c 0x2b2f 0x2b97 0x2ba3 0x25b6 0x25c9 0x2916 0x2b3e 0x2bb4 0x2bb5 0x25b6 0x25c7 0x286d 0x2b48 0x2bc2 0x2bac 0x25b6 0x25c5 0x28c8 0x2b5d 0x2bc6 0x2ba7 0x25b6 0x25c2 0x293c 0x2b62 0x2bcf 0x2bb5 0x25b6 0x25c1 0x28c9 0x2b65 0x2bf4 0x2bc6 0x25b6 0x25bf 0x2839 0x2b66 0x2c14 0x2be2 0x25b6 0x25bd 0x2803 0x2b6a 0x2c1c 0x2c2d 0x25b6 0x25bc 0x27e3 0x2b6d 0x2c24 0x2c66 0x25b6 0x25bb 0x27ba 0x2b5e 0x2c39 0x2c64 0x25b6 0x25b9 0x2775 0x2b34 0x2c58 0x2c49 0x25b6 0x25b8 0x26fc 0x2b24 0x2c5f 0x2c32 0x25b6 0x25b8 0x2695 0x2b47 0x2c48 0x2c19 0x25b6 0x25b7 0x265d 0x2b69 0x2c2a 0x2c10 0x25b6 0x25b6 0x262e 0x2b5a 0x2c19 0x2c1b 0x25b6 0x25b6 0x25ff 0x2b2b 0x2c0c 0x2c24 0x25b6 0x25b6 0x25e3 0x2b02 0x2c0c 0x2c26 0x25b6 0x25b6 0x25d6 0x2ad9 0x2c4d 0x2c2e 0x25b6 0x25b5 0x25d0 0x2aad 0x2c7c 0x2c2c 0x25b6 0x25b5 0x25ca 0x2a79 0x2c65 0x2c2f 0x25b6 0x25b5 0x25c4 0x2a24 0x2c17 0x2c48 0x25b5 0x25b5 0x25c1 0x29d0 0x2c09 0x2c45 0x25b5 0x25b5 0x25bf 0x29ec 0x2c1f 0x2be4 0x25b5 0x25b5 0x25be 0x2a2b 0x2c27 0x2b9c 0x25b5 0x25b5 0x25bd 0x2a2d 0x2be0 0x2b92 0x25b5 0x25b5 0x25bc 0x2a10 0x2bcd 0x2b9d 0x25b4 0x25b5 0x25bb 0x29f5 0x2bce 0x2b61 0x25b3 0x25b5 0x25ba 0x29a5 0x2b97 0x2b33 0x25b2 0x25b4 0x25b9 0x2978 0x2b50 0x2afb 0x25b2 0x25b3 0x25b8 0x2946 0x2ae6 0x2a98 0x25b0 0x25b2 0x25b7 0x2917 0x2a77 0x2a13 0x25b0 0x25b2 0x25b7 0x2917 0x2a77 0x2a13 0x25b0 0x25b2 0x25b7 0x2917 0x2a77 0x2a13>;
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|
};
|
|
|
|
qcom,pc-temp-y3-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
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|
qcom,lut-data = <0x3a2e 0x356b 0x344b 0x33fb 0x33e8 0x33e2 0x39a9 0x3567 0x344e 0x33fc 0x33e6 0x33e0 0x3914 0x355c 0x3451 0x33fd 0x33e4 0x33df 0x3882 0x354d 0x3454 0x33fe 0x33e3 0x33de 0x3803 0x353c 0x3457 0x33ff 0x33e2 0x33de 0x37ab 0x352a 0x345a 0x3400 0x33e2 0x33de 0x3783 0x3518 0x345c 0x3401 0x33e3 0x33de 0x3774 0x3500 0x345e 0x3401 0x33e4 0x33df 0x3763 0x34e5 0x3460 0x3402 0x33e4 0x33df 0x3731 0x34c8 0x3463 0x3403 0x33e3 0x33e0 0x36f9 0x34bc 0x3464 0x3404 0x33e3 0x33e0 0x36e9 0x34be 0x3464 0x3404 0x33e5 0x33e1 0x36ef 0x34c1 0x3464 0x3405 0x33e7 0x33e1 0x36d0 0x34c3 0x3462 0x3405 0x33e8 0x33e0 0x3695 0x34c1 0x345c 0x3406 0x33ea 0x33e0 0x3685 0x34c0 0x3454 0x3406 0x33ea 0x33e0 0x3685 0x34c0 0x344d 0x3407 0x33eb 0x33e2 0x3687 0x34b8 0x3445 0x3407 0x33eb 0x33e4 0x368a 0x34a7 0x343c 0x3406 0x33ed 0x33e7 0x368f 0x3490 0x3432 0x3403 0x33ef 0x33e8 0x369e 0x3475 0x342b 0x33ff 0x33ec 0x33e5 0x36be 0x345b 0x3426 0x33f9 0x33e5 0x33df 0x36e2 0x344b 0x3422 0x33f5 0x33e3 0x33dd 0x370f 0x3442 0x341c 0x33f2 0x33e2 0x33dd 0x3741 0x3442 0x3412 0x33f1 0x33e2 0x33dd 0x3771 0x344e 0x3406 0x33f0 0x33e1 0x33dc 0x37a3 0x3463 0x33fa 0x33f0 0x33df 0x33dc 0x37d7 0x347b 0x33ed 0x33f0 0x33df 0x33dc 0x3811 0x3496 0x33d9 0x33f0 0x33df 0x33dc 0x384d 0x34b6 0x33cc 0x33ef 0x33e0 0x33dc 0x388a 0x34dd 0x33cc 0x33ef 0x33e0 0x33db 0x38c9 0x350c 0x33cd 0x33ee 0x33e1 0x33db 0x390a 0x3542 0x33cd 0x33ee 0x33e1 0x33dc 0x394e 0x357f 0x33cd 0x33ed 0x33e2 0x33dc 0x3990 0x35c7 0x33d0 0x33ed 0x33e2 0x33dc 0x39cf 0x361b 0x33e2 0x33ee 0x33e0 0x33dc 0x3a0e 0x3679 0x3400 0x33ee 0x33df 0x33db 0x3a4e 0x36e0 0x3413 0x33eb 0x33df 0x33db 0x3a8e 0x3752 0x3417 0x33e4 0x33df 0x33db 0x3acd 0x37c9 0x3418 0x33e3 0x33de 0x33db 0x3b0b 0x3846 0x341f 0x33ea 0x33de 0x33db 0x3b4c 0x38c3 0x3431 0x33ed 0x33de 0x33db 0x3b8f 0x393c 0x3453 0x33ee 0x33dd 0x33db 0x3bdd 0x39a8 0x3486 0x33f0 0x33dd 0x33da 0x3c0c 0x39d9 0x34b1 0x33f0 0x33de 0x33db 0x3cb8 0x3a4b 0x34d5 0x33f7 0x33e0 0x33dd 0x3d2b 0x3a7d 0x34fb 0x33fd 0x33e1 0x33e0 0x3daa 0x3a96 0x3531 0x3403 0x33e6 0x33e3 0x3e6e 0x3a90 0x3562 0x3407 0x33e8 0x33e3 0x3fd5 0x3acd 0x3582 0x340b 0x33e6 0x33e1 0x419c 0x3b1c 0x35c1 0x340c 0x33e7 0x33e1 0x442b 0x3b9f 0x3628 0x3413 0x33e9 0x33e3 0x47c1 0x3d7c 0x36a9 0x341f 0x33eb 0x33e5 0x4c7e 0x40c4 0x3772 0x3430 0x33f0 0x33e8 0x4c7e 0x40c4 0x3772 0x3430 0x33f0 0x33e8 0x4c7e 0x40c4 0x3772 0x3430 0x33f0 0x33e8>;
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|
};
|
|
|
|
qcom,pc-temp-y4-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x4365 0x42ed 0x4167 0x40c1 0x4060 0x404c 0x43ea 0x434f 0x4198 0x40cb 0x4063 0x404d 0x44a0 0x43ab 0x41dd 0x40d4 0x4066 0x404d 0x4560 0x43fb 0x4224 0x40da 0x4068 0x404d 0x4600 0x4438 0x425d 0x40df 0x4069 0x404d 0x4657 0x445b 0x4274 0x40e0 0x4069 0x404d 0x4659 0x445e 0x4274 0x40de 0x4068 0x404d 0x4644 0x445c 0x4272 0x40da 0x4067 0x404e 0x464f 0x4487 0x426e 0x40d8 0x4068 0x404f 0x4679 0x4510 0x4264 0x40d7 0x406b 0x4051 0x462f 0x4594 0x425d 0x40d7 0x406e 0x4053 0x45b4 0x45b0 0x4282 0x40d9 0x4071 0x4055 0x4548 0x453c 0x42bd 0x40df 0x4074 0x4058 0x44c2 0x4483 0x42e8 0x40ea 0x4079 0x405f 0x441c 0x43bb 0x430e 0x40fb 0x407f 0x4067 0x43a8 0x4391 0x42ff 0x410c 0x4088 0x406f 0x435c 0x4395 0x42d6 0x411c 0x4096 0x4077 0x4327 0x4364 0x42a8 0x4131 0x40a9 0x4083 0x42e4 0x42ff 0x426c 0x4161 0x40cf 0x409e 0x42a5 0x4290 0x4209 0x418c 0x40ee 0x40b4 0x4281 0x423b 0x41aa 0x4165 0x40d4 0x40a1 0x4268 0x41fa 0x415e 0x40e4 0x408a 0x406e 0x4259 0x41cd 0x412c 0x40a4 0x4067 0x4057 0x4252 0x41b1 0x4119 0x4093 0x405c 0x404e 0x4251 0x41a3 0x4117 0x408a 0x4057 0x404c 0x4257 0x419e 0x4116 0x4087 0x4058 0x404c 0x425f 0x419a 0x4112 0x4086 0x405a 0x404d 0x4269 0x4198 0x4116 0x4086 0x405d 0x4050 0x4272 0x419a 0x412e 0x4089 0x4061 0x4054 0x427c 0x419f 0x413d 0x408d 0x4066 0x4059 0x4283 0x41a8 0x413c 0x4091 0x406f 0x4061 0x4289 0x41b3 0x413f 0x4094 0x407b 0x406a 0x428f 0x41bf 0x4147 0x4094 0x4089 0x4076 0x4296 0x41cc 0x4151 0x4090 0x4098 0x4081 0x429e 0x41d8 0x4155 0x408b 0x4098 0x407f 0x42a8 0x41ea 0x414c 0x407b 0x4076 0x4063 0x42af 0x41fc 0x413d 0x406d 0x4056 0x404f 0x42b1 0x4200 0x413c 0x406e 0x404c 0x404c 0x42b2 0x41ff 0x414e 0x4071 0x4047 0x404a 0x42b6 0x4202 0x4164 0x4075 0x4048 0x404a 0x42be 0x420b 0x4174 0x407d 0x404d 0x404c 0x42cc 0x4214 0x417e 0x4088 0x404d 0x4049 0x42e7 0x421f 0x4189 0x4095 0x4050 0x404a 0x42ff 0x4231 0x4194 0x4097 0x4043 0x4038 0x4313 0x4248 0x41b6 0x4097 0x4045 0x403c 0x437d 0x4294 0x41d8 0x40c0 0x405b 0x4050 0x43bd 0x42cd 0x421a 0x40e2 0x406a 0x4063 0x4402 0x42e9 0x4239 0x410b 0x4082 0x4086 0x444e 0x42d3 0x4277 0x4134 0x4098 0x4087 0x44c5 0x42dc 0x427f 0x4133 0x4077 0x4058 0x4559 0x42cd 0x4286 0x411d 0x406f 0x405b 0x464e 0x42c4 0x42a7 0x4142 0x4082 0x406e 0x480c 0x438c 0x42ec 0x4188 0x40aa 0x4098 0x4c11 0x45cc 0x43af 0x4207 0x4120 0x4148 0x4c11 0x45cc 0x43af 0x4207 0x4120 0x4148 0x4c11 0x45cc 0x43af 0x4207 0x4120 0x4148>;
|
|
};
|
|
|
|
qcom,pc-temp-y5-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x2a9f 0x283a 0x3785 0x413d 0x455b 0x523c 0x2a92 0x2933 0x386d 0x417e 0x4399 0x4bf3 0x2ac5 0x2aab 0x394b 0x418d 0x4098 0x46e4 0x2b16 0x2c60 0x3a19 0x4176 0x3d59 0x4303 0x2b61 0x2e0e 0x3ad4 0x4144 0x3ada 0x4043 0x2b84 0x2f7c 0x3b79 0x40fe 0x3a14 0x3ea8 0x2ca3 0x314e 0x3c25 0x405c 0x3a4e 0x3e90 0x31e2 0x3246 0x3ca1 0x3fc0 0x3a8b 0x3edc 0x3641 0x30d0 0x3ca6 0x3f8b 0x398a 0x3e0b 0x3550 0x305e 0x3c72 0x3f40 0x3743 0x3c97 0x3217 0x32f3 0x3bf7 0x3ec3 0x36d5 0x3c18 0x3426 0x36af 0x396f 0x3d97 0x381e 0x3b44 0x3821 0x37f2 0x3704 0x3c0e 0x391b 0x3a14 0x360b 0x3557 0x3776 0x39e1 0x3932 0x37ce 0x3063 0x3397 0x3961 0x379d 0x3905 0x357a 0x2e56 0x34ce 0x3b36 0x370c 0x3860 0x3561 0x2e43 0x36bd 0x3d02 0x3708 0x372d 0x3641 0x2e60 0x36ed 0x3ea0 0x3743 0x36cd 0x3750 0x2db1 0x359c 0x3fa2 0x38e7 0x37e3 0x38ad 0x2ce8 0x3430 0x406b 0x3bb6 0x399a 0x3a2d 0x2c20 0x324a 0x40f5 0x3f5d 0x3c3e 0x3bd8 0x2b0a 0x2f7d 0x412d 0x440e 0x4002 0x3e04 0x2aa3 0x2cf5 0x4115 0x4566 0x4210 0x3fea 0x2ab9 0x2b2f 0x3fec 0x435d 0x4382 0x438e 0x2ac5 0x2a6e 0x3b15 0x4194 0x444a 0x4528 0x2ab0 0x2a6f 0x373b 0x419c 0x4297 0x4463 0x2a8d 0x2a8c 0x3578 0x41cf 0x3f81 0x4321 0x2a6e 0x2adc 0x332f 0x420a 0x3e58 0x41db 0x2a5e 0x2b29 0x2e55 0x423b 0x3ea3 0x4007 0x2a6f 0x2b4d 0x2b4d 0x424a 0x3f75 0x3ea0 0x2aa8 0x2b94 0x2b56 0x4240 0x406e 0x3dc5 0x2afa 0x2be6 0x2b39 0x4259 0x41a7 0x3d75 0x2b46 0x2bec 0x2aff 0x42f2 0x43ea 0x3e52 0x2b7b 0x2bd5 0x2ad0 0x4434 0x470c 0x4066 0x2b7d 0x2c0a 0x2b0f 0x456f 0x4804 0x42bb 0x2b59 0x2cc3 0x2c9f 0x47f7 0x47f7 0x4543 0x2b3d 0x2d55 0x2e86 0x4a15 0x47f7 0x4723 0x2b34 0x2d62 0x2f27 0x4491 0x4ab2 0x48f6 0x2b2f 0x2d54 0x2f07 0x37f4 0x4d7f 0x4aa1 0x2b1d 0x2d53 0x2eca 0x354b 0x4a4c 0x4a55 0x2afa 0x2d5c 0x2e8f 0x3aad 0x45a2 0x47d3 0x2adb 0x2d4f 0x2e2f 0x3b81 0x4646 0x45e7 0x2adc 0x2cc9 0x2de1 0x3940 0x4082 0x4574 0x2b96 0x2ca4 0x2e64 0x3a3f 0x471e 0x4d24 0x2bcc 0x2cea 0x2eb7 0x3946 0x4608 0x4793 0x2c69 0x2d12 0x2e4c 0x3abb 0x4065 0x40ad 0x2d33 0x2d6b 0x2f39 0x3af5 0x3bd2 0x41b3 0x2d69 0x2e7e 0x316d 0x3b25 0x405c 0x3ff6 0x2d3b 0x30e7 0x33ef 0x3a00 0x402f 0x3f77 0x2c74 0x314a 0x33d8 0x3d8f 0x4374 0x45cf 0x2b14 0x3068 0x338a 0x3e76 0x4875 0x45b1 0x2905 0x2eca 0x3397 0x3dab 0x4873 0x4895 0x2764 0x2c1a 0x32b6 0x3e0c 0x46c1 0x478d 0x262f 0x2999 0x322d 0x3ebe 0x4672 0x478c 0x262f 0x2999 0x322d 0x3ebe 0x4672 0x478c 0x262f 0x2999 0x322d 0x3ebe 0x4672 0x478c>;
|
|
};
|
|
|
|
qcom,pc-temp-y6-lut {
|
|
qcom,lut-col-legend = <0xfffffff6 0x00 0x0a 0x19 0x28 0x32>;
|
|
qcom,lut-row-legend = <0x2710 0x2648 0x2580 0x24b8 0x23f0 0x2328 0x2260 0x2198 0x20d0 0x2008 0x1f40 0x1e78 0x1db0 0x1ce8 0x1c20 0x1b58 0x1a90 0x19c8 0x1900 0x1838 0x1770 0x16a8 0x15e0 0x1518 0x1450 0x1388 0x12c0 0x11f8 0x1130 0x1068 0xfa0 0xed8 0xe10 0xd48 0xc80 0xbb8 0xaf0 0xa28 0x960 0x898 0x7d0 0x708 0x640 0x578 0x4b0 0x3e8 0x384 0x320 0x2bc 0x258 0x1f4 0x190 0x12c 0xc8 0x64 0x00>;
|
|
qcom,lut-data = <0x1d55 0x1871 0x15b0 0x142a 0x13b6 0x139e 0x1d27 0x186e 0x15b7 0x142a 0x13b6 0x139d 0x1cf5 0x1867 0x15be 0x142b 0x13b5 0x139c 0x1cc3 0x185d 0x15c2 0x142b 0x13b4 0x139b 0x1c95 0x1851 0x15c4 0x142a 0x13b4 0x139a 0x1c6e 0x1846 0x15c4 0x142a 0x13b3 0x139a 0x1c4b 0x1839 0x15be 0x1428 0x13b3 0x139a 0x1c36 0x1829 0x15b4 0x1425 0x13b2 0x139b 0x1c38 0x1819 0x15ac 0x1423 0x13b2 0x139b 0x1c21 0x181d 0x15a3 0x1421 0x13b2 0x139c 0x1be3 0x1834 0x159c 0x1420 0x13b2 0x139c 0x1baf 0x1841 0x15a0 0x1420 0x13b4 0x139d 0x1b90 0x1822 0x15ab 0x1420 0x13b6 0x139e 0x1b57 0x17e3 0x15b2 0x1422 0x13b8 0x13a0 0x1b05 0x17a0 0x15b4 0x1426 0x13ba 0x13a1 0x1ad9 0x1792 0x15aa 0x142b 0x13bd 0x13a4 0x1ac3 0x1794 0x1599 0x142f 0x13c1 0x13a7 0x1aba 0x1782 0x1586 0x1435 0x13c7 0x13ac 0x1aa9 0x175f 0x156d 0x1441 0x13d3 0x13b5 0x1a9b 0x1738 0x154a 0x144b 0x13dd 0x13bd 0x1aa2 0x171a 0x152b 0x143e 0x13d3 0x13b5 0x1ab8 0x1706 0x1513 0x1415 0x13b9 0x13a2 0x1ad2 0x1701 0x1504 0x1400 0x13ad 0x139a 0x1af4 0x1703 0x14fa 0x13f9 0x13a9 0x1397 0x1b1b 0x1709 0x14f1 0x13f6 0x13a8 0x1396 0x1b41 0x171a 0x14ed 0x13f6 0x13a8 0x1396 0x1b67 0x1736 0x14ec 0x13f6 0x13a8 0x1397 0x1b8f 0x1754 0x14ea 0x13f6 0x13a8 0x1397 0x1bba 0x1776 0x14e9 0x13f8 0x13aa 0x1398 0x1be6 0x179e 0x14eb 0x13fa 0x13ac 0x139a 0x1c15 0x17cb 0x14f2 0x13fd 0x13af 0x139c 0x1c46 0x17fe 0x14fc 0x13ff 0x13b3 0x139f 0x1c77 0x1835 0x1508 0x1400 0x13b8 0x13a3 0x1ca9 0x1872 0x1516 0x1400 0x13be 0x13a7 0x1cd9 0x18b5 0x1528 0x1400 0x13be 0x13a6 0x1d08 0x18ff 0x153f 0x13ff 0x13b4 0x139e 0x1d37 0x194f 0x155a 0x13fd 0x13aa 0x1399 0x1d65 0x19a0 0x1579 0x13fd 0x13a8 0x1398 0x1d95 0x19f5 0x159f 0x13fd 0x13a7 0x1398 0x1dc6 0x1a4e 0x15ca 0x13ff 0x13a7 0x1398 0x1df7 0x1aad 0x15fb 0x140a 0x13a9 0x1399 0x1e2d 0x1b0b 0x1631 0x1416 0x13aa 0x1398 0x1e66 0x1b66 0x166f 0x141f 0x13ab 0x1399 0x1ea5 0x1bba 0x16b7 0x1428 0x13a8 0x1394 0x1ed3 0x1be7 0x16f4 0x142c 0x13ab 0x1396 0x1f70 0x1c53 0x1726 0x1446 0x13b3 0x139e 0x1fd8 0x1c8a 0x175f 0x145a 0x13b8 0x13a5 0x2050 0x1ca5 0x1796 0x1471 0x13c4 0x13b2 0x2109 0x1c9f 0x17d4 0x1486 0x13cb 0x13b2 0x225d 0x1cce 0x17f7 0x148e 0x13c1 0x13a3 0x2405 0x1d06 0x1838 0x148f 0x13c0 0x13a4 0x2668 0x1d69 0x18a3 0x14ae 0x13c9 0x13ac 0x29da 0x1f3a 0x1927 0x14db 0x13d7 0x13bb 0x2e6a 0x228d 0x19fd 0x151c 0x13fe 0x13f1 0x2e6a 0x228d 0x19fd 0x151c 0x13fe 0x13f1 0x2e6a 0x228d 0x19fd 0x151c 0x13fe 0x13f1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
12c@13 {
|
|
status = "ok";
|
|
cell-index = <0x0d>;
|
|
compatible = "i2c-gpio";
|
|
gpios = <0x16c 0x2a 0x00 0x16c 0x2b 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3a9>;
|
|
phandle = <0x5a0>;
|
|
|
|
qcom,smb1390@10 {
|
|
compatible = "qcom,i2c-pmic";
|
|
reg = <0x10>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupt-parent = <0x2dc>;
|
|
interrupts = <0x00 0xc2 0x00 0x08>;
|
|
interrupt_names = "smb1390";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
qcom,periph-map = <0x10>;
|
|
status = "disabled";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x4f7>;
|
|
phandle = <0x4f9>;
|
|
|
|
qcom,revid {
|
|
compatible = "qcom,qpnp-revid";
|
|
reg = <0x100>;
|
|
phandle = <0x4f8>;
|
|
};
|
|
|
|
qcom,charge_pump {
|
|
compatible = "qcom,smb1390-charger-psy";
|
|
qcom,pmic-revid = <0x4f8>;
|
|
interrupt-parent = <0x4f9>;
|
|
status = "disabled";
|
|
io-channels = <0xa1 0x0e>;
|
|
io-channel-names = "cp_die_temp";
|
|
phandle = <0x5a1>;
|
|
|
|
qcom,core {
|
|
interrupts = <0x10 0x00 0x03 0x10 0x01 0x03 0x10 0x02 0x03 0x10 0x03 0x03 0x10 0x04 0x03 0x10 0x05 0x01 0x10 0x06 0x01 0x10 0x07 0x01>;
|
|
interrupt-names = "switcher-off-window\0switcher-off-fault\0tsd-fault\0irev-fault\0vph-ov-hard\0vph-ov-soft\0ilim\0temp-alarm";
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,smb1390_slave@18 {
|
|
compatible = "qcom,i2c-pmic";
|
|
reg = <0x18>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
qcom,periph-map = <0x10>;
|
|
status = "disabled";
|
|
phandle = <0x5a2>;
|
|
|
|
qcom,charge_pump_slave {
|
|
compatible = "qcom,smb1390-slave";
|
|
status = "disabled";
|
|
phandle = <0x5a3>;
|
|
};
|
|
};
|
|
|
|
s2mu106@3D {
|
|
status = "okay";
|
|
compatible = "samsung,s2mu106mfd";
|
|
reg = <0x3d>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x4fa>;
|
|
s2mu106,irq-gpio = <0x16c 0x44 0x00>;
|
|
s2mu106,wakeup;
|
|
};
|
|
|
|
s2mu107-fuelgauge@3B {
|
|
compatible = "samsung,s2mu107-fuelgauge";
|
|
reg = <0x3b>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x551>;
|
|
fuelgauge,charger_name = "s2mu107-switching-charger";
|
|
fuelgauge,fuel_int = <0x16c 0x68 0x00>;
|
|
fuelgauge,fuel_alert_soc = <0x01>;
|
|
fuelgauge,fuel_alert_vol = <0xce4>;
|
|
fuelgauge,low_temp_limit = <0x64>;
|
|
fuelgauge,sw_vbat_l_recovery_vol = <0xd89>;
|
|
fuelgauge,capacity_max = <0x3de>;
|
|
fuelgauge,capacity_max_margin = <0xc8>;
|
|
fuelgauge,capacity_min = <0x00>;
|
|
fuelgauge,capacity_calculation_type = <0x1c>;
|
|
fuelgauge,capacity_full = <0xbb8>;
|
|
fuelgauge,type_str = "SDI";
|
|
fuelgauge,fg_log_enable = <0x01>;
|
|
fuelgauge,low_vbat_threshold_lowtemp = <0xbb8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flash_led {
|
|
reg = <0x74>;
|
|
compatible = "qcom,s2mu106-fled";
|
|
enable = <0x01 0x01>;
|
|
flash-gpio = <0x16c 0x16 0x00>;
|
|
torch-gpio = <0x16c 0x18 0x00>;
|
|
pinctrl-names = "fled_default\0fled_suspend";
|
|
pinctrl-0 = <0x552 0x553>;
|
|
pinctrl-1 = <0x554 0x555>;
|
|
flash_current = <0x578>;
|
|
preflash_current = <0xc8>;
|
|
torch_current = <0x12c>;
|
|
movie_current = <0xc8>;
|
|
factory_current = <0x12c>;
|
|
flashlight_current = <0x19 0x4b 0x64 0x96 0xc8>;
|
|
status = "okay";
|
|
};
|
|
|
|
pca9468@57 {
|
|
compatible = "nxp,pca9468";
|
|
reg = <0x57>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x58a>;
|
|
pca9468,irq-gpio = <0x16c 0x39 0x01>;
|
|
pca9468,input-current-limit = <0x273710>;
|
|
pca9468,charging-current = <0x5b8d80>;
|
|
pca9468,input-itopoff = <0x7a120>;
|
|
pca9468,sense-resistance = <0x00>;
|
|
pca9468,switching-frequency = <0x03>;
|
|
pca9468,ntc-threshold = <0x00>;
|
|
pca9468,chg_gpio_en = <0x16c 0x37 0x00>;
|
|
pca9468,ta-mode = <0x01>;
|
|
};
|
|
};
|
|
|
|
gpio_keys {
|
|
compatible = "gpio-keys";
|
|
label = "gpio-keys";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x4fb>;
|
|
status = "ok";
|
|
input-name = "gpio-keys";
|
|
|
|
vol_up {
|
|
label = "volume_up";
|
|
gpios = <0x2e4 0x02 0x01>;
|
|
linux,input-type = <0x01>;
|
|
linux,code = <0x73>;
|
|
linux,can-disable;
|
|
debounce-interval = <0x0f>;
|
|
gpio-key,wakeup;
|
|
};
|
|
};
|
|
|
|
lpi_pinctrl@62b40000 {
|
|
compatible = "qcom,lpi-pinctrl";
|
|
reg = <0x62b40000 0x00>;
|
|
qcom,num-gpios = <0x20>;
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000 0x1c000 0x1d000 0x1e000 0x1f000>;
|
|
clock-names = "lpass_core_hw_vote";
|
|
clocks = <0x4b4 0x00>;
|
|
phandle = <0x513>;
|
|
|
|
lpi_wcd934x_reset_active {
|
|
phandle = <0x526>;
|
|
|
|
mux {
|
|
pins = "gpio29";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio29";
|
|
drive-strength = <0x10>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
lpi_wcd934x_reset_sleep {
|
|
phandle = <0x527>;
|
|
|
|
mux {
|
|
pins = "gpio29";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio29";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
lpi_wcd937x_reset_active {
|
|
phandle = <0x528>;
|
|
|
|
mux {
|
|
pins = "gpio24";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio24";
|
|
drive-strength = <0x10>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
lpi_wcd937x_reset_sleep {
|
|
phandle = <0x529>;
|
|
|
|
mux {
|
|
pins = "gpio24";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio24";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
dmic01_clk_active {
|
|
phandle = <0x514>;
|
|
|
|
mux {
|
|
pins = "gpio26";
|
|
function = "func1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio26";
|
|
drive-strength = <0x08>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
dmic01_clk_sleep {
|
|
phandle = <0x516>;
|
|
|
|
mux {
|
|
pins = "gpio26";
|
|
function = "func1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio26";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
dmic01_data_active {
|
|
phandle = <0x515>;
|
|
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "func1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
drive-strength = <0x08>;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
dmic01_data_sleep {
|
|
phandle = <0x517>;
|
|
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "func1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
drive-strength = <0x02>;
|
|
pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
dmic23_clk_active {
|
|
phandle = <0x518>;
|
|
|
|
mux {
|
|
pins = "gpio28";
|
|
function = "func1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28";
|
|
drive-strength = <0x08>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
dmic23_clk_sleep {
|
|
phandle = <0x51a>;
|
|
|
|
mux {
|
|
pins = "gpio28";
|
|
function = "func1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
dmic23_data_active {
|
|
phandle = <0x519>;
|
|
|
|
mux {
|
|
pins = "gpio29";
|
|
function = "func1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio29";
|
|
drive-strength = <0x08>;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
dmic23_data_sleep {
|
|
phandle = <0x51b>;
|
|
|
|
mux {
|
|
pins = "gpio29";
|
|
function = "func1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio29";
|
|
drive-strength = <0x02>;
|
|
pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tx_swr_clk_sleep {
|
|
phandle = <0x523>;
|
|
|
|
mux {
|
|
pins = "gpio18";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio18";
|
|
drive-strength = <0x02>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
tx_swr_clk_active {
|
|
phandle = <0x520>;
|
|
|
|
mux {
|
|
pins = "gpio18";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio18";
|
|
drive-strength = <0x08>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
tx_swr_data1_sleep {
|
|
phandle = <0x524>;
|
|
|
|
mux {
|
|
pins = "gpio19";
|
|
function = "func3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19";
|
|
drive-strength = <0x02>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
tx_swr_data1_active {
|
|
phandle = <0x521>;
|
|
|
|
mux {
|
|
pins = "gpio19";
|
|
function = "func3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19";
|
|
drive-strength = <0x08>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
tx_swr_data2_sleep {
|
|
phandle = <0x525>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x02>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
tx_swr_data2_active {
|
|
phandle = <0x522>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x08>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
rx_swr_clk_sleep {
|
|
phandle = <0x51e>;
|
|
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
drive-strength = <0x02>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
rx_swr_clk_active {
|
|
phandle = <0x51c>;
|
|
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
drive-strength = <0x08>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
rx_swr_data_sleep {
|
|
phandle = <0x51f>;
|
|
|
|
mux {
|
|
pins = "gpio22\0gpio23";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22\0gpio23";
|
|
drive-strength = <0x02>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
rx_swr_data_active {
|
|
phandle = <0x51d>;
|
|
|
|
mux {
|
|
pins = "gpio22\0gpio23";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22\0gpio23";
|
|
drive-strength = <0x08>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
sec_mi2s_clk_active {
|
|
phandle = <0x538>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "func3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x08>;
|
|
};
|
|
};
|
|
|
|
sec_mi2s_clk_sleep {
|
|
phandle = <0x53c>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "func3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sec_mi2s_ws_active {
|
|
phandle = <0x539>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "func3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x08>;
|
|
};
|
|
};
|
|
|
|
sec_mi2s_ws_sleep {
|
|
phandle = <0x53d>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "func3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sec_mi2s_sd0_active {
|
|
phandle = <0x53a>;
|
|
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "func4";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <0x08>;
|
|
};
|
|
};
|
|
|
|
sec_mi2s_sd0_sleep {
|
|
phandle = <0x53e>;
|
|
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "func4";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sec_mi2s_sd1_active {
|
|
phandle = <0x53b>;
|
|
|
|
mux {
|
|
pins = "gpio11";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11";
|
|
drive-strength = <0x08>;
|
|
};
|
|
};
|
|
|
|
sec_mi2s_sd1_sleep {
|
|
phandle = <0x53f>;
|
|
|
|
mux {
|
|
pins = "gpio11";
|
|
function = "func2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cdc_dmic01_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active\0aud_sleep";
|
|
pinctrl-0 = <0x514 0x515>;
|
|
pinctrl-1 = <0x516 0x517>;
|
|
qcom,lpi-gpios;
|
|
phandle = <0x50c>;
|
|
};
|
|
|
|
cdc_dmic23_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active\0aud_sleep";
|
|
pinctrl-0 = <0x518 0x519>;
|
|
pinctrl-1 = <0x51a 0x51b>;
|
|
qcom,lpi-gpios;
|
|
phandle = <0x50d>;
|
|
};
|
|
|
|
wsa_swr_clk_data_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active\0aud_sleep";
|
|
pinctrl-0 = <0x3c1 0x3c3>;
|
|
pinctrl-1 = <0x3c0 0x3c2>;
|
|
status = "disabled";
|
|
phandle = <0x504>;
|
|
};
|
|
|
|
rx_swr_clk_data_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active\0aud_sleep";
|
|
pinctrl-0 = <0x51c 0x51d>;
|
|
pinctrl-1 = <0x51e 0x51f>;
|
|
qcom,lpi-gpios;
|
|
phandle = <0x501>;
|
|
};
|
|
|
|
tx_swr_clk_data_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active\0aud_sleep";
|
|
pinctrl-0 = <0x520 0x521 0x522>;
|
|
pinctrl-1 = <0x523 0x524 0x525>;
|
|
qcom,lpi-gpios;
|
|
phandle = <0x4fe>;
|
|
};
|
|
|
|
wsa_spkr_en1_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active\0aud_sleep";
|
|
pinctrl-0 = <0x3c5>;
|
|
pinctrl-1 = <0x3c4>;
|
|
status = "disabled";
|
|
phandle = <0x505>;
|
|
};
|
|
|
|
wsa_spkr_en2_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active\0aud_sleep";
|
|
pinctrl-0 = <0x3c7>;
|
|
pinctrl-1 = <0x3c6>;
|
|
status = "disabled";
|
|
phandle = <0x506>;
|
|
};
|
|
|
|
wcd9xxx-irq {
|
|
status = "disabled";
|
|
compatible = "qcom,wcd9xxx-irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-parent = <0x16c>;
|
|
qcom,gpio-connect = <0x16c 0x7a 0x00>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3c8>;
|
|
phandle = <0x52c>;
|
|
};
|
|
|
|
msm_cdc_pinctrl@29 {
|
|
status = "disabled";
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active\0aud_sleep";
|
|
pinctrl-0 = <0x526>;
|
|
pinctrl-1 = <0x527>;
|
|
qcom,lpi-gpios;
|
|
phandle = <0x52d>;
|
|
};
|
|
|
|
msm_cdc_pinctrl@24 {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active\0aud_sleep";
|
|
pinctrl-0 = <0x528>;
|
|
pinctrl-1 = <0x529>;
|
|
qcom,lpi-gpios;
|
|
phandle = <0x508>;
|
|
};
|
|
|
|
qcom,wcd-dsp-glink {
|
|
status = "disabled";
|
|
compatible = "qcom,wcd-dsp-glink";
|
|
qcom,wdsp-channels = "g_glink_ctrl\0g_glink_persistent_data_nild\0g_glink_persistent_data_ild\0g_glink_audio_data";
|
|
phandle = <0x5ab>;
|
|
};
|
|
|
|
wcd-dsp-mgr@2 {
|
|
status = "disabled";
|
|
compatible = "qcom,wcd-dsp-mgr";
|
|
qcom,wdsp-components = <0x52a 0x00 0x52b 0x01 0x2cf 0x02>;
|
|
qcom,img-filename = "cpe_9340";
|
|
phandle = <0x5ac>;
|
|
};
|
|
|
|
wsa_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <0x03>;
|
|
qcom,codec-lpass-ext-clk-freq = <0x124f800>;
|
|
qcom,codec-lpass-clk-id = <0x309>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x502>;
|
|
};
|
|
|
|
wsa_npl_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <0x04>;
|
|
qcom,codec-lpass-ext-clk-freq = <0x124f800>;
|
|
qcom,codec-lpass-clk-id = <0x30a>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x503>;
|
|
};
|
|
|
|
va_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <0x02>;
|
|
qcom,codec-lpass-ext-clk-freq = <0x124f800>;
|
|
qcom,codec-lpass-clk-id = <0x30b>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x507>;
|
|
};
|
|
|
|
rx_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <0x05>;
|
|
qcom,codec-lpass-ext-clk-freq = <0x1588800>;
|
|
qcom,codec-lpass-clk-id = <0x30e>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x4ff>;
|
|
};
|
|
|
|
rx_npl_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <0x06>;
|
|
qcom,codec-lpass-ext-clk-freq = <0x1588800>;
|
|
qcom,codec-lpass-clk-id = <0x30f>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x500>;
|
|
};
|
|
|
|
tx_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <0x07>;
|
|
qcom,codec-lpass-ext-clk-freq = <0x124f800>;
|
|
qcom,codec-lpass-clk-id = <0x30c>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x4fc>;
|
|
};
|
|
|
|
tx_npl_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <0x08>;
|
|
qcom,codec-lpass-ext-clk-freq = <0x124f800>;
|
|
qcom,codec-lpass-clk-id = <0x30d>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x4fd>;
|
|
};
|
|
|
|
audio_ext_clk {
|
|
status = "disabled";
|
|
qcom,codec-ext-clk-src = <0x00>;
|
|
compatible = "qcom,audio-ref-clk";
|
|
pinctrl-names = "active\0sleep";
|
|
pinctrl-0 = <0x2e1>;
|
|
pinctrl-1 = <0x2e1>;
|
|
qcom,use-pinctrl = <0x01>;
|
|
qcom,audio-ref-clk-gpio = <0x2df 0x08 0x00>;
|
|
clock-names = "osr_clk";
|
|
clocks = <0x9f>;
|
|
qcom,node_has_rpm_clock;
|
|
pmic-clock-names = "pm6150_div_clk1";
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x52e>;
|
|
};
|
|
|
|
dbu1 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "dbu1";
|
|
startup-delay-us = <0x00>;
|
|
enable-active-high;
|
|
phandle = <0x52f>;
|
|
};
|
|
|
|
input_booster {
|
|
status = "okay";
|
|
compatible = "input_booster";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
booster_key@1 {
|
|
input_booster,label = "KEY";
|
|
input_booster,type = <0x00>;
|
|
input_booster,levels = <0x01>;
|
|
input_booster,cpu_freqs = <0x143700>;
|
|
input_booster,core_num = <0x00>;
|
|
input_booster,hmp_boost = <0x02>;
|
|
input_booster,bimc_freqs = <0x00>;
|
|
input_booster,lpm_bias = <0x00>;
|
|
input_booster,head_times = <0xc8>;
|
|
input_booster,tail_times = <0x00>;
|
|
};
|
|
|
|
booster_key@2 {
|
|
input_booster,label = "TOUCHKEY";
|
|
input_booster,type = <0x01>;
|
|
input_booster,levels = <0x01>;
|
|
input_booster,cpu_freqs = <0x143700>;
|
|
input_booster,core_num = <0x00>;
|
|
input_booster,hmp_boost = <0x02>;
|
|
input_booster,bimc_freqs = <0x00>;
|
|
input_booster,lpm_bias = <0x00>;
|
|
input_booster,head_times = <0x00>;
|
|
input_booster,tail_times = <0x12c>;
|
|
};
|
|
|
|
booster_key@3 {
|
|
input_booster,label = "TOUCH";
|
|
input_booster,type = <0x02>;
|
|
input_booster,levels = <0x01 0x02 0x03>;
|
|
input_booster,cpu_freqs = <0x143700 0x143700 0x127500>;
|
|
input_booster,core_num = <0x04 0x04 0x00>;
|
|
input_booster,hmp_boost = <0x02 0x02 0x02>;
|
|
input_booster,bimc_freqs = <0x00 0x00 0x00>;
|
|
input_booster,lpm_bias = <0x05 0x05 0x05>;
|
|
input_booster,head_times = <0xc8 0xc8 0x00>;
|
|
input_booster,tail_times = <0x00 0x00 0x12c>;
|
|
};
|
|
|
|
booster_key@4 {
|
|
input_booster,label = "MULTITOUCH";
|
|
input_booster,type = <0x03>;
|
|
input_booster,levels = <0x01 0x02>;
|
|
input_booster,cpu_freqs = <0x143700 0x00>;
|
|
input_booster,core_num = <0x00 0x00>;
|
|
input_booster,hmp_boost = <0x02 0x00>;
|
|
input_booster,bimc_freqs = <0x00 0x00>;
|
|
input_booster,lpm_bias = <0x00 0x00>;
|
|
input_booster,head_times = <0x3e8 0x00>;
|
|
input_booster,tail_times = <0x00 0x1f4>;
|
|
};
|
|
|
|
booster_key@5 {
|
|
input_booster,label = "KEYBOARD";
|
|
input_booster,type = <0x04>;
|
|
input_booster,levels = <0x01 0x02>;
|
|
input_booster,cpu_freqs = <0x143700 0x143700>;
|
|
input_booster,core_num = <0x00 0x00>;
|
|
input_booster,hmp_boost = <0x02 0x02>;
|
|
input_booster,bimc_freqs = <0x00 0x00>;
|
|
input_booster,lpm_bias = <0x00 0x00>;
|
|
input_booster,head_times = <0x82 0x82>;
|
|
input_booster,tail_times = <0x00 0x00>;
|
|
};
|
|
|
|
booster_key@6 {
|
|
input_booster,label = "MOUSE";
|
|
input_booster,type = <0x05>;
|
|
input_booster,levels = <0x01 0x02>;
|
|
input_booster,cpu_freqs = <0x143700 0x127500>;
|
|
input_booster,core_num = <0x00 0x00>;
|
|
input_booster,hmp_boost = <0x02 0x02>;
|
|
input_booster,bimc_freqs = <0x00 0x00>;
|
|
input_booster,lpm_bias = <0x00 0x00>;
|
|
input_booster,head_times = <0xc8 0x00>;
|
|
input_booster,tail_times = <0x00 0x12c>;
|
|
};
|
|
|
|
booster_key@7 {
|
|
input_booster,label = "MOUSE WHEEL";
|
|
input_booster,type = <0x06>;
|
|
input_booster,levels = <0x01 0x02>;
|
|
input_booster,cpu_freqs = <0x143700 0x00>;
|
|
input_booster,core_num = <0x00 0x00>;
|
|
input_booster,hmp_boost = <0x02 0x00>;
|
|
input_booster,bimc_freqs = <0x00 0x00>;
|
|
input_booster,lpm_bias = <0x00 0x00>;
|
|
input_booster,head_times = <0xc8 0x00>;
|
|
input_booster,tail_times = <0x00 0x00>;
|
|
};
|
|
|
|
booster_key@8 {
|
|
input_booster,label = "PEN HOVER";
|
|
input_booster,type = <0x07>;
|
|
input_booster,levels = <0x01 0x02>;
|
|
input_booster,cpu_freqs = <0x143700 0x127500>;
|
|
input_booster,core_num = <0x00 0x00>;
|
|
input_booster,hmp_boost = <0x02 0x02>;
|
|
input_booster,bimc_freqs = <0x00 0x00>;
|
|
input_booster,lpm_bias = <0x00 0x00>;
|
|
input_booster,head_times = <0xc8 0x00>;
|
|
input_booster,tail_times = <0x00 0x12c>;
|
|
};
|
|
|
|
booster_key@9 {
|
|
input_booster,label = "PEN";
|
|
input_booster,type = <0x08>;
|
|
input_booster,levels = <0x01 0x02>;
|
|
input_booster,cpu_freqs = <0x17bb00 0xef100>;
|
|
input_booster,hmp_boost = <0x02 0x02>;
|
|
input_booster,ddr_freqs = <0x00 0x00>;
|
|
input_booster,lpm_bias = <0x00 0x00>;
|
|
input_booster,head_times = <0xc8 0x00>;
|
|
input_booster,tail_times = <0x00 0x258>;
|
|
};
|
|
|
|
booster_key@10 {
|
|
input_booster,label = "KEY_TWO";
|
|
input_booster,type = <0x09>;
|
|
input_booster,levels = <0x01>;
|
|
input_booster,cpu_freqs = <0x17bb00>;
|
|
input_booster,hmp_boost = <0x02>;
|
|
input_booster,ddr_freqs = <0x00>;
|
|
input_booster,lpm_bias = <0x00>;
|
|
input_booster,head_times = <0x2bc>;
|
|
input_booster,tail_times = <0x2bc>;
|
|
};
|
|
};
|
|
|
|
sec_smem@0 {
|
|
compatible = "samsung,sec-smem";
|
|
status = "okay";
|
|
};
|
|
|
|
argos {
|
|
compatible = "samsung,argos";
|
|
#address-cells = <0x01>;
|
|
|
|
boot_device@1 {
|
|
net_boost,label = "WIFI";
|
|
net_boost,node = "wlan0";
|
|
net_boost,table_size = <0x03>;
|
|
net_boost,table = <0x96 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xc8 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x12c 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01>;
|
|
};
|
|
|
|
boot_device@2 {
|
|
net_boost,label = "WIFI TX";
|
|
net_boost,node = "wlan0";
|
|
net_boost,table_size = <0x05>;
|
|
net_boost,table = <0x14 0x15ae00 0x00 0x15ae00 0x00 0x00 0x00 0x00 0x00 0x00 0x3c 0x1a5e00 0x00 0x1a5e00 0x00 0x00 0x00 0x00 0x00 0x00 0x64 0x1de200 0x00 0x1de200 0x00 0x00 0x00 0x00 0x00 0x00 0x96 0x21b100 0x00 0x21b100 0x00 0x00 0x00 0x01 0x01 0x01 0x12c 0x286e00 0x00 0x286e00 0x00 0x00 0x00 0x01 0x01 0x01>;
|
|
};
|
|
|
|
boot_device@3 {
|
|
net_boost,label = "WIFI RX";
|
|
net_boost,node = "wlan0";
|
|
net_boost,table_size = <0x04>;
|
|
net_boost,table = <0x3c 0x122a00 0x00 0x122a00 0x00 0x00 0x00 0x00 0x00 0x00 0x64 0x135600 0x00 0x135600 0x00 0x00 0x00 0x00 0x00 0x00 0xc8 0x1a5e00 0x00 0x1a5e00 0x00 0x00 0x00 0x01 0x01 0x01 0x12c 0x1f0e00 0x00 0x1f0e00 0x00 0x00 0x00 0x01 0x01 0x01>;
|
|
};
|
|
|
|
boot_device@4 {
|
|
net_boost,label = "SWLAN";
|
|
net_boost,node = "swlan0";
|
|
net_boost,table_size = <0x04>;
|
|
net_boost,table = <0x02 0x189c00 0x00 0x189c00 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x1c2000 0x00 0x1c2000 0x00 0x00 0x00 0x00 0x00 0x00 0x14 0x1fef00 0x00 0x1fef00 0x00 0x00 0x00 0x01 0x01 0x01 0x32 0x224700 0x00 0x224700 0x00 0x00 0x00 0x01 0x01 0x01>;
|
|
};
|
|
|
|
boot_device@5 {
|
|
net_boost,label = "UFS";
|
|
net_boost,node = [00];
|
|
net_boost,sysnode = "/sys/class/scsi_host/host0/transferred_cnt";
|
|
net_boost,table_size = <0x03>;
|
|
net_boost,table = <0x70 0x00 0x00 0x8a480 0x00 0x00 0x00 0x00 0x00 0x00 0x320 0x00 0x00 0xd7a00 0x00 0x00 0x00 0x00 0x00 0x00 0xc80 0x00 0x00 0x1fef00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
};
|
|
|
|
boot_device@6 {
|
|
net_boost,label = "P2P";
|
|
net_boost,node = "p2p-wlan0-0";
|
|
net_boost,table_size = <0x03>;
|
|
net_boost,table = <0x1e 0x15ae00 0x00 0x15ae00 0x00 0x00 0x00 0x00 0x00 0x00 0x5a 0x1de200 0x00 0x1de200 0x00 0x00 0x00 0x00 0x00 0x00 0x12c 0x21b100 0x00 0x21b100 0x00 0x00 0x00 0x01 0x01 0x01>;
|
|
};
|
|
|
|
boot_device@7 {
|
|
net_boost,label = "IPC";
|
|
net_boost,node = "rmnet_ipa0";
|
|
net_boost,table_size = <0x05>;
|
|
net_boost,table = <0x0a 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x3c 0x143700 0x00 0x143700 0x00 0x00 0x00 0x00 0x00 0x00 0x64 0x17bb00 0x00 0x17bb00 0x00 0x00 0x00 0x00 0x00 0x00 0xc8 0x1a1300 0x00 0x1a1300 0x00 0x00 0x00 0x01 0x01 0x01 0x12c 0x1d9700 0x00 0x1d9700 0x00 0x00 0x00 0x01 0x01 0x01>;
|
|
};
|
|
};
|
|
|
|
det_zones {
|
|
#list-det-cells = <0x02>;
|
|
phandle = <0x532>;
|
|
};
|
|
|
|
samsung,q6audio-adaptation {
|
|
compatible = "samsung,q6audio-adaptation";
|
|
adaptation,voice-tracking-tx-port-id = <0xb037>;
|
|
adaptation,amp-rx-port-id = <0x1002>;
|
|
adaptation,amp-rx-topology = <0x1000fc01>;
|
|
adaptation,amp-tx-topology = <0x1000fd01>;
|
|
phandle = <0x531>;
|
|
};
|
|
|
|
msm_cdc_pinctrl_sec {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active\0aud_sleep";
|
|
pinctrl-0 = <0x538 0x539 0x53a 0x53b>;
|
|
pinctrl-1 = <0x53c 0x53d 0x53e 0x53f>;
|
|
phandle = <0x533>;
|
|
};
|
|
|
|
ss_touch {
|
|
compatible = "samsung,ss_touch";
|
|
ss_touch,numbers = <0x01>;
|
|
};
|
|
|
|
tsp_ldo_en {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "tsp_ldo_en";
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
gpio = <0x16c 0x38 0x00>;
|
|
enable-active-high;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
tsp_ldo_avdd {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "tsp_ldo_avdd";
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
gpio = <0x16c 0x38 0x00>;
|
|
enable-active-high;
|
|
};
|
|
|
|
sec-mst {
|
|
compatible = "sec-mst";
|
|
sec-mst,mst-pwr-gpio = <0x16c 0x05 0x00>;
|
|
sec-mst,mst-data-gpio = <0x16c 0x53 0x00>;
|
|
sec-mst,mst-en-gpio = <0x16c 0x54 0x00>;
|
|
sec-mst,mst-support-gpio = <0x2e4 0x04 0x00>;
|
|
};
|
|
|
|
i2c@17 {
|
|
status = "ok";
|
|
cell-index = <0x11>;
|
|
compatible = "i2c-gpio";
|
|
gpios = <0x16c 0x19 0x00 0x16c 0x1a 0x00>;
|
|
#i2c-gpio,delay-us = <0x02>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x544>;
|
|
pinctrl-1 = <0x545>;
|
|
phandle = <0x5b9>;
|
|
|
|
a96t3x6@21 {
|
|
compatible = "a96t3x6";
|
|
reg = <0x21>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x546>;
|
|
pinctrl-1 = <0x547>;
|
|
interrupt-parent = <0x2dc>;
|
|
interrupts = <0x04 0xc4 0x00 0x02>;
|
|
a96t3x6,irq_gpio = <0x2e4 0x05 0x01>;
|
|
a96t3x6,dvdd_vreg_name = "pm6150l_l11";
|
|
a96t3x6,fw_path = "abov/a96t356_a71.bin";
|
|
a96t3x6,firmup_cmd = <0x3b>;
|
|
};
|
|
|
|
a96t3x6_sub@20 {
|
|
compatible = "a96t3x6_sub";
|
|
reg = <0x20>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x548>;
|
|
pinctrl-1 = <0x549>;
|
|
interrupt-parent = <0x2dc>;
|
|
interrupts = <0x04 0xc4 0x00 0x02>;
|
|
a96t3x6,irq_gpio = <0x2e4 0x06 0x01>;
|
|
a96t3x6,dvdd_vreg_name = "pm6150_l16";
|
|
a96t3x6,fw_path = "abov/a96t356_a71_sub.bin";
|
|
a96t3x6,firmup_cmd = <0x3b>;
|
|
};
|
|
};
|
|
|
|
ssc_core {
|
|
status = "okay";
|
|
compatible = "ssc_core";
|
|
ssc_core,mst_gpio = <0x2e4 0x04 0x00>;
|
|
};
|
|
|
|
sec_detect_conn {
|
|
compatible = "samsung,sec_detect_conn";
|
|
sec,det_pm_conn_gpios = <0x2df 0x08 0x00>;
|
|
sec,det_pm_conn_name = "SUB_CONNECT";
|
|
pinctrl-names = "det_pm_connect";
|
|
pinctrl-0 = <0x54a>;
|
|
};
|
|
|
|
sec_abc {
|
|
compatible = "samsung,sec_abc";
|
|
status = "okay";
|
|
|
|
gpu {
|
|
gpu,label = "GPU fault";
|
|
gpu,threshold_count = <0x14>;
|
|
gpu,threshold_time = <0x4b0>;
|
|
};
|
|
|
|
aicl {
|
|
aicl,label = "battery aicl";
|
|
aicl,threshold_count = <0x05>;
|
|
aicl,threshold_time = <0x12c>;
|
|
};
|
|
};
|
|
|
|
abc_hub {
|
|
compatible = "samsung,abc_hub";
|
|
status = "okay";
|
|
pinctrl-names = "det_pm_connect";
|
|
pinctrl-0 = <0x54a>;
|
|
|
|
bootc {
|
|
bootc,time_spec_user = <0x186a0>;
|
|
bootc,time_spec_eng = <0x186a0>;
|
|
bootc,time_spec_fac = <0x186a0>;
|
|
};
|
|
|
|
cond {
|
|
sec,det_pm_conn_gpios = <0x2df 0x08 0x00>;
|
|
sec,det_pm_conn_name = "sub";
|
|
};
|
|
};
|
|
|
|
qcom,qup_hsuart@0xa88000 {
|
|
compatible = "qcom,msm-geni-serial-hs\0qcom,msm-geni-uart";
|
|
reg = <0xa88000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk\0m-ahb\0s-ahb";
|
|
clocks = <0x27 0x5b 0x27 0x69 0x27 0x6a>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x54b 0x54c>;
|
|
pinctrl-1 = <0x54d 0x54e>;
|
|
interrupts = <0x00 0x163 0x00>;
|
|
qcom,wrapper-core = <0x17a>;
|
|
status = "ok";
|
|
always-on-clock;
|
|
phandle = <0x5ba>;
|
|
};
|
|
|
|
sec_thermistor@0 {
|
|
compatible = "samsung,sec-ap-thermistor";
|
|
status = "okay";
|
|
io-channels = <0xa1 0x4f>;
|
|
io-channel-names = "ap_therm";
|
|
adc_array = <0x70e 0x8a0 0xa3c 0xc04 0xe36 0x1103 0x1467 0x17f5 0x1c02 0x20ba 0x25b4 0x2b63 0x3141 0x3799 0x3d1c 0x44c8 0x4b37 0x51b0 0x5641 0x5bbf 0x5fec 0x6437 0x66e9>;
|
|
temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>;
|
|
};
|
|
|
|
sec_thermistor@1 {
|
|
compatible = "samsung,sec-pa-thermistor";
|
|
status = "okay";
|
|
io-channels = <0x9b 0x4e>;
|
|
io-channel-names = "pa_therm";
|
|
adc_array = <0x745 0x8dc 0xa82 0xc3c 0xe92 0x112d 0x149e 0x1836 0x1c41 0x211f 0x2636 0x2bc9 0x31a3 0x3802 0x3d67 0x453a 0x4b8f 0x518c 0x5730 0x5c17 0x60ae 0x6482 0x672b>;
|
|
temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>;
|
|
};
|
|
|
|
sec_thermistor@2 {
|
|
compatible = "samsung,sec-wf-thermistor";
|
|
status = "okay";
|
|
io-channels = <0x9b 0x4f>;
|
|
io-channel-names = "wf_therm";
|
|
adc_array = <0x753 0x8de 0xa8f 0xc4d 0xe9a 0x1140 0x149f 0x183d 0x1c54 0x2116 0x262e 0x2bdb 0x31c1 0x3816 0x3d7c 0x455a 0x4b86 0x51c4 0x56f2 0x5c43 0x60c5 0x64b3 0x6785>;
|
|
temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>;
|
|
};
|
|
|
|
i2c@26 {
|
|
cell-index = <0x1a>;
|
|
compatible = "i2c-gpio";
|
|
gpios = <0x16c 0x2e 0x00 0x16c 0x2f 0x00>;
|
|
#i2c-gpio,delay-us = <0x02>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x54f>;
|
|
phandle = <0x5bb>;
|
|
|
|
s2mpb03@56 {
|
|
compatible = "samsung,s2mpb03pmic";
|
|
reg = <0x56>;
|
|
additional_reg_init;
|
|
|
|
regulators {
|
|
|
|
s2mpb03-ldo1 {
|
|
regulator-name = "s2mpb03-ldo1";
|
|
regulator-min-microvolt = <0x100590>;
|
|
regulator-max-microvolt = <0x100590>;
|
|
phandle = <0x56b>;
|
|
};
|
|
|
|
s2mpb03-ldo2 {
|
|
regulator-name = "s2mpb03-ldo2";
|
|
regulator-min-microvolt = <0x100590>;
|
|
regulator-max-microvolt = <0x100590>;
|
|
phandle = <0x577>;
|
|
};
|
|
|
|
s2mpb03-ldo3 {
|
|
regulator-name = "s2mpb03-ldo3";
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
phandle = <0x564>;
|
|
};
|
|
|
|
s2mpb03-ldo4 {
|
|
regulator-name = "s2mpb03-ldo4";
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
phandle = <0x571>;
|
|
};
|
|
|
|
s2mpb03-ldo5 {
|
|
regulator-name = "s2mpb03-ldo5";
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
phandle = <0x563>;
|
|
};
|
|
|
|
s2mpb03-ldo6 {
|
|
regulator-name = "s2mpb03-ldo6";
|
|
regulator-min-microvolt = <0x2c4020>;
|
|
regulator-max-microvolt = <0x2c4020>;
|
|
phandle = <0x56a>;
|
|
};
|
|
|
|
s2mpb03-ldo7 {
|
|
regulator-name = "s2mpb03-ldo7";
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
phandle = <0x562>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
battery {
|
|
status = "okay";
|
|
compatible = "samsung,sec-battery";
|
|
pinctrl-names = "default";
|
|
battery,vendor = "Battery";
|
|
battery,charger_name = "sec-direct-charger";
|
|
battery,fuelgauge_name = "s2mu106-fuelgauge";
|
|
battery,technology = <0x02>;
|
|
battery,fgsrc_switch_name = "s2mu106-fuelgauge";
|
|
battery,batt_data_version = <0x01>;
|
|
battery,chip_vendor = "QCOM";
|
|
battery,temp_channel_raw = <0x01>;
|
|
battery,temp_adc_type = <0x01>;
|
|
battery,temp_check_type = <0x01>;
|
|
battery,chg_temp_check_type = <0x02>;
|
|
battery,thermal_source = <0x02>;
|
|
battery,chg_thermal_source = <0x00>;
|
|
battery,dchg_thermal_source = <0x03>;
|
|
battery,polling_time = <0x0a 0x1e 0x1e 0x1e 0xe10>;
|
|
battery,temp_table_adc = <0x84f 0x9ab 0xb96 0xd31 0xf87 0x1218 0x154e 0x18f6 0x1d4b 0x2205 0x274a 0x2d17 0x32f9 0x3974 0x4013 0x46d1 0x4dab 0x534e 0x58fc 0x5dc7 0x60f9 0x63cb 0x6644>;
|
|
battery,temp_table_data = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>;
|
|
battery,inbat_voltage = <0x01>;
|
|
battery,inbat_voltage_table_adc = <0xb04 0xaeb 0xacf 0xab1 0xa92 0xa7e 0xa63 0xa46 0xa2a 0xa0e 0x9f0 0x9d2 0x9b4 0x998 0x980 0x965 0x94b 0x92f 0x910 0x8f4 0x8d9 0x8bc 0x89f>;
|
|
battery,inbat_voltage_table_data = <0x1130 0x10fe 0x10cc 0x109a 0x1068 0x1036 0x1004 0xfd2 0xfa0 0xf6e 0xf3c 0xf0a 0xed8 0xea6 0xe74 0xe42 0xe10 0xdde 0xdac 0xd7a 0xd48 0xd16 0xce4>;
|
|
battery,dchg_temp_table_adc = <0x1aeb6 0x20130 0x26f28 0x2e64a 0x36fc0 0x40b8a 0x4b07e 0x5b116 0x6a884 0x7cdc4 0x90e82 0xa73e8 0xbf4cc 0xd8804 0xf2466 0x10c9f2 0x126654 0x13d4e4 0x153a4a 0x1671de 0x177ba0 0x185790 0x190ed8>;
|
|
battery,dchg_temp_table_data = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>;
|
|
battery,adc_check_count = <0x05>;
|
|
battery,cable_check_type = <0x04>;
|
|
battery,cable_source_type = <0x01>;
|
|
battery,polling_type = <0x01>;
|
|
battery,monitor_initial_count = <0x00>;
|
|
battery,pre_afc_input_current = <0x1f4>;
|
|
battery,prepare_afc_delay = <0x00>;
|
|
battery,battery_check_type = <0x00>;
|
|
battery,check_count = <0x00>;
|
|
battery,ovp_uvlo_check_type = <0x03>;
|
|
battery,temp_check_count = <0x01>;
|
|
battery,temp_highlimit_threshold_event = <0x2bc>;
|
|
battery,temp_highlimit_recovery_event = <0x2a8>;
|
|
battery,temp_high_threshold_event = <0x1f4>;
|
|
battery,temp_high_recovery_event = <0x1e0>;
|
|
battery,temp_low_threshold_event = <0x00>;
|
|
battery,temp_low_recovery_event = <0x14>;
|
|
battery,temp_highlimit_threshold_normal = <0x2bc>;
|
|
battery,temp_highlimit_recovery_normal = <0x2a8>;
|
|
battery,temp_high_threshold_normal = <0x1f4>;
|
|
battery,temp_high_recovery_normal = <0x1e0>;
|
|
battery,temp_low_threshold_normal = <0x00>;
|
|
battery,temp_low_recovery_normal = <0x14>;
|
|
battery,temp_highlimit_threshold_lpm = <0x320>;
|
|
battery,temp_highlimit_recovery_lpm = <0x2ee>;
|
|
battery,temp_high_threshold_lpm = <0x1f4>;
|
|
battery,temp_high_recovery_lpm = <0x1e0>;
|
|
battery,temp_low_threshold_lpm = <0x00>;
|
|
battery,temp_low_recovery_lpm = <0x14>;
|
|
battery,wpc_high_threshold_normal = <0x1c2>;
|
|
battery,wpc_high_recovery_normal = <0x190>;
|
|
battery,wpc_low_threshold_normal = <0x00>;
|
|
battery,wpc_low_recovery_normal = <0x32>;
|
|
battery,full_check_type = <0x02>;
|
|
battery,full_check_type_2nd = <0x02>;
|
|
battery,full_check_count = <0x01>;
|
|
battery,chg_gpio_full_check = <0x00>;
|
|
battery,chg_polarity_full_check = <0x01>;
|
|
battery,chg_heating_prevention_method = <0x01>;
|
|
battery,chg_high_temp = <0x1d6>;
|
|
battery,chg_high_temp_recovery = <0x1ae>;
|
|
battery,chg_input_limit_current = <0x3e8>;
|
|
battery,chg_charging_limit_current = <0x708>;
|
|
battery,dchg_input_limit_current = <0x3e8>;
|
|
battery,dchg_charging_limit_current = <0x7d0>;
|
|
battery,mix_high_temp = <0x1a4>;
|
|
battery,mix_high_chg_temp = <0x1f4>;
|
|
battery,mix_high_temp_recovery = <0x186>;
|
|
battery,full_condition_type = <0x0d>;
|
|
battery,full_condition_soc = <0x5d>;
|
|
battery,full_condition_vcell = <0x109a>;
|
|
battery,recharge_check_count = <0x01>;
|
|
battery,recharge_condition_type = <0x04>;
|
|
battery,recharge_condition_soc = <0x62>;
|
|
battery,recharge_condition_vcell = <0x10b8>;
|
|
battery,charging_total_time = <0x3840>;
|
|
battery,hv_charging_total_time = <0x2a30>;
|
|
battery,normal_charging_total_time = <0x4650>;
|
|
battery,usb_charging_total_time = <0x8ca0>;
|
|
battery,recharging_total_time = <0x1518>;
|
|
battery,charging_reset_time = <0x00>;
|
|
battery,chg_float_voltage = <0x10fe>;
|
|
battery,swelling_high_temp_block = <0x19a>;
|
|
battery,swelling_high_temp_recov = <0x186>;
|
|
battery,swelling_wc_high_temp_recov = <0x186>;
|
|
battery,swelling_low_temp_block_1st = <0x96>;
|
|
battery,swelling_low_temp_recov_1st = <0xaa>;
|
|
battery,swelling_low_temp_block_2nd = <0x32>;
|
|
battery,swelling_low_temp_recov_2nd = <0x46>;
|
|
battery,swelling_low_temp_3rd_ctrl;
|
|
battery,swelling_low_temp_block_3rd = <0xb4>;
|
|
battery,swelling_low_temp_recov_3rd = <0xc8>;
|
|
battery,swelling_low_temp_current = <0x3e8>;
|
|
battery,swelling_low_temp_current_2nd = <0x190>;
|
|
battery,swelling_low_temp_current_3rd = <0xc1c>;
|
|
battery,swelling_low_temp_topoff = <0xfa>;
|
|
battery,swelling_high_temp_current = <0x60e>;
|
|
battery,swelling_high_temp_topoff = <0xfa>;
|
|
battery,swelling_wc_high_temp_current = <0x2ee>;
|
|
battery,swelling_wc_low_temp_current = <0x2ee>;
|
|
battery,swelling_drop_float_voltage = <0x1036>;
|
|
battery,swelling_high_rechg_voltage = <0xfa0>;
|
|
battery,swelling_low_rechg_voltage = <0x1068>;
|
|
battery,siop_event_check_type = <0x01>;
|
|
battery,siop_call_cv_current = <0x14a>;
|
|
battery,siop_call_cc_current = <0x14a>;
|
|
battery,siop_input_limit_current = <0x4b0>;
|
|
battery,siop_charging_limit_current = <0x3e8>;
|
|
battery,siop_hv_input_limit_current = <0x2bc>;
|
|
battery,siop_hv_charging_limit_current = <0x3e8>;
|
|
battery,input_current_by_siop_20 = <0x190>;
|
|
battery,rp_current_rp1 = <0x1f4>;
|
|
battery,rp_current_rp2 = <0x5dc>;
|
|
battery,rp_current_rp3 = <0xbb8>;
|
|
battery,rp_current_rdu_rp3 = <0x834>;
|
|
battery,rp_current_abnormal_rp3 = <0x708>;
|
|
battery,pd_charging_charge_power = <0x3a98>;
|
|
battery,max_charging_current = <0xc4e>;
|
|
battery,battery_full_capacity = <0x1130>;
|
|
battery,ttf_hv_charge_current = <0xabe>;
|
|
battery,ttf_dc25_charge_current = <0xc80>;
|
|
battery,ttf_capacity = <0xe14>;
|
|
battery,cv_data = <0xbfd 0x33e 0x708 0xb9c 0x346 0x6d6 0xb14 0x34e 0x6a4 0xad2 0x355 0x672 0xa8f 0x35b 0x640 0xa1b 0x360 0x60e 0x9db 0x367 0x5dc 0x978 0x36e 0x5aa 0x926 0x374 0x578 0x90f 0x377 0x546 0x853 0x37d 0x514 0x859 0x383 0x4e2 0x7fc 0x389 0x4b0 0x7d9 0x38c 0x47e 0x788 0x391 0x44c 0x77f 0x397 0x41a 0x72f 0x39a 0x3e8 0x6ef 0x39f 0x3b6 0x6d4 0x3a3 0x384 0x676 0x3a9 0x352 0x661 0x3ac 0x320 0x64f 0x3b0 0x2ee 0x60a 0x3b2 0x2bc 0x5fb 0x3b5 0x28a 0x5cc 0x3b8 0x258 0x561 0x3be 0x226 0x52e 0x3c3 0x1f4 0x4f2 0x3c9 0x1c2 0x4a6 0x3cd 0x190 0x477 0x3d1 0x15e 0x430 0x3d5 0x12c 0x3ff 0x3d9 0xfa 0x403 0x3dc 0xc8 0x3f2 0x3e0 0x96 0x361 0x3e2 0x64 0x352 0x3e5 0x32 0x34e 0x3e8 0x00>;
|
|
battery,age_data = <0x00 0x10fe 0x10b8 0x109a 0x5d 0x2d 0x12c 0x10ea 0x10a4 0x1086 0x5c 0x2d 0x190 0x10d6 0x1090 0x1072 0x5b 0x2d 0x2bc 0x10c2 0x107c 0x105e 0x5a 0x2d 0x3e8 0x1090 0x104a 0x102c 0x59 0x2d>;
|
|
battery,step_charging_type = <0x00>;
|
|
battery,step_charging_charge_power = <0x2ee0>;
|
|
battery,step_charging_condition = <0x2d 0x64>;
|
|
battery,step_charging_condition_curr = <0xc1c 0xc1c>;
|
|
battery,step_charging_current = <0xc1c 0xc1c>;
|
|
battery,step_charging_float_voltage = <0x1036 0x10fe>;
|
|
battery,dc_step_chg_type = <0x6b>;
|
|
battery,dc_step_chg_charge_power = <0x55f0>;
|
|
battery,dc_step_chg_step = <0x03>;
|
|
battery,dc_step_chg_cond_vol = <0xffa 0x105e 0x10fe>;
|
|
battery,dc_step_chg_cond_iin = <0x79e 0x627 0x00>;
|
|
battery,dc_step_chg_iin_check_cnt = <0x03>;
|
|
battery,dc_step_chg_cond_soc = <0x09 0x30 0x64>;
|
|
battery,dc_step_chg_val_vfloat = <0xffa 0x105e 0x10fe>;
|
|
battery,dc_step_chg_val_iout = <0x11f8 0xf3c 0xc1c>;
|
|
battery,max_input_voltage = <0x2328>;
|
|
battery,max_input_current = <0xbb8>;
|
|
battery,standard_curr = <0xc1c>;
|
|
battery,expired_time = <0x3138>;
|
|
battery,recharging_expired_time = <0x1518>;
|
|
battery,cisd_alg_index = <0x07>;
|
|
battery,cisd_max_voltage_thr = <0x1388>;
|
|
io-channels = <0x9b 0x50>;
|
|
io-channel-names = "adc-temp";
|
|
battery,recovery_cable;
|
|
battery,lowtemp_support_full_volt;
|
|
battery,enable_water_resistance;
|
|
battery,ta_alert_wa;
|
|
};
|
|
|
|
s2mu107-charger {
|
|
status = "disable";
|
|
compatible = "samsung,s2mu107-switching-charger";
|
|
};
|
|
|
|
s2mu107-direct-charger {
|
|
status = "enable";
|
|
dc,direct_charger_name = "s2mu107-direct-charger";
|
|
dc,step_charge_level = <0x03>;
|
|
dc,dc_step_voltage_45w = <0xffa 0x105e 0x10fe>;
|
|
dc,dc_step_current_45w = <0x11f8 0xf3c 0xc1c>;
|
|
dc,dc_step_voltage_25w = <0xffa 0x105e 0x10fe>;
|
|
dc,dc_step_current_25w = <0x11f8 0xf3c 0xc1c>;
|
|
dc,dc_c_rate = <0x14 0x0e 0x09>;
|
|
};
|
|
|
|
sec-direct-charger {
|
|
status = "okay";
|
|
compatible = "samsung,sec-direct-charger";
|
|
charger,battery_name = "battery";
|
|
charger,main_charger = "s2mu106-charger";
|
|
charger,direct_charger = "pca9468-charger";
|
|
charger,dchg_min_current = <0x7d0>;
|
|
charger,dchg_temp_low_threshold = <0xb4>;
|
|
charger,dchg_temp_high_threshold = <0x19a>;
|
|
charger,ta_alert_wa;
|
|
};
|
|
|
|
battery_params {
|
|
battery,battery_data = <0x05 0x0b 0x7b 0x0a 0xf1 0x09 0x7b 0x09 0x0c 0x09 0xa7 0x08 0x30 0x08 0xc9 0x07 0x93 0x07 0x45 0x07 0xdb 0x06 0xa1 0x06 0x79 0x06 0x5a 0x06 0x41 0x06 0x2e 0x06 0x07 0x06 0xd9 0x05 0x95 0x05 0x80 0x05 0xab 0x03 0x8b 0x01 0x6b 0x08 0x00 0x08 0x95 0x07 0x2a 0x07 0xbf 0x06 0x54 0x06 0xe8 0x05 0x7d 0x05 0x12 0x05 0xa7 0x04 0x3c 0x04 0xd1 0x03 0x66 0x03 0xfb 0x02 0x90 0x02 0x25 0x02 0xba 0x01 0x4e 0x01 0xe3 0x00 0x78 0x00 0x0d 0x00 0xda 0x0f 0x0a 0x0a 0x0a 0x0a 0x1d 0x1d 0x1c 0x1c 0x1c 0x1b 0x1b 0x1c 0x1c 0x1e 0x1f 0x20 0x21 0x23 0x26 0x2d 0x39 0x70 0x1c 0x43 0xbe 0x0b 0x00 0x08 0x291b 0x2710 0x2505 0x22fa 0x20ef 0x1ee3 0x1cd9 0x1ace 0x18c3 0x16b8 0x14ad 0x12a2 0x1098 0xe8d 0xc82 0xa77 0x86c 0x661 0x456 0x24b 0x40 0xffffff45 0xab00 0xa85f 0xa5bd 0xa37d 0xa15c 0x9f6e 0x9d29 0x9b33 0x9a2b 0x98ae 0x96a9 0x9590 0x94cb 0x9433 0x93bb 0x935b 0x929d 0x91c0 0x9071 0x9009 0x8718 0x7cb8 0x00 0x05 0x0b 0x7b 0x0a 0xf2 0x09 0x7b 0x09 0x0c 0x09 0xa7 0x08 0x30 0x08 0xc9 0x07 0x93 0x07 0x45 0x07 0xdb 0x06 0xa1 0x06 0x79 0x06 0x5a 0x06 0x41 0x06 0x2e 0x06 0x07 0x06 0xd9 0x05 0x95 0x05 0x80 0x05 0xab 0x03 0x8b 0x01 0x7e 0x08 0x12 0x08 0xa6 0x07 0x3a 0x07 0xce 0x06 0x62 0x06 0xf6 0x05 0x8a 0x05 0x1e 0x05 0xb2 0x04 0x45 0x04 0xd9 0x03 0x6d 0x03 0x01 0x03 0x95 0x02 0x29 0x02 0xbd 0x01 0x51 0x01 0xe5 0x00 0x79 0x00 0x0d 0x00 0xda 0x0f 0x0a 0x0a 0x0a 0x0a 0x1d 0x1d 0x1c 0x1c 0x1c 0x1b 0x1b 0x1c 0x1c 0x1e 0x1f 0x20 0x21 0x23 0x27 0x2d 0x39 0x70 0xb0 0x45 0xf0 0x0d 0x00 0x08 0x2976 0x2766 0x2557 0x2347 0x2138 0x1f28 0x1d19 0x1b09 0x18fa 0x16ea 0x14db 0x12cb 0x10bc 0xeac 0xc9d 0xa8d 0x87e 0x66e 0x45f 0x24f 0x40 0xffffff45 0xab00 0xa85e 0xa5bd 0xa37c 0xa15d 0x9f6d 0x9d29 0x9b32 0x9a2b 0x98ad 0x96a9 0x9590 0x94cb 0x9433 0x93ba 0x935b 0x929d 0x91bf 0x9070 0x9009 0x8717 0x7cb8 0x00 0x05 0x0b 0x7b 0x0a 0xf2 0x09 0x7b 0x09 0x0c 0x09 0xa7 0x08 0x30 0x08 0xc9 0x07 0x93 0x07 0x45 0x07 0xdb 0x06 0xa1 0x06 0x79 0x06 0x5a 0x06 0x41 0x06 0x2e 0x06 0x07 0x06 0xd9 0x05 0x95 0x05 0x80 0x05 0xab 0x03 0x8b 0x01 0xa1 0x08 0x33 0x08 0xc5 0x07 0x57 0x07 0xea 0x06 0x7c 0x06 0x0e 0x06 0xa0 0x05 0x32 0x05 0xc5 0x04 0x57 0x04 0xe9 0x03 0x7b 0x03 0x0e 0x03 0xa0 0x02 0x32 0x02 0xc4 0x01 0x57 0x01 0xe9 0x00 0x7b 0x00 0x0d 0x00 0xda 0x0f 0x0a 0x0a 0x0a 0x0a 0x1d 0x1d 0x1c 0x1c 0x1c 0x1b 0x1b 0x1c 0x1c 0x1e 0x1f 0x20 0x21 0x23 0x27 0x2d 0x39 0x70 0x9c 0x44 0xd8 0x0b 0x00 0x08 0x2a20 0x2808 0x25f0 0x23d8 0x21c0 0x1fa8 0x1d90 0x1b78 0x1960 0x1748 0x1530 0x1318 0x1100 0xee8 0xcd1 0xab9 0x8a1 0x689 0x471 0x259 0x41 0xffffff43 0xab00 0xa85e 0xa5bd 0xa37c 0xa15d 0x9f6d 0x9d29 0x9b32 0x9a2b 0x98ad 0x96a9 0x9590 0x94cb 0x9433 0x93ba 0x935b 0x929d 0x91bf 0x9070 0x9009 0x8717 0x7cb8 0x00 0x05 0x0b 0x7b 0x0a 0xf2 0x09 0x7b 0x09 0x0c 0x09 0xa7 0x08 0x30 0x08 0xc9 0x07 0x93 0x07 0x45 0x07 0xdb 0x06 0xa1 0x06 0x79 0x06 0x5a 0x06 0x41 0x06 0x2e 0x06 0x07 0x06 0xd9 0x05 0x95 0x05 0x80 0x05 0xab 0x03 0x8b 0x01 0xc8 0x08 0x58 0x08 0xe8 0x07 0x79 0x07 0x09 0x07 0x99 0x06 0x29 0x06 0xba 0x05 0x4a 0x05 0xda 0x04 0x6b 0x04 0xfb 0x03 0x8b 0x03 0x1c 0x03 0xac 0x02 0x3c 0x02 0xcc 0x01 0x5d 0x01 0xed 0x00 0x7d 0x00 0x0e 0x00 0xd9 0x0f 0x0a 0x0a 0x0a 0x0a 0x1d 0x1d 0x1c 0x1c 0x1c 0x1b 0x1b 0x1c 0x1c 0x1e 0x1f 0x20 0x21 0x23 0x27 0x2d 0x39 0x70 0x68 0x43 0x7b 0x0d 0x00 0x08 0x2adf 0x28bd 0x269c 0x247a 0x2259 0x2038 0x1e16 0x1bf5 0x19d3 0x17b2 0x1590 0x136f 0x114e 0xf2c 0xd0b 0xae9 0x8c8 0x6a6 0x485 0x264 0x42 0xffffff42 0xab00 0xa85e 0xa5bd 0xa37c 0xa15d 0x9f6d 0x9d29 0x9b32 0x9a2b 0x98ad 0x96a9 0x9590 0x94cb 0x9433 0x93ba 0x935b 0x929d 0x91bf 0x9070 0x9009 0x8717 0x7cb8 0x00 0x05 0x0b 0x7b 0x0a 0xf2 0x09 0x7b 0x09 0x0c 0x09 0xa7 0x08 0x30 0x08 0xc9 0x07 0x93 0x07 0x45 0x07 0xdb 0x06 0xa1 0x06 0x79 0x06 0x5a 0x06 0x41 0x06 0x2e 0x06 0x07 0x06 0xd9 0x05 0x95 0x05 0x80 0x05 0xab 0x03 0x8b 0x01 0x2d 0x09 0xb8 0x08 0x44 0x08 0xcf 0x07 0x5a 0x07 0xe5 0x06 0x71 0x06 0xfc 0x05 0x87 0x05 0x12 0x05 0x9e 0x04 0x29 0x04 0xb4 0x03 0x3f 0x03 0xcb 0x02 0x56 0x02 0xe1 0x01 0x6c 0x01 0xf8 0x00 0x83 0x00 0x0e 0x00 0xd9 0x0f 0x0a 0x0a 0x0a 0x0a 0x1d 0x1d 0x1c 0x1c 0x1c 0x1b 0x1b 0x1c 0x1c 0x1e 0x1f 0x20 0x21 0x23 0x27 0x2d 0x39 0x70 0x80 0x40 0xe6 0x0c 0x00 0x08 0x2ccf 0x2a94 0x285a 0x2620 0x23e6 0x21ac 0x1f72 0x1d38 0x1afe 0x18c4 0x168a 0x1450 0x1216 0xfdc 0xda2 0xb67 0x92d 0x6f3 0x4b9 0x27f 0x45 0xffffff3d 0xab00 0xa85e 0xa5bd 0xa37c 0xa15d 0x9f6d 0x9d29 0x9b32 0x9a2b 0x98ad 0x96a9 0x9590 0x94cb 0x9433 0x93ba 0x935b 0x929d 0x91bf 0x9070 0x9009 0x8717 0x7cb8 0x00>;
|
|
battery,battery_table3 = <0x05 0x0b 0x7b 0x0a 0xf1 0x09 0x7b 0x09 0x0c 0x09 0xa7 0x08 0x30 0x08 0xc9 0x07 0x93 0x07 0x45 0x07 0xdb 0x06 0xa1 0x06 0x79 0x06 0x5a 0x06 0x41 0x06 0x2e 0x06 0x07 0x06 0xd9 0x05 0x95 0x05 0x80 0x05 0xab 0x03 0x8b 0x01 0x6b 0x08 0x00 0x08 0x95 0x07 0x2a 0x07 0xbf 0x06 0x54 0x06 0xe8 0x05 0x7d 0x05 0x12 0x05 0xa7 0x04 0x3c 0x04 0xd1 0x03 0x66 0x03 0xfb 0x02 0x90 0x02 0x25 0x02 0xba 0x01 0x4e 0x01 0xe3 0x00 0x78 0x00 0x0d 0x00 0xda 0x0f>;
|
|
battery,battery_table4 = <0x0a 0x0a 0x0a 0x0a 0x1d 0x1d 0x1c 0x1c 0x1c 0x1b 0x1b 0x1c 0x1c 0x1e 0x1f 0x20 0x21 0x23 0x26 0x2d 0x39 0x70>;
|
|
battery,batcap = <0x1c 0x43 0xbe 0x0b>;
|
|
battery,soc_arr_val = <0x291b 0x2710 0x2505 0x22fa 0x20ef 0x1ee3 0x1cd9 0x1ace 0x18c3 0x16b8 0x14ad 0x12a2 0x1098 0xe8d 0xc82 0xa77 0x86c 0x661 0x456 0x24b 0x40 0xffffff45>;
|
|
battery,ocv_arr_val = <0xab00 0xa85f 0xa5bd 0xa37d 0xa15c 0x9f6e 0x9d29 0x9b33 0x9a2b 0x98ae 0x96a9 0x9590 0x94cb 0x9433 0x93bb 0x935b 0x929d 0x91c0 0x9071 0x9009 0x8718 0x7cb8>;
|
|
};
|
|
|
|
cable-info {
|
|
default_input_current = <0x708>;
|
|
default_charging_current = <0x834>;
|
|
full_check_current_1st = <0x28a>;
|
|
full_check_current_2nd = <0xfa>;
|
|
|
|
current_group_1 {
|
|
cable_number = <0x01 0x04 0x13 0x15 0x16 0x17 0x1e>;
|
|
input_current = <0x1f4>;
|
|
charging_current = <0x1f4>;
|
|
};
|
|
|
|
current_group_2 {
|
|
cable_number = <0x02 0x19>;
|
|
input_current = <0x3e8>;
|
|
charging_current = <0x3e8>;
|
|
};
|
|
|
|
current_group_3 {
|
|
cable_number = <0x05>;
|
|
input_current = <0x5dc>;
|
|
charging_current = <0x5dc>;
|
|
};
|
|
|
|
current_group_4 {
|
|
cable_number = <0x06 0x07 0x08>;
|
|
input_current = <0x672>;
|
|
charging_current = <0xc1c>;
|
|
};
|
|
|
|
current_group_5 {
|
|
cable_number = <0x09>;
|
|
input_current = <0x672>;
|
|
charging_current = <0x898>;
|
|
};
|
|
|
|
current_group_6 {
|
|
cable_number = <0x0a 0x0c 0x0e 0x0f 0x1b>;
|
|
input_current = <0x384>;
|
|
charging_current = <0x4b0>;
|
|
};
|
|
|
|
current_group_7 {
|
|
cable_number = <0x0d>;
|
|
input_current = <0x2bc>;
|
|
charging_current = <0x4b0>;
|
|
};
|
|
|
|
current_group_8 {
|
|
cable_number = <0x18>;
|
|
input_current = <0x3e8>;
|
|
charging_current = <0x1c2>;
|
|
};
|
|
|
|
current_group_9 {
|
|
cable_number = <0x1a>;
|
|
input_current = <0x7d0>;
|
|
charging_current = <0x708>;
|
|
};
|
|
|
|
current_group_10 {
|
|
cable_number = <0x0b 0x10 0x1c>;
|
|
input_current = <0x28a>;
|
|
charging_current = <0x4b0>;
|
|
};
|
|
|
|
current_group_11 {
|
|
cable_number = <0x1d>;
|
|
input_current = <0x1f4>;
|
|
charging_current = <0x4b0>;
|
|
};
|
|
};
|
|
|
|
samsung,vibrator {
|
|
compatible = "samsung_vib";
|
|
samsung,chip_model = <0x04>;
|
|
samsung,vib_type = "COINDC";
|
|
status = "ok";
|
|
pinctrl-names = "tlmm_pwm_default";
|
|
pinctrl-0 = <0x556>;
|
|
pwms = <0x2fa 0x00 0xf4240>;
|
|
};
|
|
|
|
hall {
|
|
status = "okay";
|
|
compatible = "hall";
|
|
linux,input-type = <0x01>;
|
|
linux,code = <0x15>;
|
|
hall,gpio_flip_cover = <0x16c 0x5b 0x01>;
|
|
debounce-interval = <0x0f>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x557>;
|
|
};
|
|
|
|
certify_hall {
|
|
status = "okay";
|
|
compatible = "certify_hall";
|
|
linux,input-type = <0x01>;
|
|
linux,code = <0x1b>;
|
|
certify_hall,gpio_certify_cover = <0x16c 0x5d 0x01>;
|
|
debounce-interval = <0x0f>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x558>;
|
|
};
|
|
|
|
usb-notifier {
|
|
compatible = "samsung,usb-notifier";
|
|
qcom,disable_control_en = <0x01>;
|
|
qcom,unsupport_host_en = <0x00>;
|
|
phandle = <0x5bc>;
|
|
};
|
|
|
|
qcom,flash_0 {
|
|
label = "flash";
|
|
qcom,led-name = "led:flash_0";
|
|
qcom,max-current = <0x5dc>;
|
|
qcom,default-led-trigger = "flash0_trigger";
|
|
qcom,id = <0x00>;
|
|
qcom,current-ma = <0x578>;
|
|
qcom,duration-ms = <0x500>;
|
|
qcom,ires-ua = <0x30d4>;
|
|
qcom,hdrm-voltage-mv = <0x145>;
|
|
qcom,hdrm-vol-hi-lo-win-mv = <0x64>;
|
|
qcom,record-current-ma = <0xc8>;
|
|
phandle = <0x55d>;
|
|
};
|
|
|
|
qcom,torch_0 {
|
|
label = "torch";
|
|
qcom,led-name = "led:torch_0";
|
|
qcom,max-current = <0x1f4>;
|
|
qcom,default-led-trigger = "torch0_trigger";
|
|
qcom,id = <0x00>;
|
|
qcom,current-ma = <0x12c>;
|
|
qcom,ires-ua = <0x30d4>;
|
|
qcom,hdrm-voltage-mv = <0x145>;
|
|
qcom,hdrm-vol-hi-lo-win-mv = <0x64>;
|
|
phandle = <0x55e>;
|
|
};
|
|
|
|
qcom,camera-flash@0 {
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,camera-flash";
|
|
flash-source = <0x55d>;
|
|
torch-source = <0x55e>;
|
|
status = "ok";
|
|
phandle = <0x560>;
|
|
};
|
|
|
|
12c@14 {
|
|
status = "ok";
|
|
cell-index = <0x0e>;
|
|
compatible = "i2c-gpio";
|
|
gpios = <0x16c 0x65 0x00 0x16c 0x66 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x587>;
|
|
phandle = <0x5be>;
|
|
|
|
usbpd-s2mu106@3C {
|
|
compatible = "s2mu106-usbpd";
|
|
status = "okay";
|
|
reg = <0x3c>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x588>;
|
|
usbpd,usbpd_int = <0x16c 0x20 0x00>;
|
|
};
|
|
|
|
s2mu106-fuelgauge@3B {
|
|
compatible = "samsung,s2mu106-fuelgauge";
|
|
reg = <0x3b>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x551>;
|
|
fuelgauge,fuel_int = <0x16c 0x68 0x00>;
|
|
fuelgauge,charger_name = "s2mu106-charger";
|
|
fuelgauge,fuel_alert_soc = <0x01>;
|
|
fuelgauge,fuel_alert_vol = <0xce4>;
|
|
fuelgauge,low_temp_limit = <0x64>;
|
|
fuelgauge,capacity_max = <0x3de>;
|
|
fuelgauge,capacity_max_margin = <0xc8>;
|
|
fuelgauge,capacity_min = <0x00>;
|
|
fuelgauge,capacity_calculation_type = <0x1c>;
|
|
fuelgauge,capacity_full = <0xbb8>;
|
|
fuelgauge,type_str = "SDI";
|
|
fuelgauge,fg_log_enable = <0x01>;
|
|
fuelgauge,low_voltage_limit = <0xd7a>;
|
|
fuelgauge,low_voltage_limit_lowtemp = <0xbb8>;
|
|
};
|
|
};
|
|
|
|
self_display_FA9_dtsi {
|
|
label = "self_display_FA9_dtsi";
|
|
samsung,self_dispaly_on = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 75 00 01 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,self_dispaly_off = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 75 00 00 29 01 00 00 00 00 02 85 00 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,self_mask_setting_pre = [29 01 00 00 00 00 02 75 10];
|
|
samsung,self_mask_setting_post = [29 01 00 00 00 00 02 75 00];
|
|
samsung,self_mask_on = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 1c 7a 23 00 00 00 95 07 9e 09 5f 01 00 07 9e 03 00 08 ca 0a 10 00 00 00 00 00 0f fc 00 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,self_mask_on_factory = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 14 7a 23 09 60 09 f5 09 f6 0a 8b 00 00 00 00 00 00 00 00 0a 10 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,self_mask_off = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 02 7a 00 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,self_mask_green_circle_on = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 02 7a 21 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,self_mask_green_circle_off = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 02 7a 23 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,self_mask_green_circle_on_factory = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 1c 7a 21 00 00 00 95 07 9e 09 5f 01 00 07 9e 03 00 08 ca 0a 10 00 00 00 00 00 0f fc 00 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,self_mask_green_circle_off_factory = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 14 7a 23 09 60 09 f5 09 f6 0a 8b 00 00 00 00 00 00 00 00 0a 10 29 01 00 00 00 00 03 f0 a5 a5];
|
|
samsung,self_mask_check_tx_pre1 = [29 01 00 00 00 00 03 9f a5 a5 29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 fc 5a 5a 29 01 00 00 00 00 03 b0 09 fe 29 01 00 00 00 00 02 fe 90 29 01 00 00 00 00 03 b0 3d fe 29 01 00 00 00 00 02 fe 80 29 01 00 00 00 00 0a bf 01 07 00 00 00 10 00 00 00 29 01 00 00 14 00 02 7a 00 29 01 00 00 00 00 02 75 10 29 01 00 00 00 00 03 fc a5 a5 29 01 00 00 00 00 03 f0 a5 a5 29 01 00 00 00 00 03 9f 5a 5a];
|
|
samsung,self_mask_check_tx_pre2 = <0x29010000 0x39f 0xa5a52901 0x00 0x3f05a5a 0x29010000 0x3fc 0x5a5a2901 0x00 0x2750129 0x1000022 0x187a21 0x1f40233 0x9600961 0x00 0x00 0xa10ffff 0xffff2901 0x00 0x3fca5a5 0x29010000 0x3f0 0xa5a52901 0x00 0x39f5a5a>;
|
|
samsung,self_mask_check_tx_post = [29 01 00 00 00 00 03 9f a5 a5 29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 03 fc 5a 5a 29 01 00 00 00 00 18 7a 21 09 60 09 f5 09 f6 0a 8b 00 00 00 00 00 00 00 00 0a 10 00 00 00 00 29 01 00 00 00 00 07 bf 00 07 ff 00 00 10 29 01 00 00 00 00 03 fc a5 a5 29 01 00 00 00 00 03 f0 a5 a5 29 01 00 00 00 00 03 9f 5a 5a];
|
|
samsung,self_partial_hlpm_scan_set = [29 01 00 00 00 00 03 f0 5a 5a 29 01 00 00 00 00 11 85 03 1b 0f 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 03 f0 a5 a5];
|
|
phandle = <0x589>;
|
|
};
|
|
|
|
fixed_reg_octa_vddi {
|
|
compatible = "regulator-fixed";
|
|
status = "okay";
|
|
regulator-name = "vddi";
|
|
gpio = <0x16c 0x45 0x00>;
|
|
enable-active-high;
|
|
regulator-boot-on;
|
|
phandle = <0x4ed>;
|
|
};
|
|
|
|
fixed_reg_octa_vddr {
|
|
compatible = "regulator-fixed";
|
|
status = "okay";
|
|
regulator-name = "vddr";
|
|
gpio = <0x16c 0x40 0x00>;
|
|
enable-active-high;
|
|
regulator-boot-on;
|
|
phandle = <0x4ee>;
|
|
};
|
|
|
|
s2mu106-charger {
|
|
status = "disable";
|
|
compatible = "samsung,s2mu106-charger";
|
|
};
|
|
};
|
|
|
|
chosen {
|
|
linux,initrd-end = <0x00 0xa2afe14e>;
|
|
linux,initrd-start = <0x00 0xa2a2b000>;
|
|
kaslr-seed = <0x00 0x00>;
|
|
rng-seed = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 console=null androidboot.hardware=qcom androidboot.memcg=1 lpm_levels.sleep_disabled=1 video=vfb:640x400,bpp=32,memsize=3072000 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=1 androidboot.usbcontroller=a600000.dwc3 firmware_class.path=/vendor/firmware_mnt/image nokaslr printk.devkmsg=on loop.max_part=7 androidboot.verifiedbootstate=orange androidboot.keymaster=1 androidboot.ulcnt=1 androidboot.vbmeta.device=PARTUUID=4b7a15d6-322c-42ac-8110-88b7da0c5d77 androidboot.vbmeta.device=PARTUUID=4b7a15d6-322c-42ac-8110-88b7da0c5d77 androidboot.vbmeta.avb_version=1.0 androidboot.vbmeta.device_state=unlocked androidboot.vbmeta.hash_alg=sha256 androidboot.vbmeta.size=17472 androidboot.vbmeta.digest=fd44b5fec533d9ad255a3da8f32ca945ea672452a7e958e7115fd0cb833c0ed1 androidboot.vbmeta.invalidate_on_error=yes androidboot.veritymode=enforcing androidboot.bootdevice=1d84000.ufshc androidboot.fstab_suffix=default androidboot.boot_devices=soc/1d84000.ufshc androidboot.serialno=RZ8N82WBX7W androidboot.baseband=msm msm_drm.dsi_display0=ss_dsi_panel_S6E3FA9_AMB667UM06_FHD: lcd_id=0xC14400 lcd_id2=0xC14400 androidboot.dtbo_idx=4 androidboot.dtb_idx=0 androidboot.sec_atd.tty=/dev/ttyHS8 androidboot.revision=6 androidboot.ap_serial=0x21C4534B ccic_info=1 fg_reset=0 sec_log=0x200000@0xA1600000 sec_dbg=0x1FF000@0xA1400000 sec_dbg_ex_info=0x1000@0xA15FF000 androidboot.debug_level=0x4f4c sec_debug.enable=0 sec_debug.enable_user=0 msm_rtb.enable=0 androidboot.cp_debug_level=0x55FF sec_debug.enable_cp_debug=0 softdog.soft_margin=100 softdog.soft_panic=1 androidboot.cp_reserved_mem=off androidboot.reserve_mem_region=0x0 androidboot.force_upload=0x0 androidboot.upload_offset=11535348 sec_debug.dump_sink=0x0 signoff=0x7277 androidboot.boot_recovery=0 androidboot.carrierid.param.offset=11534796 androidboot.carrierid=DBT androidboot.sales.param.offset=11534800 androidboot.sales_code=DBT androidboot.prototype.param.offset=11534812 androidboot.im.param.offset=11534384 androidboot.me.param.offset=11534464 androidboot.sn.param.offset=11534544 androidboot.pr.param.offset=11534624 androidboot.sku.param.offset=11534704 androidboot.fastbootd=false androidboot.warranty_bit=1 androidboot.wb.hs=303 androidboot.wb.snapQB=CUSTOM androidboot.ucs_mode=0 androidboot.swp_config=0 androidboot.rp=11 androidboot.svb.ver=SVB1.0 androidboot.em.did=20110021C4534B11 androidboot.em.model=SM-A715F androidboot.em.status=0x0 androidboot.sb.debug0=0x0 androidboot.em.rdx_dump=false androidboot.bootloader=A715FXXSBDXB1 afc_disable=0x30 sapa=0 androidboot.security_mode=1526595585 androidboot.dram_info=FF,05,00,6G androidboot.usrf=11535344 factory_mode=0 androidboot.product.model=SM-A715F androidboot.hardware.sku=hcesimese";
|
|
};
|
|
|
|
aliases {
|
|
spi0 = "/soc/spi@0x880000";
|
|
spi1 = "/soc/spi@0x890000";
|
|
i2c0 = "/soc/i2c@0x888000";
|
|
i2c1 = "/soc/i2c@0xa84000";
|
|
i2c2 = "/soc/i2c@0xa8c000";
|
|
serial0 = "/soc/qcom,qup_uart@0xa88000";
|
|
hsuart0 = "/soc/qcom,qup_uart@0x88c000";
|
|
sdhc1 = "/soc/sdhci@7c4000";
|
|
sdhc2 = "/soc/sdhci@8804000";
|
|
ufshc1 = "/soc/ufshc@1d84000";
|
|
swr0 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/wsa-macro@62f00000/wsa_swr_master";
|
|
swr1 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/rx-macro@62ee0000/rx_swr_master";
|
|
swr2 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@62ec0000/tx_swr_master";
|
|
phandle = <0x4bc>;
|
|
i2c24 = "/soc/i2c@0x880000";
|
|
i2c17 = "/fragment@99/__overlay__/i2c@17";
|
|
hsuart8 = "/soc/qcom,qup_hsuart@0xa88000";
|
|
};
|
|
|
|
memory {
|
|
ddr_device_type = <0x07>;
|
|
device_type = "memory";
|
|
reg = <0x00 0x80000000 0x00 0xc0000000 0x01 0x40000000 0x00 0xbcb00000>;
|
|
};
|
|
|
|
energy-costs {
|
|
compatible = "sched-energy";
|
|
phandle = <0x4bd>;
|
|
|
|
core-cost0 {
|
|
busy-cost-data = <0x493e0 0x0a 0x8ca00 0x12 0xbb800 0x17 0xf8700 0x24 0x130b00 0x34 0x143700 0x43 0x16da00 0x4c 0x189c00 0x5c 0x1a1300 0x71 0x1b8a00 0x77>;
|
|
idle-cost-data = <0x10 0x0c 0x08 0x06>;
|
|
phandle = <0x02>;
|
|
};
|
|
|
|
core-cost1 {
|
|
busy-cost-data = <0x493e0 0xa6 0x9f600 0xf2 0xc4e00 0x125 0xef100 0x1a8 0x10b300 0x1d6 0x127500 0x26d 0x143700 0x2a4 0x17bb00 0x3cd 0x1a1300 0x424 0x1c2000 0x512 0x1d9700 0x552 0x211b00 0x709 0x21b100 0x7d0 0x240900 0x916 0x249f00 0xa08>;
|
|
idle-cost-data = <0x64 0x50 0x3c 0x28>;
|
|
phandle = <0x0c>;
|
|
};
|
|
|
|
cluster-cost0 {
|
|
busy-cost-data = <0x493e0 0x05 0x8ca00 0x05 0xbb800 0x05 0xf8700 0x07 0x130b00 0x08 0x143700 0x0a 0x16da00 0x0a 0x189c00 0x0c 0x1a1300 0x0e 0x1b8a00 0x0e>;
|
|
idle-cost-data = <0x05 0x04 0x03 0x02 0x01>;
|
|
phandle = <0x03>;
|
|
};
|
|
|
|
cluster-cost1 {
|
|
busy-cost-data = <0x493e0 0x13 0x9f600 0x15 0xc4e00 0x15 0xef100 0x19 0x10b300 0x1a 0x127500 0x20 0x143700 0x21 0x17bb00 0x29 0x1a1300 0x2b 0x1c2000 0x31 0x1d9700 0x32 0x211b00 0x3c 0x21b100 0x3d 0x240900 0x3e 0x249f00 0x3f>;
|
|
idle-cost-data = <0x05 0x04 0x03 0x02 0x01>;
|
|
phandle = <0x0d>;
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
firmware {
|
|
phandle = <0x4be>;
|
|
|
|
android {
|
|
compatible = "android,firmware";
|
|
phandle = <0x4bf>;
|
|
|
|
vbmeta {
|
|
compatible = "android,vbmeta";
|
|
parts = "vbmeta,boot,system,vendor,product,odm,prism,optics,vbmeta_samsung,recovery,dtbo,abl,xbl,tz,hyp";
|
|
phandle = <0x4c0>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
ranges;
|
|
phandle = <0x4c1>;
|
|
|
|
uh_heap_region {
|
|
reg = <0x00 0xb0400000 0x00 0x1400000>;
|
|
};
|
|
|
|
hyp_region@85700000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x85700000 0x00 0x600000>;
|
|
phandle = <0x4c2>;
|
|
};
|
|
|
|
xbl_aop_mem@85d00000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x85d00000 0x00 0x2ff000>;
|
|
phandle = <0x4c3>;
|
|
};
|
|
|
|
sec_apps_region@85fff000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x85fff000 0x00 0x1000>;
|
|
phandle = <0x4c4>;
|
|
};
|
|
|
|
smem@86000000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x86000000 0x00 0x200000>;
|
|
phandle = <0x86>;
|
|
};
|
|
|
|
removed_region@86200000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x86200000 0x00 0x5600000>;
|
|
phandle = <0x4c5>;
|
|
};
|
|
|
|
camera_region@8ab00000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x8cb00000 0x00 0x500000>;
|
|
phandle = <0x1ae>;
|
|
};
|
|
|
|
modem_region@8b000000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x8d000000 0x00 0x8c00000>;
|
|
phandle = <0xa9>;
|
|
};
|
|
|
|
pil_video_region@93400000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x95c00000 0x00 0x500000>;
|
|
phandle = <0xad>;
|
|
};
|
|
|
|
cdsp_regions@93900000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x96100000 0x00 0x1e00000>;
|
|
phandle = <0xa5>;
|
|
};
|
|
|
|
pil_adsp_region@95700000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x97f00000 0x00 0x2800000>;
|
|
phandle = <0x97>;
|
|
};
|
|
|
|
wlan_msa_region@97500000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x9a700000 0x00 0x180000>;
|
|
phandle = <0xaf>;
|
|
};
|
|
|
|
npu_region@97680000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x9a880000 0x00 0x80000>;
|
|
phandle = <0xae>;
|
|
};
|
|
|
|
ips_fw_region@97700000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x9a900000 0x00 0x10000>;
|
|
phandle = <0xc1>;
|
|
};
|
|
|
|
ipa_gsi_region@97710000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x9a910000 0x00 0x5000>;
|
|
phandle = <0x4c6>;
|
|
};
|
|
|
|
gpu_region@97715000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x9a915000 0x00 0x2000>;
|
|
phandle = <0x4c7>;
|
|
};
|
|
|
|
qseecom_region@9e400000 {
|
|
compatible = "shared-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0x9e400000 0x00 0x2400000>;
|
|
phandle = <0x90>;
|
|
};
|
|
|
|
cdsp_sec_regions@0x9f800000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0xa4000000 0x00 0xc00000>;
|
|
phandle = <0x1bc>;
|
|
};
|
|
|
|
adsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0xc00000>;
|
|
phandle = <0x88>;
|
|
};
|
|
|
|
cdsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x400000>;
|
|
phandle = <0x19c>;
|
|
};
|
|
|
|
qseecom_ta_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x2000000>;
|
|
phandle = <0x1b9>;
|
|
};
|
|
|
|
sp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x800000>;
|
|
phandle = <0x1ba>;
|
|
};
|
|
|
|
secure_display_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x8c00000>;
|
|
phandle = <0x1bb>;
|
|
};
|
|
|
|
cont_splash_region@9c000000 {
|
|
reg = <0x00 0x9c000000 0x00 0x1700000>;
|
|
label = "cont_splash_region";
|
|
phandle = <0x4c8>;
|
|
};
|
|
|
|
disp_rdump_region@9c000000 {
|
|
reg = <0x00 0x9c000000 0x00 0x1800000>;
|
|
label = "disp_rdump_region";
|
|
phandle = <0x4c9>;
|
|
};
|
|
|
|
dfps_data_region@9d700000 {
|
|
reg = <0x00 0x9e300000 0x00 0x100000>;
|
|
label = "dfps_data_region";
|
|
phandle = <0x19d>;
|
|
};
|
|
|
|
mem_dump_region {
|
|
compatible = "shared-dma-pool";
|
|
reusable;
|
|
size = <0x00 0x2400000>;
|
|
phandle = <0x53>;
|
|
};
|
|
|
|
linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x2000000>;
|
|
linux,cma-default;
|
|
};
|
|
|
|
ss_plog@A1100000 {
|
|
compatible = "ss_plog";
|
|
no-map;
|
|
reg = <0x00 0xa1100000 0x00 0x200000>;
|
|
};
|
|
|
|
ramoops@A1300000 {
|
|
compatible = "ramoops";
|
|
reg = <0x00 0xa1300000 0x00 0x100000>;
|
|
record-size = <0x40000>;
|
|
console-size = <0x40000>;
|
|
ftrace-size = <0x40000>;
|
|
pmsg-size = <0x40000>;
|
|
};
|
|
|
|
sec_debug_region@0 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0xa1400000 0x00 0x800000>;
|
|
phandle = <0x5ad>;
|
|
};
|
|
|
|
sec_debug_autocomment@0 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0xa1c00000 0x00 0x1000>;
|
|
phandle = <0x5ae>;
|
|
};
|
|
|
|
sec_debug_rdx_bootdev@0 {
|
|
no-ship;
|
|
reg = <0x01 0x00 0x00 0x5900000>;
|
|
phandle = <0x5af>;
|
|
};
|
|
|
|
kaslr_region@80001000 {
|
|
compatible = "removed-dma-pool";
|
|
reg = <0x00 0x80001000 0x00 0x1000>;
|
|
phandle = <0x5b0>;
|
|
};
|
|
|
|
rkp_region@B0200000 {
|
|
compatible = "removed-dma-pool";
|
|
reg = <0x00 0xb0200000 0x00 0x200000>;
|
|
phandle = <0x5b1>;
|
|
};
|
|
|
|
tima_region@B0100000 {
|
|
compatible = "removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0xb0100000 0x00 0x100000>;
|
|
phandle = <0x5b2>;
|
|
};
|
|
|
|
modem_shared_mem_region@BA000000 {
|
|
compatible = "modem-removed-dma-pool";
|
|
no-map;
|
|
reg = <0x00 0xba000000 0x00 0x6000000>;
|
|
phandle = <0x530>;
|
|
};
|
|
|
|
camera_mem_region {
|
|
reg = <0x00 0xc2000000 0x00 0x25800000>;
|
|
ion,recyclable;
|
|
phandle = <0x543>;
|
|
};
|
|
};
|
|
|
|
__symbols__ {
|
|
CPU0 = "/cpus/cpu@0";
|
|
L2_0 = "/cpus/cpu@0/l2-cache";
|
|
L3_0 = "/cpus/cpu@0/l2-cache/l3-cache";
|
|
L1_I_0 = "/cpus/cpu@0/l1-icache";
|
|
L1_D_0 = "/cpus/cpu@0/l1-dcache";
|
|
L2_TLB_0 = "/cpus/cpu@0/l2-tlb";
|
|
CPU1 = "/cpus/cpu@100";
|
|
L2_100 = "/cpus/cpu@100/l2-cache";
|
|
L1_I_100 = "/cpus/cpu@100/l1-icache";
|
|
L1_D_100 = "/cpus/cpu@100/l1-dcache";
|
|
L2_TLB_100 = "/cpus/cpu@100/l2-tlb";
|
|
CPU2 = "/cpus/cpu@200";
|
|
L2_200 = "/cpus/cpu@200/l2-cache";
|
|
L1_I_200 = "/cpus/cpu@200/l1-icache";
|
|
L1_D_200 = "/cpus/cpu@200/l1-dcache";
|
|
L2_TLB_200 = "/cpus/cpu@200/l2-tlb";
|
|
CPU3 = "/cpus/cpu@300";
|
|
L2_300 = "/cpus/cpu@300/l2-cache";
|
|
L1_I_300 = "/cpus/cpu@300/l1-icache";
|
|
L1_D_300 = "/cpus/cpu@300/l1-dcache";
|
|
L2_TLB_300 = "/cpus/cpu@300/l2-tlb";
|
|
CPU4 = "/cpus/cpu@400";
|
|
L2_400 = "/cpus/cpu@400/l2-cache";
|
|
L1_I_400 = "/cpus/cpu@400/l1-icache";
|
|
L1_D_400 = "/cpus/cpu@400/l1-dcache";
|
|
L2_TLB_400 = "/cpus/cpu@400/l2-tlb";
|
|
CPU5 = "/cpus/cpu@500";
|
|
L2_500 = "/cpus/cpu@500/l2-cache";
|
|
L1_I_500 = "/cpus/cpu@500/l1-icache";
|
|
L1_D_500 = "/cpus/cpu@500/l1-dcache";
|
|
L2_TLB_500 = "/cpus/cpu@500/l2-tlb";
|
|
CPU6 = "/cpus/cpu@600";
|
|
L2_600 = "/cpus/cpu@600/l2-cache";
|
|
L1_I_600 = "/cpus/cpu@600/l1-icache";
|
|
L1_D_600 = "/cpus/cpu@600/l1-dcache";
|
|
L1_ITLB_600 = "/cpus/cpu@600/l1-itlb";
|
|
L1_DTLB_600 = "/cpus/cpu@600/l1-dtlb";
|
|
L2_TLB_600 = "/cpus/cpu@600/l2-tlb";
|
|
CPU7 = "/cpus/cpu@700";
|
|
L2_700 = "/cpus/cpu@700/l2-cache";
|
|
L1_I_700 = "/cpus/cpu@700/l1-icache";
|
|
L1_D_700 = "/cpus/cpu@700/l1-dcache";
|
|
L1_ITLB_700 = "/cpus/cpu@700/l1-itlb";
|
|
L1_DTLB_700 = "/cpus/cpu@700/l1-dtlb";
|
|
L2_TLB_700 = "/cpus/cpu@700/l2-tlb";
|
|
soc = "/soc";
|
|
jtag_mm0 = "/soc/jtagmm@7040000";
|
|
jtag_mm1 = "/soc/jtagmm@7140000";
|
|
jtag_mm2 = "/soc/jtagmm@7240000";
|
|
jtag_mm3 = "/soc/jtagmm@7340000";
|
|
jtag_mm4 = "/soc/jtagmm@7440000";
|
|
jtag_mm5 = "/soc/jtagmm@7540000";
|
|
jtag_mm6 = "/soc/jtagmm@7640000";
|
|
jtag_mm7 = "/soc/jtagmm@7740000";
|
|
intc = "/soc/interrupt-controller@17a00000";
|
|
pdc = "/soc/interrupt-controller@b220000";
|
|
mem_client_3_size = "/soc/qcom,memshare/qcom,client_3";
|
|
sleep_clk = "/soc/clocks/sleep-clk";
|
|
clock_rpmh = "/soc/qcom,rpmh";
|
|
clock_aop = "/soc/qcom,aopclk";
|
|
clock_gcc = "/soc/qcom,gcc@100000";
|
|
clock_camcc = "/soc/qcom,camcc";
|
|
clock_gpucc = "/soc/qcom,gpucc";
|
|
clock_videocc = "/soc/qcom,videocc@ab00000";
|
|
clock_dispcc = "/soc/qcom,dispcc@af00000";
|
|
clock_npucc = "/soc/qcom,npucc";
|
|
clock_cpucc = "/soc/qcom,cpucc@18321000";
|
|
lmh_dcvs0 = "/soc/qcom,cpucc@18321000/qcom,limits-dcvs@18358800";
|
|
lmh_dcvs1 = "/soc/qcom,cpucc@18321000/qcom,limits-dcvs@18350800";
|
|
cpucc_debug = "/soc/syscon@182a0018";
|
|
mccc_debug = "/soc/syscon@90b0000";
|
|
clock_debug = "/soc/qcom,cc-debug";
|
|
cpu_pmu = "/soc/cpu-pmu";
|
|
gpi_dma0 = "/soc/qcom,gpi-dma@0x800000";
|
|
gpi_dma1 = "/soc/qcom,gpi-dma@0xa00000";
|
|
bluetooth = "/soc/bt_wcn3990";
|
|
slim_aud = "/soc/slim@62dc0000";
|
|
iommu_slim_aud_ctrl_cb = "/soc/slim@62dc0000/qcom,iommu_slim_ctrl_cb";
|
|
dai_slim = "/soc/slim@62dc0000/msm_dai_slim";
|
|
slim_qca = "/soc/slim@62e40000";
|
|
iommu_slim_qca_ctrl_cb = "/soc/slim@62e40000/qcom,iommu_slim_ctrl_cb";
|
|
btfmslim_codec = "/soc/slim@62e40000/wcn3990";
|
|
wdog = "/soc/qcom,wdt@17c10000";
|
|
eud = "/soc/qcom,msm-eud@88e0000";
|
|
thermal_zones = "/soc/thermal-zones";
|
|
pm6150_temp_alarm = "/soc/thermal-zones/pm6150-tz";
|
|
pm6150_trip0 = "/soc/thermal-zones/pm6150-tz/trips/trip0";
|
|
pm6150_trip1 = "/soc/thermal-zones/pm6150-tz/trips/trip1";
|
|
ibat_lvl0 = "/soc/thermal-zones/pm6150-ibat-lvl0/trips/ibat-lvl0";
|
|
ibat_lvl1 = "/soc/thermal-zones/pm6150-ibat-lvl1/trips/ibat-lvl1";
|
|
vbat_lvl0 = "/soc/thermal-zones/pm6150-vbat-lvl0/trips/vbat-lvl0";
|
|
vbat_lvl1 = "/soc/thermal-zones/pm6150-vbat-lvl1/trips/vbat-lvl1";
|
|
vbat_lvl2 = "/soc/thermal-zones/pm6150-vbat-lvl2/trips/vbat-lvl2";
|
|
bcl_lvl0 = "/soc/thermal-zones/pm6150-bcl-lvl0/trips/bcl-lvl0";
|
|
bcl_lvl1 = "/soc/thermal-zones/pm6150-bcl-lvl1/trips/bcl-lvl1";
|
|
bcl_lvl2 = "/soc/thermal-zones/pm6150-bcl-lvl2/trips/bcl-lvl2";
|
|
soc_trip = "/soc/thermal-zones/soc/trips/soc-trip";
|
|
pm6150l_temp_alarm = "/soc/thermal-zones/pm6150l-tz";
|
|
pm6150l_trip0 = "/soc/thermal-zones/pm6150l-tz/trips/trip0";
|
|
pm6150l_trip1 = "/soc/thermal-zones/pm6150l-tz/trips/trip1";
|
|
vph_lvl0 = "/soc/thermal-zones/pm6150l-vph-lvl0/trips/vph-lvl0";
|
|
vph_lvl1 = "/soc/thermal-zones/pm6150l-vph-lvl1/trips/vph-lvl1";
|
|
vph_lvl2 = "/soc/thermal-zones/pm6150l-vph-lvl2/trips/vph-lvl2";
|
|
l_bcl_lvl0 = "/soc/thermal-zones/pm6150l-bcl-lvl0/trips/l-bcl-lvl0";
|
|
l_bcl_lvl1 = "/soc/thermal-zones/pm6150l-bcl-lvl1/trips/l-bcl-lvl1";
|
|
l_bcl_lvl2 = "/soc/thermal-zones/pm6150l-bcl-lvl2/trips/l-bcl-lvl2";
|
|
gpu_trip = "/soc/thermal-zones/gpuss-max-step/trips/gpu-trip";
|
|
cpu0_config = "/soc/thermal-zones/cpu-0-0-step/trips/cpu0-config";
|
|
cpu1_config = "/soc/thermal-zones/cpu-0-1-step/trips/cpu1-config";
|
|
cpu2_config = "/soc/thermal-zones/cpu-0-2-step/trips/cpu2-config";
|
|
cpu3_config = "/soc/thermal-zones/cpu-0-3-step/trips/cpu3-config";
|
|
cpu4_config = "/soc/thermal-zones/cpu-0-4-step/trips/cpu4-config";
|
|
cpu5_config = "/soc/thermal-zones/cpu-0-5-step/trips/cpu5-config";
|
|
cpu6_0_config = "/soc/thermal-zones/cpu-1-0-step/trips/cpu6-0-config";
|
|
cpu6_1_config = "/soc/thermal-zones/cpu-1-1-step/trips/cpu6-1-config";
|
|
cpu7_0_config = "/soc/thermal-zones/cpu-1-2-step/trips/cpu7-0-config";
|
|
cpu7_1_config = "/soc/thermal-zones/cpu-1-3-step/trips/cpu7-1-config";
|
|
aoss_lowc = "/soc/thermal-zones/aoss-lowc/trips/aoss-lowc";
|
|
cpu_1_0_trip = "/soc/thermal-zones/cpu-1-0-lowf/trips/cpu-1-0-trip";
|
|
npu_trip0 = "/soc/thermal-zones/npu-step/trips/npu-trip0";
|
|
q6_hvx_trip0 = "/soc/thermal-zones/q6-hvx-step/trips/q6-hvx-trip0";
|
|
q6_hvx_trip1 = "/soc/thermal-zones/q6-hvx-step/trips/q6-hvx-trip1";
|
|
q6_hvx_trip2 = "/soc/thermal-zones/q6-hvx-step/trips/q6-hvx-trip2";
|
|
batt_trip0 = "/soc/thermal-zones/quiet-therm-step/trips/batt-trip0";
|
|
batt_trip1 = "/soc/thermal-zones/quiet-therm-step/trips/batt-trip1";
|
|
batt_trip2 = "/soc/thermal-zones/quiet-therm-step/trips/batt-trip2";
|
|
modem_trip0 = "/soc/thermal-zones/quiet-therm-step/trips/modem-trip0";
|
|
batt_trip3 = "/soc/thermal-zones/quiet-therm-step/trips/batt-trip3";
|
|
modem_trip1_hvx_trip = "/soc/thermal-zones/quiet-therm-step/trips/modem-trip1-hvx-trip";
|
|
gold_trip = "/soc/thermal-zones/quiet-therm-step/trips/gold-trip";
|
|
batt_trip4 = "/soc/thermal-zones/quiet-therm-step/trips/batt-trip4";
|
|
skin_gpu_trip = "/soc/thermal-zones/quiet-therm-step/trips/skin-gpu-trip";
|
|
modem_trip2 = "/soc/thermal-zones/quiet-therm-step/trips/modem-trip2";
|
|
silver_trip = "/soc/thermal-zones/quiet-therm-step/trips/silver-trip";
|
|
modem_trip3 = "/soc/thermal-zones/quiet-therm-step/trips/modem-trip3";
|
|
tsens0 = "/soc/tsens@c222000";
|
|
tsens1 = "/soc/tsens@c223000";
|
|
dcc = "/soc/dcc_v2@10a2000";
|
|
llcc = "/soc/qcom,llcc@9200000/qcom,sdmmagpie-llcc";
|
|
LLCC_1 = "/soc/qcom,llcc@9200000/llcc_1_dcache";
|
|
LLCC_2 = "/soc/qcom,llcc@9200000/llcc_2_dcache";
|
|
apps_rsc = "/soc/mailbox@18220000";
|
|
disp_rsc = "/soc/mailbox@af20000";
|
|
cmd_db = "/soc/qcom,cmd-db@c3f000c";
|
|
tcsr_mutex_block = "/soc/syscon@1f40000";
|
|
tcsr_mutex = "/soc/hwlock";
|
|
smem = "/soc/qcom,smem";
|
|
apcs = "/soc/syscon@17c0000c";
|
|
apcs_glb = "/soc/mailbox@17c00000";
|
|
glink_modem = "/soc/qcom,glink/modem";
|
|
glink_adsp = "/soc/qcom,glink/adsp";
|
|
glink_cdsp = "/soc/qcom,glink/cdsp";
|
|
msm_cdsp_rm = "/soc/qcom,glink/cdsp/qcom,msm_cdsprm_rpmsg/qcom,msm_cdsp_rm";
|
|
msm_hvx_rm = "/soc/qcom,glink/cdsp/qcom,msm_cdsprm_rpmsg/qcom,msm_hvx_rm";
|
|
glink_spi_xprt_wdsp = "/soc/qcom,glink/wdsp";
|
|
qmp_npu0 = "/soc/qcom,qmp-npu-low@9818000";
|
|
qmp_npu1 = "/soc/qcom,qmp-npu-high@9818000";
|
|
qmp_aop = "/soc/qcom,qmp-aop@c300000";
|
|
modem_smp2p_out = "/soc/qcom,smp2p-modem/master-kernel";
|
|
modem_smp2p_in = "/soc/qcom,smp2p-modem/slave-kernel";
|
|
smp2p_ipa_1_out = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-out";
|
|
smp2p_ipa_1_in = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-in";
|
|
smp2p_wlan_1_in = "/soc/qcom,smp2p-modem/qcom,smp2p-wlan-1-in";
|
|
adsp_smp2p_out = "/soc/qcom,smp2p-adsp/master-kernel";
|
|
adsp_smp2p_in = "/soc/qcom,smp2p-adsp/slave-kernel";
|
|
smp2p_rdbg2_out = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-out";
|
|
smp2p_rdbg2_in = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-in";
|
|
sleepstate_smp2p_out = "/soc/qcom,smp2p-adsp/sleepstate-out";
|
|
sleepstate_smp2p_in = "/soc/qcom,smp2p-adsp/qcom,sleepstate-in";
|
|
cdsp_smp2p_out = "/soc/qcom,smp2p-cdsp/master-kernel";
|
|
cdsp_smp2p_in = "/soc/qcom,smp2p-cdsp/slave-kernel";
|
|
smp2p_rdbg5_out = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-out";
|
|
smp2p_rdbg5_in = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-in";
|
|
smp2p_qvrexternal5_out = "/soc/qcom,smp2p-cdsp/qcom,smp2p-qvrexternal5-out";
|
|
sdcc1_ice = "/soc/sdcc1ice@7C8000";
|
|
sdhc_1 = "/soc/sdhci@7c4000";
|
|
sdhc_2 = "/soc/sdhci@8804000";
|
|
qcom_seecom = "/soc/qseecom@86d00000";
|
|
qcom_smcinvoke = "/soc/smcinvoke@86d00000";
|
|
qcom_rng = "/soc/qrng@793000";
|
|
ufs_ice = "/soc/ufsice@1d90000";
|
|
ufsphy_mem = "/soc/ufsphy_mem@1d87000";
|
|
ufshc_mem = "/soc/ufshc@1d84000";
|
|
qcom_cedev = "/soc/qcedev@1de0000";
|
|
qcom_msmhdcp = "/soc/qcom,msm_hdcp";
|
|
qcom_crypto = "/soc/qcrypto@1de0000";
|
|
qcom_tzlog = "/soc/tz-log@146aa720";
|
|
spmi_bus = "/soc/qcom,spmi@c440000";
|
|
pm6150_revid = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,revid@100";
|
|
pm6150_vadc = "/soc/qcom,spmi@c440000/qcom,pm6150@0/vadc@3100";
|
|
pm6150_adc_tm = "/soc/qcom,spmi@c440000/qcom,pm6150@0/adc_tm@3500";
|
|
pm6150_misc = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,misc@900";
|
|
pm6150_charger = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,qpnp-smb5";
|
|
smb5_vbus = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,qpnp-smb5/qcom,smb5-vbus";
|
|
smb5_vconn = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,qpnp-smb5/qcom,smb5-vconn";
|
|
pm6150_pdphy = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,usb-pdphy@1700";
|
|
pm6150_qg = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qpnp,qg";
|
|
pm6150_bcl = "/soc/qcom,spmi@c440000/qcom,pm6150@0/bcl@1d00";
|
|
bcl_soc = "/soc/qcom,spmi@c440000/qcom,pm6150@0/bcl-soc";
|
|
pm6150_tz = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,temp-alarm@2400";
|
|
pm6150_clkdiv = "/soc/qcom,spmi@c440000/qcom,pm6150@0/clock-controller@5b00";
|
|
pm6150_gpios = "/soc/qcom,spmi@c440000/qcom,pm6150@0/pinctrl@c000";
|
|
gpio1_afc_switch_default = "/soc/qcom,spmi@c440000/qcom,pm6150@0/pinctrl@c000/afc_switch/gpio1_afc_switch_default";
|
|
wcd934x_mclk_default = "/soc/qcom,spmi@c440000/qcom,pm6150@0/pinctrl@c000/wcd934x_mclk/wcd934x_mclk_default";
|
|
pm6150_rtc = "/soc/qcom,spmi@c440000/qcom,pm6150@0/qcom,pm6150_rtc";
|
|
pm6150_vib = "/soc/qcom,spmi@c440000/qcom,pm6150@1/qcom,vibrator@5300";
|
|
pm6150l_revid = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/qcom,revid@100";
|
|
pm6150l_tz = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/qcom,temp-alarm@2400";
|
|
pm6150l_bcl = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/bcl@3d00";
|
|
pm6150l_vadc = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/vadc@3100";
|
|
pm6150l_adc_tm = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/adc_tm@3500";
|
|
pm6150l_clkdiv = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/clock-controller@5b00";
|
|
pm6150l_gpios = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/pinctrl@c000";
|
|
rid_adc_irq_default = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/pinctrl@c000/rid_adc_irq/rid_adc_irq_default";
|
|
gpio11_dig_out_default = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/pinctrl@c000/gpio11_dig_out/gpio11_dig_out_default";
|
|
disp_pins_default = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/pinctrl@c000/disp_pins/disp_pins_default";
|
|
nvm_therm_default = "/soc/qcom,spmi@c440000/qcom,pm6150l@4/pinctrl@c000/nvm_therm/nvm_therm_default";
|
|
pm6150l_lcdb = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00";
|
|
lcdb_ldo_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00/ldo";
|
|
lcdb_ncp_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00/ncp";
|
|
lcdb_bst_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,lcdb@ec00/bst";
|
|
flash_led = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300";
|
|
pm6150l_flash0 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flash_0";
|
|
pm6150l_flash1 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flash_1";
|
|
pm6150l_flash2 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,flash_2";
|
|
pm6150l_torch0 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,torch_0";
|
|
pm6150l_torch1 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,torch_1";
|
|
pm6150l_torch2 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,torch_2";
|
|
pm6150l_switch0 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,led_switch_0";
|
|
pm6150l_switch1 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,led_switch_1";
|
|
pm6150l_switch2 = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d300/qcom,led_switch_2";
|
|
pm6150l_wled = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800";
|
|
wled_flash = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800/qcom,wled-flash";
|
|
wled_torch = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800/qcom,wled-torch";
|
|
wled_switch = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,wled@d800/qcom,wled-switch";
|
|
pm6150l_lpg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,pwms@b100";
|
|
pm6150l_pwm = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,pwms@bc00";
|
|
pm6150l_rgb_led = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,leds@d000";
|
|
pm6150a_amoled = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled";
|
|
oledb_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled/oledb@e000";
|
|
ab_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled/ab@de00";
|
|
ibb_vreg = "/soc/qcom,spmi@c440000/qcom,pm6150l@5/qcom,amoled/ibb@dc00";
|
|
pm8009_gpios = "/soc/qcom,spmi@c440000/qcom,pm8009@a/pinctrl@c000";
|
|
pil_modem = "/soc/qcom,mss@4080000";
|
|
icnss = "/soc/qcom,icnss@18800000";
|
|
ipa_hw = "/soc/qcom,ipa@1e00000";
|
|
llcc_pmu = "/soc/llcc-pmu@90cc000";
|
|
llcc_bw_opp_table = "/soc/llcc-bw-opp-table";
|
|
cpu_cpu_llcc_bw = "/soc/qcom,cpu-cpu-llcc-bw";
|
|
cpu_cpu_llcc_bwmon = "/soc/qcom,cpu-cpu-llcc-bwmon@90b6300";
|
|
ddr_bw_opp_table = "/soc/ddr-bw-opp-table";
|
|
cpu_llcc_ddr_bw = "/soc/qcom,cpu-llcc-ddr-bw";
|
|
cpu_llcc_ddr_bwmon = "/soc/qcom,cpu-llcc-ddr-bwmon@90cd000";
|
|
suspendable_ddr_bw_opp_table = "/soc/suspendable-ddr-bw-opp-table";
|
|
cdsp_cdsp_l3_lat = "/soc/qcom,cdsp-cdsp-l3-lat";
|
|
cpu0_cpu_l3_lat = "/soc/qcom,cpu0-cpu-l3-lat";
|
|
cpu0_cpu_l3_latmon = "/soc/qcom,cpu0-cpu-l3-latmon";
|
|
cpu6_cpu_l3_lat = "/soc/qcom,cpu6-cpu-l3-lat";
|
|
cpu6_cpu_l3_latmon = "/soc/qcom,cpu6-cpu-l3-latmon";
|
|
cpu0_cpu_llcc_lat = "/soc/qcom,cpu0-cpu-llcc-lat";
|
|
cpu0_cpu_llcc_latmon = "/soc/qcom,cpu0-cpu-llcc-latmon";
|
|
cpu6_cpu_llcc_lat = "/soc/qcom,cpu6-cpu-llcc-lat";
|
|
cpu6_cpu_llcc_latmon = "/soc/qcom,cpu6-cpu-llcc-latmon";
|
|
cpu0_llcc_ddr_lat = "/soc/qcom,cpu0-llcc-ddr-lat";
|
|
cpu0_llcc_ddr_latmon = "/soc/qcom,cpu0-llcc-ddr-latmon";
|
|
cpu6_llcc_ddr_lat = "/soc/qcom,cpu6-llcc-ddr-lat";
|
|
cpu6_llcc_ddr_latmon = "/soc/qcom,cpu6-llcc-ddr-latmon";
|
|
cpu0_cpu_ddr_latfloor = "/soc/qcom,cpu0-cpu-ddr-latfloor";
|
|
cpu0_computemon = "/soc/qcom,cpu0-computemon";
|
|
cpu6_cpu_ddr_latfloor = "/soc/qcom,cpu6-cpu-ddr-latfloor";
|
|
cpu6_computemon = "/soc/qcom,cpu6-computemon";
|
|
npu_npu_ddr_bw = "/soc/qcom,npu-npu-ddr-bw";
|
|
npu_npu_ddr_bwmon = "/soc/qcom,npu-npu-ddr-bwmon@9960300";
|
|
ipa_smmu_ap = "/soc/ipa_smmu_ap";
|
|
ipa_smmu_wlan = "/soc/ipa_smmu_wlan";
|
|
ipa_smmu_uc = "/soc/ipa_smmu_uc";
|
|
keepalive_opp_table = "/soc/keepalive-opp-table";
|
|
snoc_cnoc_keepalive = "/soc/qcom,snoc_cnoc_keepalive";
|
|
bus_proxy_client = "/soc/qcom,bus_proxy_client";
|
|
cx_ipeak_lm = "/soc/cx_ipeak@01fed000";
|
|
pcie_0_gdsc = "/soc/qcom,gdsc@16b004";
|
|
ufs_phy_gdsc = "/soc/qcom,gdsc@177004";
|
|
usb30_prim_gdsc = "/soc/qcom,gdsc@10f004";
|
|
hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = "/soc/qcom,gdsc@17d030";
|
|
hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = "/soc/qcom,gdsc@17d03c";
|
|
hlos1_vote_aggre_noc_mmu_tbu1_gdsc = "/soc/qcom,gdsc@17d034";
|
|
hlos1_vote_aggre_noc_mmu_tbu2_gdsc = "/soc/qcom,gdsc@17d038";
|
|
hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = "/soc/qcom,gdsc@17d040";
|
|
hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = "/soc/qcom,gdsc@17d048";
|
|
hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = "/soc/qcom,gdsc@17d044";
|
|
bps_gdsc = "/soc/qcom,gdsc@ad07004";
|
|
ife_0_gdsc = "/soc/qcom,gdsc@ad0a004";
|
|
ife_1_gdsc = "/soc/qcom,gdsc@ad0b004";
|
|
ipe_0_gdsc = "/soc/qcom,gdsc@ad08004";
|
|
ipe_1_gdsc = "/soc/qcom,gdsc@ad09004";
|
|
titan_top_gdsc = "/soc/qcom,gdsc@ad0c1c4";
|
|
mdss_core_gdsc = "/soc/qcom,gdsc@0f03000";
|
|
gpu_cx_hw_ctrl = "/soc/syscon@5091540";
|
|
gpu_gx_domain_addr = "/soc/syscon@0x5091508";
|
|
gpu_gx_sw_reset = "/soc/syscon@0x5091008";
|
|
gpu_cx_gdsc = "/soc/qcom,gdsc@509106c";
|
|
gpu_gx_gdsc = "/soc/qcom,gdsc@509100c";
|
|
mvsc_gdsc = "/soc/qcom,gdsc@0b00814";
|
|
mvs0_gdsc = "/soc/qcom,gdsc@ab00874";
|
|
mvs1_gdsc = "/soc/qcom,gdsc@ab008b4";
|
|
npu_core_gdsc = "/soc/qcom,gdsc@9911028";
|
|
ad_hoc_bus = "/soc/ad-hoc-bus";
|
|
rsc_apps = "/soc/ad-hoc-bus/rsc-apps";
|
|
rsc_disp = "/soc/ad-hoc-bus/rsc-disp";
|
|
bcm_acv = "/soc/ad-hoc-bus/bcm-acv";
|
|
bcm_alc = "/soc/ad-hoc-bus/bcm-alc";
|
|
bcm_mc0 = "/soc/ad-hoc-bus/bcm-mc0";
|
|
bcm_sh0 = "/soc/ad-hoc-bus/bcm-sh0";
|
|
bcm_mm0 = "/soc/ad-hoc-bus/bcm-mm0";
|
|
bcm_mm1 = "/soc/ad-hoc-bus/bcm-mm1";
|
|
bcm_sh2 = "/soc/ad-hoc-bus/bcm-sh2";
|
|
bcm_sh3 = "/soc/ad-hoc-bus/bcm-sh3";
|
|
bcm_mm2 = "/soc/ad-hoc-bus/bcm-mm2";
|
|
bcm_mm3 = "/soc/ad-hoc-bus/bcm-mm3";
|
|
bcm_sh5 = "/soc/ad-hoc-bus/bcm-sh5";
|
|
bcm_sn0 = "/soc/ad-hoc-bus/bcm-sn0";
|
|
bcm_sh8 = "/soc/ad-hoc-bus/bcm-sh8";
|
|
bcm_sh10 = "/soc/ad-hoc-bus/bcm-sh10";
|
|
bcm_ce0 = "/soc/ad-hoc-bus/bcm-ce0";
|
|
bcm_ip0 = "/soc/ad-hoc-bus/bcm-ip0";
|
|
bcm_cn0 = "/soc/ad-hoc-bus/bcm-cn0";
|
|
bcm_qup0 = "/soc/ad-hoc-bus/bcm-qup0";
|
|
bcm_sn1 = "/soc/ad-hoc-bus/bcm-sn1";
|
|
bcm_sn2 = "/soc/ad-hoc-bus/bcm-sn2";
|
|
bcm_sn4 = "/soc/ad-hoc-bus/bcm-sn4";
|
|
bcm_sn9 = "/soc/ad-hoc-bus/bcm-sn9";
|
|
bcm_sn11 = "/soc/ad-hoc-bus/bcm-sn11";
|
|
bcm_sn12 = "/soc/ad-hoc-bus/bcm-sn12";
|
|
bcm_sn14 = "/soc/ad-hoc-bus/bcm-sn14";
|
|
bcm_sn15 = "/soc/ad-hoc-bus/bcm-sn15";
|
|
bcm_acv_display = "/soc/ad-hoc-bus/bcm-acv_display";
|
|
bcm_alc_display = "/soc/ad-hoc-bus/bcm-alc_display";
|
|
bcm_mc0_display = "/soc/ad-hoc-bus/bcm-mc0_display";
|
|
bcm_sh0_display = "/soc/ad-hoc-bus/bcm-sh0_display";
|
|
bcm_mm0_display = "/soc/ad-hoc-bus/bcm-mm0_display";
|
|
bcm_mm1_display = "/soc/ad-hoc-bus/bcm-mm1_display";
|
|
bcm_mm2_display = "/soc/ad-hoc-bus/bcm-mm2_display";
|
|
bcm_mm3_display = "/soc/ad-hoc-bus/bcm-mm3_display";
|
|
fab_aggre1_noc = "/soc/ad-hoc-bus/fab-aggre1_noc";
|
|
fab_aggre2_noc = "/soc/ad-hoc-bus/fab-aggre2_noc";
|
|
fab_camnoc_virt = "/soc/ad-hoc-bus/fab-camnoc_virt";
|
|
fab_compute_noc = "/soc/ad-hoc-bus/fab-compute_noc";
|
|
fab_config_noc = "/soc/ad-hoc-bus/fab-config_noc";
|
|
fab_dc_noc = "/soc/ad-hoc-bus/fab-dc_noc";
|
|
fab_gem_noc = "/soc/ad-hoc-bus/fab-gem_noc";
|
|
fab_ipa_virt = "/soc/ad-hoc-bus/fab-ipa_virt";
|
|
fab_mc_virt = "/soc/ad-hoc-bus/fab-mc_virt";
|
|
fab_mmss_noc = "/soc/ad-hoc-bus/fab-mmss_noc";
|
|
fab_system_noc = "/soc/ad-hoc-bus/fab-system_noc";
|
|
fab_gem_noc_display = "/soc/ad-hoc-bus/fab-gem_noc_display";
|
|
fab_mc_virt_display = "/soc/ad-hoc-bus/fab-mc_virt_display";
|
|
fab_mmss_noc_display = "/soc/ad-hoc-bus/fab-mmss_noc_display";
|
|
mas_qhm_a1noc_cfg = "/soc/ad-hoc-bus/mas-qhm-a1noc-cfg";
|
|
mas_qhm_qup_center = "/soc/ad-hoc-bus/mas-qhm-qup-center";
|
|
mas_qhm_tsif = "/soc/ad-hoc-bus/mas-qhm-tsif";
|
|
mas_xm_emmc = "/soc/ad-hoc-bus/mas-xm-emmc";
|
|
mas_xm_sdc2 = "/soc/ad-hoc-bus/mas-xm-sdc2";
|
|
mas_xm_sdc4 = "/soc/ad-hoc-bus/mas-xm-sdc4";
|
|
mas_xm_ufs_mem = "/soc/ad-hoc-bus/mas-xm-ufs-mem";
|
|
mas_qhm_a2noc_cfg = "/soc/ad-hoc-bus/mas-qhm-a2noc-cfg";
|
|
mas_qhm_qdss_bam = "/soc/ad-hoc-bus/mas-qhm-qdss-bam";
|
|
mas_qhm_qup_north = "/soc/ad-hoc-bus/mas-qhm-qup-north";
|
|
mas_qnm_cnoc = "/soc/ad-hoc-bus/mas-qnm-cnoc";
|
|
mas_qxm_crypto = "/soc/ad-hoc-bus/mas-qxm-crypto";
|
|
mas_qxm_ipa = "/soc/ad-hoc-bus/mas-qxm-ipa";
|
|
mas_xm_pcie3_0 = "/soc/ad-hoc-bus/mas-xm-pcie3-0";
|
|
mas_xm_qdss_etr = "/soc/ad-hoc-bus/mas-xm-qdss-etr";
|
|
mas_xm_usb3_0 = "/soc/ad-hoc-bus/mas-xm-usb3-0";
|
|
mas_qxm_camnoc_hf0_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-hf0-uncomp";
|
|
mas_qxm_camnoc_rt_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-rt-uncomp";
|
|
mas_qxm_camnoc_sf_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-sf-uncomp";
|
|
mas_qxm_camnoc_nrt_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-nrt-uncomp";
|
|
mas_qnm_npu = "/soc/ad-hoc-bus/mas-qnm-npu";
|
|
mas_qhm_spdm = "/soc/ad-hoc-bus/mas-qhm-spdm";
|
|
mas_qnm_snoc = "/soc/ad-hoc-bus/mas-qnm-snoc";
|
|
mas_xm_qdss_dap = "/soc/ad-hoc-bus/mas-xm-qdss-dap";
|
|
mas_qhm_cnoc_dc_noc = "/soc/ad-hoc-bus/mas-qhm-cnoc-dc-noc";
|
|
mas_acm_apps = "/soc/ad-hoc-bus/mas-acm-apps";
|
|
mas_acm_sys_tcu = "/soc/ad-hoc-bus/mas-acm-sys-tcu";
|
|
mas_qhm_gemnoc_cfg = "/soc/ad-hoc-bus/mas-qhm-gemnoc-cfg";
|
|
mas_qnm_cmpnoc = "/soc/ad-hoc-bus/mas-qnm-cmpnoc";
|
|
mas_qnm_mnoc_hf = "/soc/ad-hoc-bus/mas-qnm-mnoc-hf";
|
|
mas_qnm_mnoc_sf = "/soc/ad-hoc-bus/mas-qnm-mnoc-sf";
|
|
mas_qnm_pcie = "/soc/ad-hoc-bus/mas-qnm-pcie";
|
|
mas_qnm_snoc_gc = "/soc/ad-hoc-bus/mas-qnm-snoc-gc";
|
|
mas_qnm_snoc_sf = "/soc/ad-hoc-bus/mas-qnm-snoc-sf";
|
|
mas_qxm_gpu = "/soc/ad-hoc-bus/mas-qxm-gpu";
|
|
mas_ipa_core_master = "/soc/ad-hoc-bus/mas-ipa-core-master";
|
|
mas_llcc_mc = "/soc/ad-hoc-bus/mas-llcc-mc";
|
|
mas_qhm_mnoc_cfg = "/soc/ad-hoc-bus/mas-qhm-mnoc-cfg";
|
|
mas_qxm_camnoc_hf = "/soc/ad-hoc-bus/mas-qxm-camnoc-hf";
|
|
mas_qxm_camnoc_nrt = "/soc/ad-hoc-bus/mas-qxm-camnoc-nrt";
|
|
mas_qxm_camnoc_rt = "/soc/ad-hoc-bus/mas-qxm-camnoc-rt";
|
|
mas_qxm_camnoc_sf = "/soc/ad-hoc-bus/mas-qxm-camnoc-sf";
|
|
mas_qxm_mdp0 = "/soc/ad-hoc-bus/mas-qxm-mdp0";
|
|
mas_qxm_mdp1 = "/soc/ad-hoc-bus/mas-qxm-mdp1";
|
|
mas_qxm_rot = "/soc/ad-hoc-bus/mas-qxm-rot";
|
|
mas_qxm_venus0 = "/soc/ad-hoc-bus/mas-qxm-venus0";
|
|
mas_qxm_venus1 = "/soc/ad-hoc-bus/mas-qxm-venus1";
|
|
mas_qxm_venus_arm9 = "/soc/ad-hoc-bus/mas-qxm-venus-arm9";
|
|
mas_qhm_snoc_cfg = "/soc/ad-hoc-bus/mas-qhm-snoc-cfg";
|
|
mas_qnm_aggre1_noc = "/soc/ad-hoc-bus/mas-qnm-aggre1-noc";
|
|
mas_qnm_aggre2_noc = "/soc/ad-hoc-bus/mas-qnm-aggre2-noc";
|
|
mas_qnm_gemnoc = "/soc/ad-hoc-bus/mas-qnm-gemnoc";
|
|
mas_qxm_pimem = "/soc/ad-hoc-bus/mas-qxm-pimem";
|
|
mas_xm_gic = "/soc/ad-hoc-bus/mas-xm-gic";
|
|
mas_alc = "/soc/ad-hoc-bus/mas-alc";
|
|
mas_qnm_mnoc_hf_display = "/soc/ad-hoc-bus/mas-qnm-mnoc-hf_display";
|
|
mas_qnm_mnoc_sf_display = "/soc/ad-hoc-bus/mas-qnm-mnoc-sf_display";
|
|
mas_llcc_mc_display = "/soc/ad-hoc-bus/mas-llcc-mc_display";
|
|
mas_qxm_mdp0_display = "/soc/ad-hoc-bus/mas-qxm-mdp0_display";
|
|
mas_qxm_mdp1_display = "/soc/ad-hoc-bus/mas-qxm-mdp1_display";
|
|
mas_qxm_rot_display = "/soc/ad-hoc-bus/mas-qxm-rot_display";
|
|
slv_qns_a1noc_snoc = "/soc/ad-hoc-bus/slv-qns-a1noc-snoc";
|
|
slv_srvc_aggre1_noc = "/soc/ad-hoc-bus/slv-srvc-aggre1-noc";
|
|
slv_qns_a2noc_snoc = "/soc/ad-hoc-bus/slv-qns-a2noc-snoc";
|
|
slv_qns_pcie_gemnoc = "/soc/ad-hoc-bus/slv-qns-pcie-gemnoc";
|
|
slv_srvc_aggre2_noc = "/soc/ad-hoc-bus/slv-srvc-aggre2-noc";
|
|
slv_qns_camnoc_uncomp = "/soc/ad-hoc-bus/slv-qns-camnoc-uncomp";
|
|
slv_qns_cdsp_gemnoc = "/soc/ad-hoc-bus/slv-qns-cdsp-gemnoc";
|
|
slv_qhs_a1_noc_cfg = "/soc/ad-hoc-bus/slv-qhs-a1-noc-cfg";
|
|
slv_qhs_a2_noc_cfg = "/soc/ad-hoc-bus/slv-qhs-a2-noc-cfg";
|
|
slv_qhs_ahb2phy_north = "/soc/ad-hoc-bus/slv-qhs-ahb2phy-north";
|
|
slv_qhs_ahb2phy_south = "/soc/ad-hoc-bus/slv-qhs-ahb2phy-south";
|
|
slv_qhs_ahb2phy_west = "/soc/ad-hoc-bus/slv-qhs-ahb2phy-west";
|
|
slv_qhs_aop = "/soc/ad-hoc-bus/slv-qhs-aop";
|
|
slv_qhs_aoss = "/soc/ad-hoc-bus/slv-qhs-aoss";
|
|
slv_qhs_camera_cfg = "/soc/ad-hoc-bus/slv-qhs-camera-cfg";
|
|
slv_qhs_camera_nrt_throttle_cfg = "/soc/ad-hoc-bus/slv-qhs-camera-nrt-thrott-cfg";
|
|
slv_qhs_camera_rt_throttle_cfg = "/soc/ad-hoc-bus/slv-qhs-camera-rt-throttle-cfg";
|
|
slv_qhs_clk_ctl = "/soc/ad-hoc-bus/slv-qhs-clk-ctl";
|
|
slv_qhs_compute_dsp_cfg = "/soc/ad-hoc-bus/slv-qhs-compute-dsp-cfg";
|
|
slv_qhs_cpr_cx = "/soc/ad-hoc-bus/slv-qhs-cpr-cx";
|
|
slv_qhs_cpr_mx = "/soc/ad-hoc-bus/slv-qhs-cpr-mx";
|
|
slv_qhs_crypto0_cfg = "/soc/ad-hoc-bus/slv-qhs-crypto0-cfg";
|
|
slv_qhs_ddrss_cfg = "/soc/ad-hoc-bus/slv-qhs-ddrss-cfg";
|
|
slv_qhs_display_cfg = "/soc/ad-hoc-bus/slv-qhs-display-cfg";
|
|
slv_qhs_display_throttle_cfg = "/soc/ad-hoc-bus/slv-qhs-display-throttle-cfg";
|
|
slv_qhs_emmc_cfg = "/soc/ad-hoc-bus/slv-qhs-emmc-cfg";
|
|
slv_qhs_glm = "/soc/ad-hoc-bus/slv-qhs-glm";
|
|
slv_qhs_gpuss_cfg = "/soc/ad-hoc-bus/slv-qhs-gpuss-cfg";
|
|
slv_qhs_imem_cfg = "/soc/ad-hoc-bus/slv-qhs-imem-cfg";
|
|
slv_qhs_ipa = "/soc/ad-hoc-bus/slv-qhs-ipa";
|
|
slv_qhs_mnoc_cfg = "/soc/ad-hoc-bus/slv-qhs-mnoc-cfg";
|
|
slv_qhs_pcie_cfg = "/soc/ad-hoc-bus/slv-qhs-pcie-cfg";
|
|
slv_qhs_pdm = "/soc/ad-hoc-bus/slv-qhs-pdm";
|
|
slv_qhs_pimem_cfg = "/soc/ad-hoc-bus/slv-qhs-pimem-cfg";
|
|
slv_qhs_prng = "/soc/ad-hoc-bus/slv-qhs-prng";
|
|
slv_qhs_qdss_cfg = "/soc/ad-hoc-bus/slv-qhs-qdss-cfg";
|
|
slv_qhs_qupv3_center = "/soc/ad-hoc-bus/slv-qhs-qupv3-center";
|
|
slv_qhs_qupv3_north = "/soc/ad-hoc-bus/slv-qhs-qupv3-north";
|
|
slv_qhs_sdc2 = "/soc/ad-hoc-bus/slv-qhs-sdc2";
|
|
slv_qhs_sdc4 = "/soc/ad-hoc-bus/slv-qhs-sdc4";
|
|
slv_qhs_snoc_cfg = "/soc/ad-hoc-bus/slv-qhs-snoc-cfg";
|
|
slv_qhs_spdm = "/soc/ad-hoc-bus/slv-qhs-spdm";
|
|
slv_qhs_tcsr = "/soc/ad-hoc-bus/slv-qhs-tcsr";
|
|
slv_qhs_tlmm_north = "/soc/ad-hoc-bus/slv-qhs-tlmm-north";
|
|
slv_qhs_tlmm_south = "/soc/ad-hoc-bus/slv-qhs-tlmm-south";
|
|
slv_qhs_tlmm_west = "/soc/ad-hoc-bus/slv-qhs-tlmm-west";
|
|
slv_qhs_tsif = "/soc/ad-hoc-bus/slv-qhs-tsif";
|
|
slv_qhs_ufs_mem_cfg = "/soc/ad-hoc-bus/slv-qhs-ufs-mem-cfg";
|
|
slv_qhs_usb3_0 = "/soc/ad-hoc-bus/slv-qhs-usb3-0";
|
|
slv_qhs_venus_cfg = "/soc/ad-hoc-bus/slv-qhs-venus-cfg";
|
|
slv_qhs_venus_cvp_throttle_cfg = "/soc/ad-hoc-bus/slv-qhs-venus-cvp-throttle-cfg";
|
|
slv_qhs_venus_throttle_cfg = "/soc/ad-hoc-bus/slv-qhs-venus-throttle-cfg";
|
|
slv_qhs_vsense_ctrl_cfg = "/soc/ad-hoc-bus/slv-qhs-vsense-ctrl-cfg";
|
|
slv_qns_cnoc_a2noc = "/soc/ad-hoc-bus/slv-qns-cnoc-a2noc";
|
|
slv_srvc_cnoc = "/soc/ad-hoc-bus/slv-srvc-cnoc";
|
|
slv_qhs_gemnoc = "/soc/ad-hoc-bus/slv-qhs-gemnoc";
|
|
slv_qhs_llcc = "/soc/ad-hoc-bus/slv-qhs-llcc";
|
|
slv_qhs_mdsp_ms_mpu_cfg = "/soc/ad-hoc-bus/slv-qhs-mdsp-ms-mpu-cfg";
|
|
slv_qns_gem_noc_snoc = "/soc/ad-hoc-bus/slv-qns-gem-noc-snoc";
|
|
slv_qns_llcc = "/soc/ad-hoc-bus/slv-qns-llcc";
|
|
slv_srvc_gemnoc = "/soc/ad-hoc-bus/slv-srvc-gemnoc";
|
|
slv_ipa_core_slave = "/soc/ad-hoc-bus/slv-ipa-core-slave";
|
|
slv_ebi = "/soc/ad-hoc-bus/slv-ebi";
|
|
slv_qns2_mem_noc = "/soc/ad-hoc-bus/slv-qns2-mem-noc";
|
|
slv_qns_mem_noc_hf = "/soc/ad-hoc-bus/slv-qns-mem-noc-hf";
|
|
slv_srvc_mnoc = "/soc/ad-hoc-bus/slv-srvc-mnoc";
|
|
slv_qhs_apss = "/soc/ad-hoc-bus/slv-qhs-apss";
|
|
slv_qns_cnoc = "/soc/ad-hoc-bus/slv-qns-cnoc";
|
|
slv_qns_gemnoc_gc = "/soc/ad-hoc-bus/slv-qns-gemnoc-gc";
|
|
slv_qns_gemnoc_sf = "/soc/ad-hoc-bus/slv-qns-gemnoc-sf";
|
|
slv_qxs_imem = "/soc/ad-hoc-bus/slv-qxs-imem";
|
|
slv_qxs_pimem = "/soc/ad-hoc-bus/slv-qxs-pimem";
|
|
slv_srvc_snoc = "/soc/ad-hoc-bus/slv-srvc-snoc";
|
|
slv_xs_qdss_stm = "/soc/ad-hoc-bus/slv-xs-qdss-stm";
|
|
slv_xs_sys_tcu_cfg = "/soc/ad-hoc-bus/slv-xs-sys-tcu-cfg";
|
|
slv_qns_llcc_display = "/soc/ad-hoc-bus/slv-qns-llcc_display";
|
|
slv_ebi_display = "/soc/ad-hoc-bus/slv-ebi_display";
|
|
slv_qns2_mem_noc_display = "/soc/ad-hoc-bus/slv-qns2-mem-noc_display";
|
|
slv_qns_mem_noc_hf_display = "/soc/ad-hoc-bus/slv-qns-mem-noc-hf_display";
|
|
qupv3_0 = "/soc/qcom,qupv3_0_geni_se@0x8c0000";
|
|
iommu_qupv3_0_geni_se_cb = "/soc/qcom,qupv3_0_geni_se@0x8c0000/qcom,iommu_qupv3_0_geni_se_cb";
|
|
qupv3_se0_i2c = "/soc/i2c@0x880000";
|
|
qupv3_se1_i2c = "/soc/i2c@0x884000";
|
|
qupv3_se2_i2c = "/soc/i2c@0x888000";
|
|
qupv3_se3_i2c = "/soc/i2c@0x88c000";
|
|
qupv3_se4_i2c = "/soc/i2c@0x890000";
|
|
qupv3_se3_4uart = "/soc/qcom,qup_uart@0x88c000";
|
|
qupv3_se4_4uart = "/soc/qcom,qup_uart@0x890000";
|
|
qupv3_se0_spi = "/soc/spi@0x880000";
|
|
qupv3_se1_spi = "/soc/spi@0x884000";
|
|
qupv3_se3_spi = "/soc/spi@0x88c000";
|
|
qupv3_se4_spi = "/soc/spi@0x890000";
|
|
qupv3_1 = "/soc/qcom,qupv3_1_geni_se@0xac0000";
|
|
iommu_qupv3_1_geni_se_cb = "/soc/qcom,qupv3_1_geni_se@0xac0000/qcom,iommu_qupv3_1_geni_se_cb";
|
|
qupv3_se8_2uart = "/soc/qcom,qup_uart@0xa88000";
|
|
qupv3_se6_i2c = "/soc/i2c@0xa80000";
|
|
qupv3_se7_i2c = "/soc/i2c@0xa84000";
|
|
qupv3_se8_i2c = "/soc/i2c@0xa88000";
|
|
qupv3_se9_i2c = "/soc/i2c@0xa8c000";
|
|
fsa4480 = "/soc/i2c@0xa8c000/fsa4480@43";
|
|
qupv3_se10_i2c = "/soc/i2c@0xa90000";
|
|
qupv3_se11_i2c = "/soc/i2c@0xa94000";
|
|
qupv3_se10_4uart = "/soc/qcom,qup_uart@0xa90000";
|
|
qupv3_se11_4uart = "/soc/qcom,qup_uart@0xa94000";
|
|
qupv3_se6_spi = "/soc/spi@0xa80000";
|
|
qupv3_se7_spi = "/soc/spi@0xa84000";
|
|
qupv3_se8_spi = "/soc/spi@0xa88000";
|
|
qupv3_se10_spi = "/soc/spi@0xa90000";
|
|
qupv3_se11_spi = "/soc/spi@0xa94000";
|
|
msm_vidc0 = "/soc/qcom,vidc0";
|
|
msm_vidc1 = "/soc/qcom,vidc1";
|
|
mdss_dsi0_pll = "/soc/qcom,mdss_dsi_pll@ae94a00";
|
|
mdss_dsi1_pll = "/soc/qcom,mdss_dsi_pll@ae96a00";
|
|
mdss_dp_pll = "/soc/qcom,mdss_dp_pll@ae90000";
|
|
mdss_mdp = "/soc/qcom,mdss_mdp@ae00000";
|
|
smmu_sde_sec = "/soc/qcom,mdss_mdp@ae00000/qcom,smmu_sde_sec_cb";
|
|
sde_rscc = "/soc/qcom,sde_rscc@af20000";
|
|
mdss_rotator = "/soc/qcom,mdss_rotator@ae00000";
|
|
rot_reg = "/soc/qcom,mdss_rotator@ae00000/qcom,rot-reg-bus";
|
|
smmu_rot_unsec = "/soc/qcom,mdss_rotator@ae00000/qcom,smmu_rot_unsec_cb";
|
|
smmu_rot_sec = "/soc/qcom,mdss_rotator@ae00000/qcom,smmu_rot_sec_cb";
|
|
mdss_dsi0 = "/soc/qcom,mdss_dsi_ctrl0@ae94000";
|
|
mdss_dsi1 = "/soc/qcom,mdss_dsi_ctrl1@ae96000";
|
|
mdss_dsi_phy0 = "/soc/qcom,mdss_dsi_phy0@ae94400";
|
|
mdss_dsi_phy1 = "/soc/qcom,mdss_dsi_phy1@ae96400";
|
|
ext_disp = "/soc/qcom,msm-ext-disp";
|
|
ext_disp_audio_codec = "/soc/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx";
|
|
sde_dp = "/soc/qcom,dp_display@0";
|
|
cam_csiphy0 = "/soc/qcom,csiphy@ace0000";
|
|
cam_csiphy1 = "/soc/qcom,csiphy@ace2000";
|
|
cam_csiphy2 = "/soc/qcom,csiphy@ace4000";
|
|
cam_csiphy3 = "/soc/qcom,csiphy@ace6000";
|
|
cam_cci0 = "/soc/qcom,cci@ac4a000";
|
|
i2c_freq_100Khz_cci0 = "/soc/qcom,cci@ac4a000/qcom,i2c_standard_mode";
|
|
i2c_freq_400Khz_cci0 = "/soc/qcom,cci@ac4a000/qcom,i2c_fast_mode";
|
|
i2c_freq_custom_cci0 = "/soc/qcom,cci@ac4a000/qcom,i2c_custom_mode";
|
|
i2c_freq_1Mhz_cci0 = "/soc/qcom,cci@ac4a000/qcom,i2c_fast_plus_mode";
|
|
cam_cci1 = "/soc/qcom,cci@ac4b000";
|
|
i2c_freq_100Khz_cci1 = "/soc/qcom,cci@ac4b000/qcom,i2c_standard_mode";
|
|
i2c_freq_400Khz_cci1 = "/soc/qcom,cci@ac4b000/qcom,i2c_fast_mode";
|
|
i2c_freq_custom_cci1 = "/soc/qcom,cci@ac4b000/qcom,i2c_custom_mode";
|
|
i2c_freq_1Mhz_cci1 = "/soc/qcom,cci@ac4b000/qcom,i2c_fast_plus_mode";
|
|
ife_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_ife/iova-mem-map";
|
|
jpeg_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_jpeg/iova-mem-map";
|
|
icp_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_icp/iova-mem-map";
|
|
cpas_cdm_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_cpas_cdm/iova-mem-map";
|
|
fd_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_fd/iova-mem-map";
|
|
lrme_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_lrme/iova-mem-map";
|
|
cam_csid0 = "/soc/qcom,csid0@acb3000";
|
|
cam_vfe0 = "/soc/qcom,vfe0@acaf000";
|
|
cam_csid1 = "/soc/qcom,csid1@acba000";
|
|
cam_vfe1 = "/soc/qcom,vfe1@acb6000";
|
|
cam_csid_lite0 = "/soc/qcom,csid-lite0@acc8000";
|
|
cam_vfe_lite0 = "/soc/qcom,vfe-lite0@acc4000";
|
|
cam_a5 = "/soc/qcom,a5@ac00000";
|
|
cam_ipe0 = "/soc/qcom,ipe0";
|
|
cam_ipe1 = "/soc/qcom,ipe1";
|
|
cam_bps = "/soc/qcom,bps";
|
|
cam_jpeg_enc = "/soc/qcom,jpegenc@ac4e000";
|
|
cam_jpeg_dma = "/soc/qcom,jpegdma@ac52000";
|
|
cam_fd = "/soc/qcom,fd@ac5a000";
|
|
cam_lrme = "/soc/qcom,lrme@ac6b000";
|
|
system_heap = "/soc/qcom,ion/qcom,ion-heap@25";
|
|
kgsl_smmu = "/soc/arm,smmu-kgsl@5040000";
|
|
apps_smmu = "/soc/apps-smmu@0x15000000";
|
|
anoc_1_tbu = "/soc/apps-smmu@0x15000000/anoc_1_tbu@0x15185000";
|
|
anoc_2_tbu = "/soc/apps-smmu@0x15000000/anoc_2_tbu@0x15189000";
|
|
mnoc_hf_0_tbu = "/soc/apps-smmu@0x15000000/mnoc_hf_0_tbu@0x1518d000";
|
|
mnoc_hf_1_tbu = "/soc/apps-smmu@0x15000000/mnoc_hf_1_tbu@0x15191000";
|
|
mnoc_sf_0_tbu = "/soc/apps-smmu@0x15000000/mnoc_sf_0_tbu@0x15195000";
|
|
compute_dsp_0_tbu = "/soc/apps-smmu@0x15000000/compute_dsp_0_tbu@0x15199000";
|
|
adsp_tbu = "/soc/apps-smmu@0x15000000/adsp_tbu@0x1519d000";
|
|
anoc_1_pcie_tbu = "/soc/apps-smmu@0x15000000/anoc_1_pcie_tbu@0x151a1000";
|
|
tlmm = "/soc/pinctrl@3400000";
|
|
ufs_dev_reset_assert = "/soc/pinctrl@3400000/ufs_dev_reset_assert";
|
|
ufs_dev_reset_deassert = "/soc/pinctrl@3400000/ufs_dev_reset_deassert";
|
|
qupv3_se0_i2c_pins = "/soc/pinctrl@3400000/qupv3_se0_i2c_pins";
|
|
qupv3_se0_i2c_active = "/soc/pinctrl@3400000/qupv3_se0_i2c_pins/qupv3_se0_i2c_active";
|
|
qupv3_se0_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sleep";
|
|
qupv3_se0_spi_pins = "/soc/pinctrl@3400000/qupv3_se0_spi_pins";
|
|
qupv3_se0_spi_active = "/soc/pinctrl@3400000/qupv3_se0_spi_pins/qupv3_se0_spi_active";
|
|
qupv3_se0_spi_sleep = "/soc/pinctrl@3400000/qupv3_se0_spi_pins/qupv3_se0_spi_sleep";
|
|
qupv3_se1_i2c_pins = "/soc/pinctrl@3400000/qupv3_se1_i2c_pins";
|
|
qupv3_se1_i2c_active = "/soc/pinctrl@3400000/qupv3_se1_i2c_pins/qupv3_se1_i2c_active";
|
|
qupv3_se1_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sleep";
|
|
qupv3_se1_spi_pins = "/soc/pinctrl@3400000/qupv3_se1_spi_pins";
|
|
qupv3_se1_spi_active = "/soc/pinctrl@3400000/qupv3_se1_spi_pins/qupv3_se1_spi_active";
|
|
qupv3_se1_spi_sleep = "/soc/pinctrl@3400000/qupv3_se1_spi_pins/qupv3_se1_spi_sleep";
|
|
qupv3_se2_i2c_pins = "/soc/pinctrl@3400000/qupv3_se2_i2c_pins";
|
|
qupv3_se2_i2c_active = "/soc/pinctrl@3400000/qupv3_se2_i2c_pins/qupv3_se2_i2c_active";
|
|
qupv3_se2_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se2_i2c_pins/qupv3_se2_i2c_sleep";
|
|
nfc_int_active = "/soc/pinctrl@3400000/nfc/nfc_int_active";
|
|
nfc_int_suspend = "/soc/pinctrl@3400000/nfc/nfc_int_suspend";
|
|
nfc_enable_active = "/soc/pinctrl@3400000/nfc/nfc_enable_active";
|
|
nfc_enable_suspend = "/soc/pinctrl@3400000/nfc/nfc_enable_suspend";
|
|
nfc_clk_req_active = "/soc/pinctrl@3400000/nfc/nfc_clk_req_active";
|
|
nfc_clk_req_suspend = "/soc/pinctrl@3400000/nfc/nfc_clk_req_suspend";
|
|
qupv3_se3_i2c_pins = "/soc/pinctrl@3400000/qupv3_se3_i2c_pins";
|
|
qupv3_se3_i2c_active = "/soc/pinctrl@3400000/qupv3_se3_i2c_pins/qupv3_se3_i2c_active";
|
|
qupv3_se3_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se3_i2c_pins/qupv3_se3_i2c_sleep";
|
|
qupv3_se3_4uart_pins = "/soc/pinctrl@3400000/qupv3_se3_4uart_pins";
|
|
qupv3_se3_ctsrx = "/soc/pinctrl@3400000/qupv3_se3_4uart_pins/qupv3_se3_ctsrx";
|
|
qupv3_se3_rts = "/soc/pinctrl@3400000/qupv3_se3_4uart_pins/qupv3_se3_rts";
|
|
qupv3_se3_tx = "/soc/pinctrl@3400000/qupv3_se3_4uart_pins/qupv3_se3_tx";
|
|
qupv3_se3_spi_pins = "/soc/pinctrl@3400000/qupv3_se3_spi_pins";
|
|
qupv3_se3_spi_active = "/soc/pinctrl@3400000/qupv3_se3_spi_pins/qupv3_se3_spi_active";
|
|
qupv3_se3_spi_sleep = "/soc/pinctrl@3400000/qupv3_se3_spi_pins/qupv3_se3_spi_sleep";
|
|
fpc_reset_low = "/soc/pinctrl@3400000/fpc_reset_int/reset_low";
|
|
fpc_reset_high = "/soc/pinctrl@3400000/fpc_reset_int/reset_high";
|
|
fpc_int_low = "/soc/pinctrl@3400000/fpc_reset_int/int_low";
|
|
qupv3_se4_i2c_pins = "/soc/pinctrl@3400000/qupv3_se4_i2c_pins";
|
|
qupv3_se4_i2c_active = "/soc/pinctrl@3400000/qupv3_se4_i2c_pins/qupv3_se4_i2c_active";
|
|
qupv3_se4_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se4_i2c_pins/qupv3_se4_i2c_sleep";
|
|
smb1390_i2c = "/soc/pinctrl@3400000/smb1390_i2c";
|
|
smb1390_i2c_active = "/soc/pinctrl@3400000/smb1390_i2c/smb1390_i2c_active";
|
|
qupv3_se4_4uart_pins = "/soc/pinctrl@3400000/qupv3_se4_4uart_pins";
|
|
qupv3_se4_ctsrx = "/soc/pinctrl@3400000/qupv3_se4_4uart_pins/qupv3_se4_ctsrx";
|
|
qupv3_se4_rts = "/soc/pinctrl@3400000/qupv3_se4_4uart_pins/qupv3_se4_rts";
|
|
qupv3_se4_tx = "/soc/pinctrl@3400000/qupv3_se4_4uart_pins/qupv3_se4_tx";
|
|
qupv3_se4_spi_pins = "/soc/pinctrl@3400000/qupv3_se4_spi_pins";
|
|
qupv3_se4_spi_active = "/soc/pinctrl@3400000/qupv3_se4_spi_pins/qupv3_se4_spi_active";
|
|
qupv3_se4_spi_sleep = "/soc/pinctrl@3400000/qupv3_se4_spi_pins/qupv3_se4_spi_sleep";
|
|
qupv3_se6_i2c_pins = "/soc/pinctrl@3400000/qupv3_se6_i2c_pins";
|
|
qupv3_se6_i2c_active = "/soc/pinctrl@3400000/qupv3_se6_i2c_pins/qupv3_se6_i2c_active";
|
|
qupv3_se6_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se6_i2c_pins/qupv3_se6_i2c_sleep";
|
|
qupv3_se6_spi_pins = "/soc/pinctrl@3400000/qupv3_se6_spi_pins";
|
|
qupv3_se6_spi_active = "/soc/pinctrl@3400000/qupv3_se6_spi_pins/qupv3_se6_spi_active";
|
|
qupv3_se6_spi_sleep = "/soc/pinctrl@3400000/qupv3_se6_spi_pins/qupv3_se6_spi_sleep";
|
|
qupv3_se7_i2c_pins = "/soc/pinctrl@3400000/qupv3_se7_i2c_pins";
|
|
qupv3_se7_i2c_active = "/soc/pinctrl@3400000/qupv3_se7_i2c_pins/qupv3_se7_i2c_active";
|
|
qupv3_se7_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se7_i2c_pins/qupv3_se7_i2c_sleep";
|
|
qupv3_se7_spi_pins = "/soc/pinctrl@3400000/qupv3_se7_spi_pins";
|
|
qupv3_se7_spi_active = "/soc/pinctrl@3400000/qupv3_se7_spi_pins/qupv3_se7_spi_active";
|
|
qupv3_se7_spi_sleep = "/soc/pinctrl@3400000/qupv3_se7_spi_pins/qupv3_se7_spi_sleep";
|
|
qupv3_se8_i2c_pins = "/soc/pinctrl@3400000/qupv3_se8_i2c_pins";
|
|
qupv3_se8_i2c_active = "/soc/pinctrl@3400000/qupv3_se8_i2c_pins/qupv3_se8_i2c_active";
|
|
qupv3_se8_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se8_i2c_pins/qupv3_se8_i2c_sleep";
|
|
qupv3_se8_2uart_pins = "/soc/pinctrl@3400000/qupv3_se8_2uart_pins";
|
|
qupv3_se8_2uart_active = "/soc/pinctrl@3400000/qupv3_se8_2uart_pins/qupv3_se8_2uart_active";
|
|
qupv3_se8_2uart_sleep = "/soc/pinctrl@3400000/qupv3_se8_2uart_pins/qupv3_se8_2uart_sleep";
|
|
qupv3_se8_spi_pins = "/soc/pinctrl@3400000/qupv3_se8_spi_pins";
|
|
qupv3_se8_spi_active = "/soc/pinctrl@3400000/qupv3_se8_spi_pins/qupv3_se8_spi_active";
|
|
qupv3_se8_spi_sleep = "/soc/pinctrl@3400000/qupv3_se8_spi_pins/qupv3_se8_spi_sleep";
|
|
qupv3_se9_i2c_pins = "/soc/pinctrl@3400000/qupv3_se9_i2c_pins";
|
|
qupv3_se9_i2c_active = "/soc/pinctrl@3400000/qupv3_se9_i2c_pins/qupv3_se9_i2c_active";
|
|
qupv3_se9_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se9_i2c_pins/qupv3_se9_i2c_sleep";
|
|
qupv3_se10_i2c_pins = "/soc/pinctrl@3400000/qupv3_se10_i2c_pins";
|
|
qupv3_se10_i2c_active = "/soc/pinctrl@3400000/qupv3_se10_i2c_pins/qupv3_se10_i2c_active";
|
|
qupv3_se10_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se10_i2c_pins/qupv3_se10_i2c_sleep";
|
|
qupv3_se10_4uart_pins = "/soc/pinctrl@3400000/qupv3_se10_4uart_pins";
|
|
qupv3_se10_ctsrx = "/soc/pinctrl@3400000/qupv3_se10_4uart_pins/qupv3_se10_ctsrx";
|
|
qupv3_se10_rts = "/soc/pinctrl@3400000/qupv3_se10_4uart_pins/qupv3_se10_rts";
|
|
qupv3_se10_tx = "/soc/pinctrl@3400000/qupv3_se10_4uart_pins/qupv3_se10_tx";
|
|
qupv3_se10_spi_pins = "/soc/pinctrl@3400000/qupv3_se10_spi_pins";
|
|
qupv3_se10_spi_active = "/soc/pinctrl@3400000/qupv3_se10_spi_pins/qupv3_se10_spi_active";
|
|
qupv3_se10_spi_sleep = "/soc/pinctrl@3400000/qupv3_se10_spi_pins/qupv3_se10_spi_sleep";
|
|
qupv3_se11_i2c_pins = "/soc/pinctrl@3400000/qupv3_se11_i2c_pins";
|
|
qupv3_se11_i2c_active = "/soc/pinctrl@3400000/qupv3_se11_i2c_pins/qupv3_se11_i2c_active";
|
|
qupv3_se11_i2c_sleep = "/soc/pinctrl@3400000/qupv3_se11_i2c_pins/qupv3_se11_i2c_sleep";
|
|
qupv3_se11_4uart_pins = "/soc/pinctrl@3400000/qupv3_se11_4uart_pins";
|
|
qupv3_se11_ctsrx = "/soc/pinctrl@3400000/qupv3_se11_4uart_pins/qupv3_se11_ctsrx";
|
|
qupv3_se11_rts = "/soc/pinctrl@3400000/qupv3_se11_4uart_pins/qupv3_se11_rts";
|
|
qupv3_se11_tx = "/soc/pinctrl@3400000/qupv3_se11_4uart_pins/qupv3_se11_tx";
|
|
qupv3_se11_spi_pins = "/soc/pinctrl@3400000/qupv3_se11_spi_pins";
|
|
qupv3_se11_spi_active = "/soc/pinctrl@3400000/qupv3_se11_spi_pins/qupv3_se11_spi_active";
|
|
qupv3_se11_spi_sleep = "/soc/pinctrl@3400000/qupv3_se11_spi_pins/qupv3_se11_spi_sleep";
|
|
sde_te_active = "/soc/pinctrl@3400000/pmx_sde_te/sde_te_active";
|
|
sde_te_suspend = "/soc/pinctrl@3400000/pmx_sde_te/sde_te_suspend";
|
|
sde_te1_active = "/soc/pinctrl@3400000/pmx_sde_te/sde_te1_active";
|
|
sde_te1_suspend = "/soc/pinctrl@3400000/pmx_sde_te/sde_te1_suspend";
|
|
sde_dp_aux_active = "/soc/pinctrl@3400000/sde_dp_aux_active";
|
|
sde_dp_aux_suspend = "/soc/pinctrl@3400000/sde_dp_aux_suspend";
|
|
sde_dp_usbplug_cc_active = "/soc/pinctrl@3400000/sde_dp_usbplug_cc_active";
|
|
sde_dp_usbplug_cc_suspend = "/soc/pinctrl@3400000/sde_dp_usbplug_cc_suspend";
|
|
wsa_swr_clk_sleep = "/soc/pinctrl@3400000/wsa_swr_clk_pin/wsa_swr_clk_sleep";
|
|
wsa_swr_clk_active = "/soc/pinctrl@3400000/wsa_swr_clk_pin/wsa_swr_clk_active";
|
|
wsa_swr_data_sleep = "/soc/pinctrl@3400000/wsa_swr_data_pin/wsa_swr_data_sleep";
|
|
wsa_swr_data_active = "/soc/pinctrl@3400000/wsa_swr_data_pin/wsa_swr_data_active";
|
|
spkr_1_sd_n_sleep = "/soc/pinctrl@3400000/spkr_1_sd_n/spkr_1_sd_n_sleep";
|
|
spkr_1_sd_n_active = "/soc/pinctrl@3400000/spkr_1_sd_n/spkr_1_sd_n_active";
|
|
spkr_2_sd_n_sleep = "/soc/pinctrl@3400000/spkr_2_sd_n/spkr_2_sd_n_sleep";
|
|
spkr_2_sd_n_active = "/soc/pinctrl@3400000/spkr_2_sd_n/spkr_2_sd_n_active";
|
|
wcd_intr_default = "/soc/pinctrl@3400000/wcd9xxx_intr/wcd_intr_default";
|
|
fsa_usbc_ana_en = "/soc/pinctrl@3400000/fsa_usbc_ana_en_n@42/fsa_usbc_ana_en";
|
|
cci0_active = "/soc/pinctrl@3400000/cci0_active";
|
|
cci0_suspend = "/soc/pinctrl@3400000/cci0_suspend";
|
|
cci1_active = "/soc/pinctrl@3400000/cci1_active";
|
|
cci1_suspend = "/soc/pinctrl@3400000/cci1_suspend";
|
|
cci2_active = "/soc/pinctrl@3400000/cci2_active";
|
|
cci2_suspend = "/soc/pinctrl@3400000/cci2_suspend";
|
|
cam_sensor_mclk0_active = "/soc/pinctrl@3400000/cam_sensor_mclk0_active";
|
|
cam_sensor_mclk0_suspend = "/soc/pinctrl@3400000/cam_sensor_mclk0_suspend";
|
|
cam_sensor_mclk1_active = "/soc/pinctrl@3400000/cam_sensor_mclk1_active";
|
|
cam_sensor_mclk1_suspend = "/soc/pinctrl@3400000/cam_sensor_mclk1_suspend";
|
|
cam_sensor_mclk2_active = "/soc/pinctrl@3400000/cam_sensor_mclk2_active";
|
|
cam_sensor_mclk2_suspend = "/soc/pinctrl@3400000/cam_sensor_mclk2_suspend";
|
|
cam_sensor_mclk3_active = "/soc/pinctrl@3400000/cam_sensor_mclk3_active";
|
|
cam_sensor_mclk3_suspend = "/soc/pinctrl@3400000/cam_sensor_mclk3_suspend";
|
|
sdc1_clk_on = "/soc/pinctrl@3400000/sdc1_clk_on";
|
|
sdc1_clk_off = "/soc/pinctrl@3400000/sdc1_clk_off";
|
|
sdc1_cmd_on = "/soc/pinctrl@3400000/sdc1_cmd_on";
|
|
sdc1_cmd_off = "/soc/pinctrl@3400000/sdc1_cmd_off";
|
|
sdc1_data_on = "/soc/pinctrl@3400000/sdc1_data_on";
|
|
sdc1_data_off = "/soc/pinctrl@3400000/sdc1_data_off";
|
|
sdc1_rclk_on = "/soc/pinctrl@3400000/sdc1_rclk_on";
|
|
sdc1_rclk_off = "/soc/pinctrl@3400000/sdc1_rclk_off";
|
|
sdc2_clk_on = "/soc/pinctrl@3400000/sdc2_clk_on";
|
|
sdc2_clk_off = "/soc/pinctrl@3400000/sdc2_clk_off";
|
|
sdc2_cmd_on = "/soc/pinctrl@3400000/sdc2_cmd_on";
|
|
sdc2_cmd_off = "/soc/pinctrl@3400000/sdc2_cmd_off";
|
|
sdc2_data_on = "/soc/pinctrl@3400000/sdc2_data_on";
|
|
sdc2_data_off = "/soc/pinctrl@3400000/sdc2_data_off";
|
|
sdc2_cd_on = "/soc/pinctrl@3400000/cd_on";
|
|
sdc2_cd_off = "/soc/pinctrl@3400000/cd_off";
|
|
ts_active = "/soc/pinctrl@3400000/pmx_ts_active/ts_active";
|
|
ts_int_suspend = "/soc/pinctrl@3400000/pmx_ts_int_suspend/ts_int_suspend";
|
|
ts_reset_suspend = "/soc/pinctrl@3400000/pmx_ts_reset_suspend/ts_reset_suspend";
|
|
ts_release = "/soc/pinctrl@3400000/pmx_ts_release/ts_release";
|
|
VDD_GFX_LEVEL = "/soc/rpmh-regulator-gfxlvl/regulator-pm6150-s2-level";
|
|
S2A_LEVEL = "/soc/rpmh-regulator-gfxlvl/regulator-pm6150-s2-level";
|
|
pm6150_s2_level = "/soc/rpmh-regulator-gfxlvl/regulator-pm6150-s2-level";
|
|
VDD_MX_LEVEL = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3";
|
|
S3A_LEVEL = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3";
|
|
pm6150_s3_level = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3";
|
|
VDD_MX_LEVEL_AO = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3-level-ao";
|
|
S3A_LEVEL_AO = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3-level-ao";
|
|
pm6150_s3_level_ao = "/soc/rpmh-regulator-mxlvl/regulator-pm6150-s3-level-ao";
|
|
mx_cdev = "/soc/rpmh-regulator-mxlvl/mx-cdev-lvl";
|
|
S1C = "/soc/rpmh-regulator-smpc1/regulator-pm6150l-s1";
|
|
pm6150l_s1 = "/soc/rpmh-regulator-smpc1/regulator-pm6150l-s1";
|
|
VDD_CX_LEVEL = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2";
|
|
S2C_LEVEL = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2";
|
|
pm6150l_s2_level = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2";
|
|
VDD_CX_LEVEL_AO = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2-level-ao";
|
|
S2C_LEVEL_AO = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2-level-ao";
|
|
pm6150l_s2_level_ao = "/soc/rpmh-regulator-cxlvl/regulator-pm6150l-s2-level-ao";
|
|
cx_cdev = "/soc/rpmh-regulator-cxlvl/regulator-cdev";
|
|
VDD_MSS_LEVEL = "/soc/rpmh-regulator-modemlvl/regulator-pm6150l-s7";
|
|
S7C_LEVEL = "/soc/rpmh-regulator-modemlvl/regulator-pm6150l-s7";
|
|
pm6150l_s7_level = "/soc/rpmh-regulator-modemlvl/regulator-pm6150l-s7";
|
|
S8C = "/soc/rpmh-regulator-smpc8/regulator-pm6150l-s8";
|
|
pm6150l_s8 = "/soc/rpmh-regulator-smpc8/regulator-pm6150l-s8";
|
|
S1F = "/soc/rpmh-regulator-smpf1/regulator-pm8009-s1";
|
|
pm8009_s1 = "/soc/rpmh-regulator-smpf1/regulator-pm8009-s1";
|
|
S2F = "/soc/rpmh-regulator-smpf2/regulator-pm8009-s2";
|
|
pm8009_s2 = "/soc/rpmh-regulator-smpf2/regulator-pm8009-s2";
|
|
L1A = "/soc/rpmh-regulator-ldoa1/regulator-pm6150-l1";
|
|
pm6150_l1 = "/soc/rpmh-regulator-ldoa1/regulator-pm6150-l1";
|
|
L2A = "/soc/rpmh-regulator-ldoa2/regulator-pm6150-l2";
|
|
pm6150_l2 = "/soc/rpmh-regulator-ldoa2/regulator-pm6150-l2";
|
|
L3A = "/soc/rpmh-regulator-ldoa3/regulator-pm6150-l3";
|
|
pm6150_l3 = "/soc/rpmh-regulator-ldoa3/regulator-pm6150-l3";
|
|
L4A = "/soc/rpmh-regulator-ldoa4/regulator-pm6150-l4";
|
|
pm6150_l4 = "/soc/rpmh-regulator-ldoa4/regulator-pm6150-l4";
|
|
L5A = "/soc/rpmh-regulator-ldoa5/regulator-pm6150-l5";
|
|
pm6150_l5 = "/soc/rpmh-regulator-ldoa5/regulator-pm6150-l5";
|
|
L6A = "/soc/rpmh-regulator-ldoa6/regulator-pm6150-l6";
|
|
pm6150_l6 = "/soc/rpmh-regulator-ldoa6/regulator-pm6150-l6";
|
|
LPI_MX_LEVEL = "/soc/rpmh-regulator-lmxlvl/regulator-pm6150-l7";
|
|
L7A_LEVEL = "/soc/rpmh-regulator-lmxlvl/regulator-pm6150-l7";
|
|
pm6150_l7_level = "/soc/rpmh-regulator-lmxlvl/regulator-pm6150-l7";
|
|
LPI_CX_LEVEL = "/soc/rpmh-regulator-lcxlvl/regulator-pm6150-l8";
|
|
L8A_LEVEL = "/soc/rpmh-regulator-lcxlvl/regulator-pm6150-l8";
|
|
pm6150_l8_level = "/soc/rpmh-regulator-lcxlvl/regulator-pm6150-l8";
|
|
WCSS_CX = "/soc/rpmh-regulator-ldoa9/regulator-pm6150-l9";
|
|
L9A = "/soc/rpmh-regulator-ldoa9/regulator-pm6150-l9";
|
|
pm6150_l9 = "/soc/rpmh-regulator-ldoa9/regulator-pm6150-l9";
|
|
L10A = "/soc/rpmh-regulator-ldoa10/regulator-pm6150-l10";
|
|
pm6150_l10 = "/soc/rpmh-regulator-ldoa10/regulator-pm6150-l10";
|
|
L11A = "/soc/rpmh-regulator-ldoa11/regulator-pm6150-l11";
|
|
pm6150_l11 = "/soc/rpmh-regulator-ldoa11/regulator-pm6150-l11";
|
|
L12A = "/soc/rpmh-regulator-ldoa12/regulator-pm6150-l12";
|
|
pm6150_l12 = "/soc/rpmh-regulator-ldoa12/regulator-pm6150-l12";
|
|
L13A = "/soc/rpmh-regulator-ldoa13/regulator-pm6150-l13";
|
|
pm6150_l13 = "/soc/rpmh-regulator-ldoa13/regulator-pm6150-l13";
|
|
L14A = "/soc/rpmh-regulator-ldoa14/regulator-pm6150-l14";
|
|
pm6150_l14 = "/soc/rpmh-regulator-ldoa14/regulator-pm6150-l14";
|
|
L15A = "/soc/rpmh-regulator-ldoa15/regulator-pm6150-l15";
|
|
pm6150_l15 = "/soc/rpmh-regulator-ldoa15/regulator-pm6150-l15";
|
|
L16A = "/soc/rpmh-regulator-ldoa16/regulator-pm6150-l16";
|
|
pm6150_l16 = "/soc/rpmh-regulator-ldoa16/regulator-pm6150-l16";
|
|
L17A = "/soc/rpmh-regulator-ldoa17/regulator-pm6150-l17";
|
|
pm6150_l17 = "/soc/rpmh-regulator-ldoa17/regulator-pm6150-l17";
|
|
L18A = "/soc/rpmh-regulator-ldoa18/regulator-pm6150-l18";
|
|
pm6150_l18 = "/soc/rpmh-regulator-ldoa18/regulator-pm6150-l18";
|
|
L19A = "/soc/rpmh-regulator-ldoa19/regulator-pm6150-l19";
|
|
pm6150_l19 = "/soc/rpmh-regulator-ldoa19/regulator-pm6150-l19";
|
|
L1C = "/soc/rpmh-regulator-ldoc1/regulator-pm6150l-l1";
|
|
pm6150l_l1 = "/soc/rpmh-regulator-ldoc1/regulator-pm6150l-l1";
|
|
L2C = "/soc/rpmh-regulator-ldoc2/regulator-pm6150l-l2";
|
|
pm6150l_l2 = "/soc/rpmh-regulator-ldoc2/regulator-pm6150l-l2";
|
|
L3C = "/soc/rpmh-regulator-ldoc3/regulator-pm6150l-l3";
|
|
pm6150l_l3 = "/soc/rpmh-regulator-ldoc3/regulator-pm6150l-l3";
|
|
L4C = "/soc/rpmh-regulator-ldoc4/regulator-pm6150l-l4";
|
|
pm6150l_l4 = "/soc/rpmh-regulator-ldoc4/regulator-pm6150l-l4";
|
|
L5C = "/soc/rpmh-regulator-ldoc5/regulator-pm6150l-l5";
|
|
pm6150l_l5 = "/soc/rpmh-regulator-ldoc5/regulator-pm6150l-l5";
|
|
L6C = "/soc/rpmh-regulator-ldoc6/regulator-pm6150l-l6";
|
|
pm6150l_l6 = "/soc/rpmh-regulator-ldoc6/regulator-pm6150l-l6";
|
|
L7C = "/soc/rpmh-regulator-ldoc7/regulator-pm6150l-l7";
|
|
pm6150l_l7 = "/soc/rpmh-regulator-ldoc7/regulator-pm6150l-l7";
|
|
L8C = "/soc/rpmh-regulator-ldoc8/regulator-pm6150l-l8";
|
|
pm6150l_l8 = "/soc/rpmh-regulator-ldoc8/regulator-pm6150l-l8";
|
|
L9C = "/soc/rpmh-regulator-ldoc9/regulator-pm6150l-l9";
|
|
pm6150l_l9 = "/soc/rpmh-regulator-ldoc9/regulator-pm6150l-l9";
|
|
L10C = "/soc/rpmh-regulator-ldoc10/regulator-pm6150l-l10";
|
|
pm6150l_l10 = "/soc/rpmh-regulator-ldoc10/regulator-pm6150l-l10";
|
|
L11C = "/soc/rpmh-regulator-ldoc11/regulator-pm6150l-l11";
|
|
pm6150l_l11 = "/soc/rpmh-regulator-ldoc11/regulator-pm6150l-l11";
|
|
BOB = "/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob";
|
|
pm6150l_bob = "/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob";
|
|
BOB_AO = "/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob-ao";
|
|
pm6150l_bob_ao = "/soc/rpmh-regulator-bobc1/regulator-pm6150l-bob-ao";
|
|
L1F = "/soc/rpmh-regulator-ldof1/regulator-pm8009-l1";
|
|
pm8009_l1 = "/soc/rpmh-regulator-ldof1/regulator-pm8009-l1";
|
|
L2F = "/soc/rpmh-regulator-ldof2/regulator-pm8009-l2";
|
|
pm8009_l2 = "/soc/rpmh-regulator-ldof2/regulator-pm8009-l2";
|
|
L4F = "/soc/rpmh-regulator-ldof4/regulator-pm8009-l4";
|
|
pm8009_l4 = "/soc/rpmh-regulator-ldof4/regulator-pm8009-l4";
|
|
L5F = "/soc/rpmh-regulator-ldof5/regulator-pm8009-l5";
|
|
pm8009_l5 = "/soc/rpmh-regulator-ldof5/regulator-pm8009-l5";
|
|
L6F = "/soc/rpmh-regulator-ldof6/regulator-pm8009-l6";
|
|
pm8009_l6 = "/soc/rpmh-regulator-ldof6/regulator-pm8009-l6";
|
|
L7F = "/soc/rpmh-regulator-ldof7/regulator-pm8009-l7";
|
|
pm8009_l7 = "/soc/rpmh-regulator-ldof7/regulator-pm8009-l7";
|
|
refgen = "/soc/refgen-regulator@ff1000";
|
|
csr = "/soc/csr@6001000";
|
|
replicator_qdss = "/soc/replicator@6046000";
|
|
replicator_out_tmc_etr = "/soc/replicator@6046000/ports/port@0/endpoint";
|
|
replicator_out_replicator1_in = "/soc/replicator@6046000/ports/port@1/endpoint";
|
|
replicator_in_tmc_etf = "/soc/replicator@6046000/ports/port@2/endpoint";
|
|
replicator_qdss1 = "/soc/replicator@604a000";
|
|
replicator1_out_funnel_swao = "/soc/replicator@604a000/ports/port@0/endpoint";
|
|
replicator1_in_replicator_out = "/soc/replicator@604a000/ports/port@1/endpoint";
|
|
tmc_etr = "/soc/tmc@6048000";
|
|
tmc_etr_in_replicator = "/soc/tmc@6048000/port/endpoint";
|
|
tmc_etf = "/soc/tmc@6047000";
|
|
tmc_etf_out_replicator = "/soc/tmc@6047000/ports/port@0/endpoint";
|
|
tmc_etf_in_funnel_merg = "/soc/tmc@6047000/ports/port@1/endpoint";
|
|
funnel_merg = "/soc/funnel@6045000";
|
|
funnel_merg_out_tmc_etf = "/soc/funnel@6045000/ports/port@0/endpoint";
|
|
funnel_merg_in_funnel_in0 = "/soc/funnel@6045000/ports/port@1/endpoint";
|
|
funnel_merg_in_funnel_in1 = "/soc/funnel@6045000/ports/port@2/endpoint";
|
|
funnel_merg_in_funnel_in2 = "/soc/funnel@6045000/ports/port@3/endpoint";
|
|
funnel_in0 = "/soc/funnel@0x6041000";
|
|
funnel_in0_out_funnel_merg = "/soc/funnel@0x6041000/ports/port@0/endpoint";
|
|
funnel_in0_in_tpdm_lpass = "/soc/funnel@0x6041000/ports/port@1/endpoint";
|
|
funnel_in0_in_audio_etm0 = "/soc/funnel@0x6041000/ports/port@2/endpoint";
|
|
funnel_in0_in_funnel_qatb = "/soc/funnel@0x6041000/ports/port@3/endpoint";
|
|
funnel_in0_in_stm = "/soc/funnel@0x6041000/ports/port@4/endpoint";
|
|
audio_etm0_out_funnel_in0 = "/soc/audio_etm0/port/endpoint";
|
|
funnel_in1 = "/soc/funnel@6042000";
|
|
funnel_in1_out_funnel_merg = "/soc/funnel@6042000/ports/port@0/endpoint";
|
|
funnel_in1_in_modem_etm0 = "/soc/funnel@6042000/ports/port@1/endpoint";
|
|
funnel_in1_in_replicator_swao = "/soc/funnel@6042000/ports/port@2/endpoint";
|
|
funnel_in1_in_funnel_modem = "/soc/funnel@6042000/ports/port@3/endpoint";
|
|
funnel_modem = "/soc/funnel@6832000";
|
|
funnel_modem_out_funnel_in1 = "/soc/funnel@6832000/ports/port@0/endpoint";
|
|
funnel_modem_in_tpda_modem_0 = "/soc/funnel@6832000/ports/port@1/endpoint";
|
|
funnel_modem_in_tpda_modem_1 = "/soc/funnel@6832000/ports/port@2/endpoint";
|
|
tpda_modem0 = "/soc/tpda@6831000";
|
|
tpda_modem_0_out_funnel_modem = "/soc/tpda@6831000/ports/port@0/endpoint";
|
|
tpda_modem_0_in_tpdm_modem_0 = "/soc/tpda@6831000/ports/port@1/endpoint";
|
|
tpda_modem1 = "/soc/tpda@6833000";
|
|
tpda_modem_1_out_funnel_modem = "/soc/tpda@6833000/ports/port@0/endpoint";
|
|
tpda_modem_1_in_tpdm_modem_1 = "/soc/tpda@6833000/ports/port@1/endpoint";
|
|
tpdm_modem0 = "/soc/tpdm@6830000";
|
|
tpdm_modem_0_out_tpda_modem_0 = "/soc/tpdm@6830000/port/endpoint";
|
|
tpdm_modem1 = "/soc/tpdm@6834000";
|
|
tpdm_modem_1_out_tpda_modem_1 = "/soc/tpdm@6834000/port/endpoint";
|
|
modem_etm0_out_funnel_in1 = "/soc/modem_etm0/port/endpoint";
|
|
dummy_eud = "/soc/dummy_sink";
|
|
eud_in_replicator_swao = "/soc/dummy_sink/port/endpoint";
|
|
replicator_swao = "/soc/replicator@6b0a000";
|
|
replicator_swao_out_eud = "/soc/replicator@6b0a000/ports/port@0/endpoint";
|
|
replicator_swao_out_funnel_in1 = "/soc/replicator@6b0a000/ports/port@1/endpoint";
|
|
replicator_swao_in_tmc_etf_swao = "/soc/replicator@6b0a000/ports/port@2/endpoint";
|
|
tmc_etf_swao = "/soc/tmc@6b09000";
|
|
tmc_etf_swao_out_replicator_swao = "/soc/tmc@6b09000/ports/port@0/endpoint";
|
|
tmc_etf_swao_in_funnel_swao = "/soc/tmc@6b09000/ports/port@1/endpoint";
|
|
swao_csr = "/soc/csr@6b0e000";
|
|
funnel_swao = "/soc/funnel@6b08000";
|
|
funnel_swao_out_tmc_etf_swao = "/soc/funnel@6b08000/ports/port@0/endpoint";
|
|
funnel_swao_in_replicator1_out = "/soc/funnel@6b08000/ports/port@1/endpoint";
|
|
funnel_swao_in_tpda_swao = "/soc/funnel@6b08000/ports/port@2/endpoint";
|
|
tpda_swao = "/soc/tpda@6b01000";
|
|
tpda_swao_out_funnel_swao = "/soc/tpda@6b01000/ports/port@0/endpoint";
|
|
tpda_swao_in_tpdm_swao0 = "/soc/tpda@6b01000/ports/port@1/endpoint";
|
|
tpda_swao_in_tpdm_swao1 = "/soc/tpda@6b01000/ports/port@2/endpoint";
|
|
tpdm_swao0 = "/soc/tpdm@6b02000";
|
|
tpdm_swao0_out_tpda_swao = "/soc/tpdm@6b02000/port/endpoint";
|
|
tpdm_swao1 = "/soc/tpdm@6b03000";
|
|
tpdm_swao1_out_tpda_swao = "/soc/tpdm@6b03000/port/endpoint";
|
|
funnel_in2 = "/soc/funnel@6043000";
|
|
funnel_in2_out_funnel_merg = "/soc/funnel@6043000/ports/port@0/endpoint";
|
|
funnel_in2_in_funnel_apss_merg = "/soc/funnel@6043000/ports/port@1/endpoint";
|
|
funnel_apss_merg = "/soc/funnel@7810000";
|
|
funnel_apss_merg_out_funnel_in2 = "/soc/funnel@7810000/ports/port@0/endpoint";
|
|
funnel_apss_merg_in_funnel_apss = "/soc/funnel@7810000/ports/port@1/endpoint";
|
|
funnel_apss_merg_in_tpda_olc = "/soc/funnel@7810000/ports/port@2/endpoint";
|
|
funnel_apss_merg_in_tpda_llm_silver = "/soc/funnel@7810000/ports/port@3/endpoint";
|
|
funnel_apss_merg_in_tpda_llm_gold = "/soc/funnel@7810000/ports/port@4/endpoint";
|
|
funnel_apss_merg_in_tpda_apss = "/soc/funnel@7810000/ports/port@5/endpoint";
|
|
tpda_olc = "/soc/tpda@7832000";
|
|
tpda_olc_out_funnel_apss_merg = "/soc/tpda@7832000/ports/port@0/endpoint";
|
|
tpda_olc_in_tpdm_olc = "/soc/tpda@7832000/ports/port@1/endpoint";
|
|
tpdm_olc = "/soc/tpdm@7830000";
|
|
tpdm_olc_out_tpda_olc = "/soc/tpdm@7830000/port/endpoint";
|
|
tpda_apss = "/soc/tpda@7862000";
|
|
tpda_apss_out_funnel_apss_merg = "/soc/tpda@7862000/ports/port@0/endpoint";
|
|
tpda_apss_in_tpdm_apss = "/soc/tpda@7862000/ports/port@1/endpoint";
|
|
tpdm_apss = "/soc/tpdm@7860000";
|
|
tpdm_apss_out_tpda_apss = "/soc/tpdm@7860000/port/endpoint";
|
|
tpda_llm_silver = "/soc/tpda@78c0000";
|
|
tpda_llm_silver_out_funnel_apss_merg = "/soc/tpda@78c0000/ports/port@0/endpoint";
|
|
tpda_llm_silver_in_tpdm_llm_silver = "/soc/tpda@78c0000/ports/port@1/endpoint";
|
|
tpdm_llm_silver = "/soc/tpdm@78a0000";
|
|
tpdm_llm_silver_out_tpda_llm_silver = "/soc/tpdm@78a0000/port/endpoint";
|
|
tpda_llm_gold = "/soc/tpda@78d0000";
|
|
tpda_llm_gold_out_funnel_apss_merg = "/soc/tpda@78d0000/ports/port@0/endpoint";
|
|
tpda_llm_gold_in_tpdm_llm_gold = "/soc/tpda@78d0000/ports/port@1/endpoint";
|
|
tpdm_llm_gold = "/soc/tpdm@78b0000";
|
|
tpdm_llm_gold_out_tpda_llm_gold = "/soc/tpdm@78b0000/port/endpoint";
|
|
funnel_apss = "/soc/funnel@7800000";
|
|
funnel_apss_out_funnel_apss_merg = "/soc/funnel@7800000/ports/port@0/endpoint";
|
|
funnel_apss_in_etm0 = "/soc/funnel@7800000/ports/port@1/endpoint";
|
|
funnel_apss_in_etm1 = "/soc/funnel@7800000/ports/port@2/endpoint";
|
|
funnel_apss_in_etm2 = "/soc/funnel@7800000/ports/port@3/endpoint";
|
|
funnel_apss_in_etm3 = "/soc/funnel@7800000/ports/port@4/endpoint";
|
|
funnel_apss_in_etm4 = "/soc/funnel@7800000/ports/port@5/endpoint";
|
|
funnel_apss_in_etm5 = "/soc/funnel@7800000/ports/port@6/endpoint";
|
|
funnel_apss_in_etm6 = "/soc/funnel@7800000/ports/port@7/endpoint";
|
|
funnel_apss_in_etm7 = "/soc/funnel@7800000/ports/port@8/endpoint";
|
|
etm0 = "/soc/etm@7040000";
|
|
etm0_out_funnel_apss = "/soc/etm@7040000/port/endpoint";
|
|
etm1 = "/soc/etm@7140000";
|
|
etm1_out_funnel_apss = "/soc/etm@7140000/port/endpoint";
|
|
etm2 = "/soc/etm@7240000";
|
|
etm2_out_funnel_apss = "/soc/etm@7240000/port/endpoint";
|
|
etm3 = "/soc/etm@7340000";
|
|
etm3_out_funnel_apss = "/soc/etm@7340000/port/endpoint";
|
|
etm4 = "/soc/etm@7440000";
|
|
etm4_out_funnel_apss = "/soc/etm@7440000/port/endpoint";
|
|
etm5 = "/soc/etm@7540000";
|
|
etm5_out_funnel_apss = "/soc/etm@7540000/port/endpoint";
|
|
etm6 = "/soc/etm@7640000";
|
|
etm6_out_funnel_apss = "/soc/etm@7640000/port/endpoint";
|
|
etm7 = "/soc/etm@7740000";
|
|
etm7_out_funnel_apss = "/soc/etm@7740000/port/endpoint";
|
|
stm = "/soc/stm@6002000";
|
|
stm_out_funnel_in0 = "/soc/stm@6002000/port/endpoint";
|
|
funnel_qatb = "/soc/funnel@6005000";
|
|
funnel_qatb_out_funnel_in0 = "/soc/funnel@6005000/ports/port@0/endpoint";
|
|
funnel_qatb_in_tpda = "/soc/funnel@6005000/ports/port@1/endpoint";
|
|
funnel_qatb_in_funnel_dl_south_1 = "/soc/funnel@6005000/ports/port@2/endpoint";
|
|
funnel_qatb_in_funnel_turing_1 = "/soc/funnel@6005000/ports/port@3/endpoint";
|
|
funnel_dl_south_1 = "/soc/funnel_1@6b53000";
|
|
funnel_dl_south_1_out_funnel_qatb = "/soc/funnel_1@6b53000/ports/port@0/endpoint";
|
|
funnel_dl_south_1_in_tpdm_wcss = "/soc/funnel_1@6b53000/ports/port@1/endpoint";
|
|
tpdm_lpass = "/soc/dummy_source";
|
|
tpdm_lpass_out_funnel_in0 = "/soc/dummy_source/port/endpoint";
|
|
tpdm_wcss = "/soc/tpdm@699c000";
|
|
tpdm_wcss_out_funnel_dl_south_1 = "/soc/tpdm@699c000/port/endpoint";
|
|
tpda = "/soc/tpda@6004000";
|
|
tpda_out_funnel_qatb = "/soc/tpda@6004000/ports/port@0/endpoint";
|
|
tpda_in_funnel_dl_mm = "/soc/tpda@6004000/ports/port@1/endpoint";
|
|
tpda_in_tpdm_dl_center = "/soc/tpda@6004000/ports/port@2/endpoint";
|
|
tpda_in_funnel_dl_south = "/soc/tpda@6004000/ports/port@3/endpoint";
|
|
tpda_in_funnel_turing = "/soc/tpda@6004000/ports/port@4/endpoint";
|
|
tpda_in_funnel_ddr_0 = "/soc/tpda@6004000/ports/port@5/endpoint";
|
|
tpda_in_funnel_gfx = "/soc/tpda@6004000/ports/port@6/endpoint";
|
|
tpda_in_tpdm_vsense = "/soc/tpda@6004000/ports/port@7/endpoint";
|
|
tpda_in_tpdm_prng = "/soc/tpda@6004000/ports/port@8/endpoint";
|
|
tpda_in_tpdm_north = "/soc/tpda@6004000/ports/port@9/endpoint";
|
|
tpda_in_tpdm_qm = "/soc/tpda@6004000/ports/port@10/endpoint";
|
|
tpda_in_tpdm_pimem = "/soc/tpda@6004000/ports/port@11/endpoint";
|
|
tpda_in_tpdm_npu = "/soc/tpda@6004000/ports/port@12/endpoint";
|
|
tpda_in_tpdm_center = "/soc/tpda@6004000/ports/port@13/endpoint";
|
|
tpda_in_tpdm_qdss = "/soc/tpda@6004000/ports/port@14/endpoint";
|
|
tpdm_qdss = "/soc/tpdm@6006000";
|
|
tpdm_qdss_out_tpda = "/soc/tpdm@6006000/port/endpoint";
|
|
funnel_dl_mm = "/soc/funnel@69C3000";
|
|
funnel_dl_mm_out_tpda = "/soc/funnel@69C3000/ports/port@0/endpoint";
|
|
funnel_dl_mm_in_tpdm_dl_mm = "/soc/funnel@69C3000/ports/port@1/endpoint";
|
|
tpdm_dl_mm = "/soc/tpdm@69c0000";
|
|
tpdm_dl_mm_out_funnel_dl_mm = "/soc/tpdm@69c0000/port/endpoint";
|
|
tpdm_dl_center = "/soc/tpdm@6c28000";
|
|
tpdm_dl_center_out_tpda = "/soc/tpdm@6c28000/port/endpoint";
|
|
funnel_dl_south = "/soc/funnel@6b53000";
|
|
funnel_dl_south_out_tpda = "/soc/funnel@6b53000/ports/port@0/endpoint";
|
|
funnel_dl_south_in_tpdm_dl_south = "/soc/funnel@6b53000/ports/port@1/endpoint";
|
|
tpdm_dl_south = "/soc/tpdm@6b52000";
|
|
tpdm_dl_south_out_funnel_dl_south = "/soc/tpdm@6b52000/port/endpoint";
|
|
funnel_turing = "/soc/funnel@6861000";
|
|
funnel_turing_out_tpda = "/soc/funnel@6861000/ports/port@0/endpoint";
|
|
funnel_turing_in_tpdm_turing = "/soc/funnel@6861000/ports/port@1/endpoint";
|
|
funnel_turing1 = "/soc/funnel_1@6861000";
|
|
funnel_turing_1_out_funnel_qatb = "/soc/funnel_1@6861000/ports/port@0/endpoint";
|
|
funnel_turing_1_in_turing_etm0 = "/soc/funnel_1@6861000/ports/port@1/endpoint";
|
|
turing_etm0_out_funnel_turing_1 = "/soc/turing_etm0/port/endpoint";
|
|
tpdm_turing = "/soc/tpdm@6860000";
|
|
tpdm_turing_out_funnel_turing = "/soc/tpdm@6860000/port/endpoint";
|
|
funnel_ddr_0 = "/soc/funnel@6a05000";
|
|
funnel_ddr_0_out_tpda = "/soc/funnel@6a05000/ports/port@0/endpoint";
|
|
funnel_ddr_0_in_tpdm_ddr = "/soc/funnel@6a05000/ports/port@1/endpoint";
|
|
tpdm_ddr = "/soc/tpdm@6a00000";
|
|
tpdm_ddr_out_funnel_ddr_0 = "/soc/tpdm@6a00000/port/endpoint";
|
|
funnel_gfx = "/soc/funnel@6943000";
|
|
funnel_gfx_out_tpda = "/soc/funnel@6943000/ports/port@0/endpoint";
|
|
funnel_gfx_in_tpdm_gfx = "/soc/funnel@6943000/ports/port@1/endpoint";
|
|
tpdm_gfx = "/soc/tpdm@6940000";
|
|
tpdm_gfx_out_funnel_gfx = "/soc/tpdm@6940000/port/endpoint";
|
|
tpdm_vsense = "/soc/tpdm@6840000";
|
|
tpdm_vsense_out_tpda = "/soc/tpdm@6840000/port/endpoint";
|
|
tpdm_prng = "/soc/tpdm@684c000";
|
|
tpdm_prng_out_tpda = "/soc/tpdm@684c000/port/endpoint";
|
|
tpdm_north = "/soc/tpdm@6b48000";
|
|
tpdm_north_out_tpda = "/soc/tpdm@6b48000/port/endpoint";
|
|
tpdm_qm = "/soc/tpdm@69d0000";
|
|
tpdm_qm_out_tpda = "/soc/tpdm@69d0000/port/endpoint";
|
|
tpdm_pimem = "/soc/tpdm@6850000";
|
|
tpdm_pimem_out_tpda = "/soc/tpdm@6850000/port/endpoint";
|
|
tpdm_center = "/soc/tpdm@6b44000";
|
|
tpdm_center_out_tpda = "/soc/tpdm@6b44000/port/endpoint";
|
|
hwevent = "/soc/hwevent@0x014066f0";
|
|
cti0_apss = "/soc/cti@78e0000";
|
|
cti1_apss = "/soc/cti@78f0000";
|
|
cti2_apss = "/soc/cti@7900000";
|
|
cti0_ddr0 = "/soc/cti@6a02000";
|
|
cti1_ddr0 = "/soc/cti@6a03000";
|
|
cti0_ddr1 = "/soc/cti@6a10000";
|
|
cti1_ddr1 = "/soc/cti@6a11000";
|
|
cti2_ddr1 = "/soc/cti@6a12000";
|
|
cti0_dlmm = "/soc/cti@69C1000";
|
|
cti1_dlmm = "/soc/cti@69C2000";
|
|
cti0_dlct = "/soc/cti@6c29000";
|
|
cti1_dlct = "/soc/cti@6c2a000";
|
|
cti0_wcss = "/soc/cti@69a4000";
|
|
cti1_wcss = "/soc/cti@69a5000";
|
|
cti2_wcss = "/soc/cti@69a6000";
|
|
cti_mss_q6 = "/soc/cti@683b000";
|
|
cti_turing = "/soc/cti@6867000";
|
|
cti0_swao = "/soc/cti@6b04000";
|
|
cti1_swao = "/soc/cti@6b05000";
|
|
cti2_swao = "/soc/cti@6b06000";
|
|
cti3_swao = "/soc/cti@6b07000";
|
|
cti_aop_m3 = "/soc/cti@6b21000";
|
|
cti_titan = "/soc/cti@6c13000";
|
|
cti_venus_arm9 = "/soc/cti@6c20000";
|
|
cti0 = "/soc/cti@6010000";
|
|
cti1 = "/soc/cti@6011000";
|
|
cti2 = "/soc/cti@6012000";
|
|
cti3 = "/soc/cti@6013000";
|
|
cti4 = "/soc/cti@6014000";
|
|
cti5 = "/soc/cti@6015000";
|
|
cti6 = "/soc/cti@6016000";
|
|
cti7 = "/soc/cti@6017000";
|
|
cti8 = "/soc/cti@6018000";
|
|
cti9 = "/soc/cti@6019000";
|
|
cti10 = "/soc/cti@601a000";
|
|
cti11 = "/soc/cti@601b000";
|
|
cti12 = "/soc/cti@601c000";
|
|
cti13 = "/soc/cti@601d000";
|
|
cti14 = "/soc/cti@601e000";
|
|
cti15 = "/soc/cti@601f000";
|
|
ipcb_tgu = "/soc/tgu@6b0c000";
|
|
tpdm_npu = "/soc/tpdm@69e1000";
|
|
tpdm_npu_out_tpda = "/soc/tpdm@69e1000/port/endpoint";
|
|
usb0 = "/soc/ssusb@a600000";
|
|
qusb_phy0 = "/soc/qusb@88e2000";
|
|
usb_qmp_dp_phy = "/soc/ssphy@88e8000";
|
|
usb_nop_phy = "/soc/usb_nop_phy";
|
|
modem_pa = "/soc/qmi-tmd-devices/modem/modem_pa";
|
|
modem_proc = "/soc/qmi-tmd-devices/modem/modem_proc";
|
|
modem_current = "/soc/qmi-tmd-devices/modem/modem_current";
|
|
modem_skin = "/soc/qmi-tmd-devices/modem/modem_skin";
|
|
modem_vdd = "/soc/qmi-tmd-devices/modem/modem_vdd";
|
|
adsp_vdd = "/soc/qmi-tmd-devices/adsp/adsp_vdd";
|
|
cdsp_vdd = "/soc/qmi-tmd-devices/cdsp/cdsp_vdd";
|
|
cxip_cdev = "/soc/cxip-cdev@1fed000";
|
|
pcm0 = "/soc/qcom,msm-pcm";
|
|
routing = "/soc/qcom,msm-pcm-routing";
|
|
compr = "/soc/qcom,msm-compr-dsp";
|
|
pcm1 = "/soc/qcom,msm-pcm-low-latency";
|
|
pcm2 = "/soc/qcom,msm-ultra-low-latency";
|
|
pcm_noirq = "/soc/qcom,msm-pcm-dsp-noirq";
|
|
trans_loopback = "/soc/qcom,msm-transcode-loopback";
|
|
compress = "/soc/qcom,msm-compress-dsp";
|
|
voip = "/soc/qcom,msm-voip-dsp";
|
|
voice = "/soc/qcom,msm-pcm-voice";
|
|
stub_codec = "/soc/qcom,msm-stub-codec";
|
|
afe = "/soc/qcom,msm-pcm-afe";
|
|
dai_hdmi = "/soc/qcom,msm-dai-q6-hdmi";
|
|
dai_hdmi_ms = "/soc/qcom,msm-dai-q6-hdmi_ms";
|
|
dai_dp = "/soc/qcom,msm-dai-q6-dp";
|
|
loopback = "/soc/qcom,msm-pcm-loopback";
|
|
loopback1 = "/soc/qcom,msm-pcm-loopback-low-latency";
|
|
pcm_dtmf = "/soc/qcom,msm-pcm-dtmf";
|
|
msm_dai_mi2s = "/soc/qcom,msm-dai-mi2s";
|
|
dai_mi2s0 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-prim";
|
|
dai_mi2s1 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-sec";
|
|
dai_mi2s2 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-tert";
|
|
dai_mi2s3 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quat";
|
|
dai_mi2s4 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quin";
|
|
dai_mi2s5 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-senary";
|
|
dai_meta_mi2s0 = "/soc/qcom,msm-dai-q6-meta-mi2s-prim";
|
|
dai_meta_mi2s1 = "/soc/qcom,msm-dai-q6-meta-mi2s-sec";
|
|
msm_dai_cdc_dma = "/soc/qcom,msm-dai-cdc-dma";
|
|
wsa_cdc_dma_0_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-0-rx";
|
|
wsa_cdc_dma_0_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-0-tx";
|
|
wsa_cdc_dma_1_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-1-rx";
|
|
wsa_cdc_dma_1_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-1-tx";
|
|
wsa_cdc_dma_2_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-wsa-cdc-dma-2-tx";
|
|
va_cdc_dma_0_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-0-tx";
|
|
va_cdc_dma_1_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-1-tx";
|
|
va_cdc_dma_2_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-2-tx";
|
|
rx_cdc_dma_0_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-0-rx";
|
|
rx_cdc_dma_1_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-1-rx";
|
|
rx_cdc_dma_2_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-2-rx";
|
|
rx_cdc_dma_3_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-3-rx";
|
|
rx_cdc_dma_4_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-4-rx";
|
|
rx_cdc_dma_5_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-5-rx";
|
|
rx_cdc_dma_6_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-6-rx";
|
|
rx_cdc_dma_7_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-7-rx";
|
|
tx_cdc_dma_0_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-0-tx";
|
|
tx_cdc_dma_1_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-1-tx";
|
|
tx_cdc_dma_2_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-2-tx";
|
|
tx_cdc_dma_3_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-3-tx";
|
|
tx_cdc_dma_4_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-4-tx";
|
|
tx_cdc_dma_5_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-tx-cdc-dma-5-tx";
|
|
lsm = "/soc/qcom,msm-lsm-client";
|
|
sb_0_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-0-rx";
|
|
sb_0_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-0-tx";
|
|
sb_1_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-1-rx";
|
|
sb_1_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-1-tx";
|
|
sb_2_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-2-rx";
|
|
sb_2_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-2-tx";
|
|
sb_3_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-3-rx";
|
|
sb_3_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-3-tx";
|
|
sb_4_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-4-rx";
|
|
sb_4_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-4-tx";
|
|
sb_5_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-5-tx";
|
|
sb_5_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-5-rx";
|
|
sb_6_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-6-rx";
|
|
sb_7_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-rx";
|
|
sb_7_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-tx";
|
|
sb_8_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-rx";
|
|
sb_8_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-tx";
|
|
sb_9_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-9-rx";
|
|
sb_9_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-9-tx";
|
|
bt_sco_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-rx";
|
|
bt_sco_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-tx";
|
|
int_fm_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-rx";
|
|
int_fm_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-tx";
|
|
afe_pcm_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-rx";
|
|
afe_pcm_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-tx";
|
|
afe_proxy_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-rx";
|
|
afe_proxy_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-tx";
|
|
incall_record_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-rx";
|
|
incall_record_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-tx";
|
|
incall_music_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-rx";
|
|
incall_music_2_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-2-rx";
|
|
proxy_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-proxy-rx";
|
|
proxy_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-proxy-tx";
|
|
usb_audio_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-rx";
|
|
usb_audio_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-tx";
|
|
hostless = "/soc/qcom,msm-pcm-hostless";
|
|
audio_apr = "/soc/qcom,msm-audio-apr";
|
|
msm_audio_ion = "/soc/qcom,msm-audio-apr/qcom,msm-audio-ion";
|
|
q6core = "/soc/qcom,msm-audio-apr/qcom,q6core-audio";
|
|
bolero = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc";
|
|
va_macro = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/va-macro@62f20000";
|
|
tx_macro = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@62ec0000";
|
|
swr2 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@62ec0000/tx_swr_master";
|
|
rx_macro = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/rx-macro@62ee0000";
|
|
swr1 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/rx-macro@62ee0000/rx_swr_master";
|
|
wsa_macro = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/wsa-macro@62f00000";
|
|
swr0 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/wsa-macro@62f00000/wsa_swr_master";
|
|
sm6150_snd = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/sound";
|
|
dai_pri_auxpcm = "/soc/qcom,msm-pri-auxpcm";
|
|
dai_sec_auxpcm = "/soc/qcom,msm-sec-auxpcm";
|
|
dai_tert_auxpcm = "/soc/qcom,msm-tert-auxpcm";
|
|
dai_quat_auxpcm = "/soc/qcom,msm-quat-auxpcm";
|
|
dai_quin_auxpcm = "/soc/qcom,msm-quin-auxpcm";
|
|
dai_sen_auxpcm = "/soc/qcom,msm-sen-auxpcm";
|
|
hdmi_dba = "/soc/qcom,msm-hdmi-dba-codec-rx";
|
|
tdm_pri_rx = "/soc/qcom,msm-dai-tdm-pri-rx";
|
|
dai_pri_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-pri-rx/qcom,msm-dai-q6-tdm-pri-rx-0";
|
|
tdm_pri_tx = "/soc/qcom,msm-dai-tdm-pri-tx";
|
|
dai_pri_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-pri-tx/qcom,msm-dai-q6-tdm-pri-tx-0";
|
|
tdm_sec_rx = "/soc/qcom,msm-dai-tdm-sec-rx";
|
|
dai_sec_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-sec-rx/qcom,msm-dai-q6-tdm-sec-rx-0";
|
|
tdm_sec_tx = "/soc/qcom,msm-dai-tdm-sec-tx";
|
|
dai_sec_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-sec-tx/qcom,msm-dai-q6-tdm-sec-tx-0";
|
|
tdm_tert_rx = "/soc/qcom,msm-dai-tdm-tert-rx";
|
|
dai_tert_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-tert-rx/qcom,msm-dai-q6-tdm-tert-rx-0";
|
|
tdm_tert_tx = "/soc/qcom,msm-dai-tdm-tert-tx";
|
|
dai_tert_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-tert-tx/qcom,msm-dai-q6-tdm-tert-tx-0";
|
|
tdm_quat_rx = "/soc/qcom,msm-dai-tdm-quat-rx";
|
|
dai_quat_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-quat-rx/qcom,msm-dai-q6-tdm-quat-rx-0";
|
|
tdm_quat_tx = "/soc/qcom,msm-dai-tdm-quat-tx";
|
|
dai_quat_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-quat-tx/qcom,msm-dai-q6-tdm-quat-tx-0";
|
|
tdm_quin_rx = "/soc/qcom,msm-dai-tdm-quin-rx";
|
|
dai_quin_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-quin-rx/qcom,msm-dai-q6-tdm-quin-rx-0";
|
|
tdm_quin_tx = "/soc/qcom,msm-dai-tdm-quin-tx";
|
|
dai_quin_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-quin-tx/qcom,msm-dai-q6-tdm-quin-tx-0";
|
|
tdm_sen_rx = "/soc/qcom,msm-dai-tdm-sen-rx";
|
|
dai_sen_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-sen-rx/qcom,msm-dai-q6-tdm-sen-rx-0";
|
|
tdm_sen_tx = "/soc/qcom,msm-dai-tdm-sen-tx";
|
|
dai_sen_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-sen-tx/qcom,msm-dai-q6-tdm-sen-tx-0";
|
|
dai_pri_spdif_rx = "/soc/qcom,msm-dai-q6-spdif-pri-rx";
|
|
dai_pri_spdif_tx = "/soc/qcom,msm-dai-q6-spdif-pri-tx";
|
|
dai_sec_spdif_rx = "/soc/qcom,msm-dai-q6-spdif-sec-rx";
|
|
dai_sec_spdif_tx = "/soc/qcom,msm-dai-q6-spdif-sec-tx";
|
|
afe_loopback_tx = "/soc/qcom,msm-dai-q6-afe-loopback-tx";
|
|
lpass_core_hw_vote = "/soc/lpass_core_hw_vote";
|
|
pil_gpu = "/soc/qcom,kgsl-hyp";
|
|
msm_bus = "/soc/qcom,kgsl-busmon";
|
|
gpu_bw_tbl = "/soc/gpu-bw-tbl";
|
|
gpubw = "/soc/qcom,gpubw";
|
|
msm_gpu = "/soc/qcom,kgsl-3d0@5000000";
|
|
kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@5040000";
|
|
gfx3d_user = "/soc/qcom,kgsl-iommu@5040000/gfx3d_user";
|
|
gfx3d_secure = "/soc/qcom,kgsl-iommu@5040000/gfx3d_secure";
|
|
gmu = "/soc/qcom,gmu@506a000";
|
|
gmu_user = "/soc/qcom,gmu@506a000/gmu_user";
|
|
gmu_kernel = "/soc/qcom,gmu@506a000/gmu_kernel";
|
|
msm_npu = "/soc/qcom,msm_npu@9800000";
|
|
aliases = "/aliases";
|
|
energy_costs = "/energy-costs";
|
|
CPU_COST_0 = "/energy-costs/core-cost0";
|
|
CPU_COST_1 = "/energy-costs/core-cost1";
|
|
CLUSTER_COST_0 = "/energy-costs/cluster-cost0";
|
|
CLUSTER_COST_1 = "/energy-costs/cluster-cost1";
|
|
firmware = "/firmware";
|
|
android = "/firmware/android";
|
|
shared_meta = "/firmware/android/vbmeta";
|
|
reserved_memory = "/reserved-memory";
|
|
hyp_region = "/reserved-memory/hyp_region@85700000";
|
|
xbl_aop_mem = "/reserved-memory/xbl_aop_mem@85d00000";
|
|
sec_apps_mem = "/reserved-memory/sec_apps_region@85fff000";
|
|
smem_region = "/reserved-memory/smem@86000000";
|
|
removed_region = "/reserved-memory/removed_region@86200000";
|
|
pil_camera_mem = "/reserved-memory/camera_region@8ab00000";
|
|
pil_modem_mem = "/reserved-memory/modem_region@8b000000";
|
|
pil_video_mem = "/reserved-memory/pil_video_region@93400000";
|
|
pil_cdsp_mem = "/reserved-memory/cdsp_regions@93900000";
|
|
pil_adsp_mem = "/reserved-memory/pil_adsp_region@95700000";
|
|
wlan_msa_mem = "/reserved-memory/wlan_msa_region@97500000";
|
|
npu_mem = "/reserved-memory/npu_region@97680000";
|
|
pil_ipa_fw_mem = "/reserved-memory/ips_fw_region@97700000";
|
|
pil_ipa_gsi_mem = "/reserved-memory/ipa_gsi_region@97710000";
|
|
pil_gpu_mem = "/reserved-memory/gpu_region@97715000";
|
|
qseecom_mem = "/reserved-memory/qseecom_region@9e400000";
|
|
cdsp_sec_mem = "/reserved-memory/cdsp_sec_regions@0x9f800000";
|
|
adsp_mem = "/reserved-memory/adsp_region";
|
|
cdsp_mem = "/reserved-memory/cdsp_region";
|
|
qseecom_ta_mem = "/reserved-memory/qseecom_ta_region";
|
|
sp_mem = "/reserved-memory/sp_region";
|
|
secure_display_memory = "/reserved-memory/secure_display_region";
|
|
cont_splash_memory = "/reserved-memory/cont_splash_region@9c000000";
|
|
disp_rdump_memory = "/reserved-memory/disp_rdump_region@9c000000";
|
|
dfps_data_memory = "/reserved-memory/dfps_data_region@9d700000";
|
|
dump_mem = "/reserved-memory/mem_dump_region";
|
|
};
|
|
};
|