From 1af79995443ac2ed092391561fe93c8b70c5bd9f Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 20 Dec 2016 11:25:12 +0100
Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers
Kernel would lower the divider on first CLK change and cause the
lock up.
---
arch/arm/mach-sunxi/clock_sun6i.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 8e84062bd7..8705fa5fc5 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -117,11 +117,10 @@ void clock_set_pll1(unsigned int clk)
int k = 1;
int m = 1;
- if (clk > 1152000000) {
+ if (clk >= 1368000000) {
+ k = 3;
+ } else if (clk >= 768000000) {
k = 2;
- } else if (clk > 768000000) {
- k = 4;
- m = 2;
}
/* Switch to 24MHz clock while changing PLL1 */
--
2.31.0