177 lines
5.9 KiB
C
177 lines
5.9 KiB
C
/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS405_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_QCS405_H
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#define GPLL0_OUT_MAIN 0
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#define GPLL0_AO_CLK_SRC 1
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#define GPLL1_OUT_MAIN 2
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#define GPLL3_OUT_MAIN 3
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#define GPLL4_OUT_MAIN 4
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#define GPLL0_AO_OUT_MAIN 5
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#define GPLL0_SLEEP_CLK_SRC 6
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#define GPLL6 7
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#define GPLL6_OUT_AUX 8
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#define APSS_AHB_CLK_SRC 9
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#define BLSP1_QUP0_I2C_APPS_CLK_SRC 10
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#define BLSP1_QUP0_SPI_APPS_CLK_SRC 11
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 12
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 13
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 14
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 15
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 16
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 17
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 18
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 19
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#define BLSP1_UART0_APPS_CLK_SRC 20
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#define BLSP1_UART1_APPS_CLK_SRC 21
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#define BLSP1_UART2_APPS_CLK_SRC 22
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#define BLSP1_UART3_APPS_CLK_SRC 23
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#define BLSP2_QUP0_I2C_APPS_CLK_SRC 24
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#define BLSP2_QUP0_SPI_APPS_CLK_SRC 25
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#define BLSP2_UART0_APPS_CLK_SRC 26
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#define BYTE0_CLK_SRC 27
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#define EMAC_CLK_SRC 28
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#define EMAC_PTP_CLK_SRC 29
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#define ESC0_CLK_SRC 30
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#define GCC_APSS_AHB_CLK 31
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#define GCC_APSS_AXI_CLK 32
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#define GCC_BIMC_APSS_AXI_CLK 33
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#define GCC_BIMC_GFX_CLK 34
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#define GCC_BIMC_MDSS_CLK 35
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#define GCC_BLSP1_AHB_CLK 36
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#define GCC_BLSP1_QUP0_I2C_APPS_CLK 37
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#define GCC_BLSP1_QUP0_SPI_APPS_CLK 38
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 39
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 40
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 41
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 42
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 43
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 44
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 45
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 46
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#define GCC_BLSP1_UART0_APPS_CLK 47
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#define GCC_BLSP1_UART1_APPS_CLK 48
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#define GCC_BLSP1_UART2_APPS_CLK 49
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#define GCC_BLSP1_UART3_APPS_CLK 50
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#define GCC_BLSP2_AHB_CLK 51
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#define GCC_BLSP2_QUP0_I2C_APPS_CLK 52
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#define GCC_BLSP2_QUP0_SPI_APPS_CLK 53
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#define GCC_BLSP2_UART0_APPS_CLK 54
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#define GCC_BOOT_ROM_AHB_CLK 55
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#define GCC_GENI_IR_H_CLK 57
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#define GCC_ETH_AXI_CLK 58
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#define GCC_ETH_PTP_CLK 59
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#define GCC_ETH_RGMII_CLK 60
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#define GCC_ETH_SLAVE_AHB_CLK 61
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#define GCC_GENI_IR_S_CLK 62
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#define GCC_GP1_CLK 63
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#define GCC_GP2_CLK 64
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#define GCC_GP3_CLK 65
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#define GCC_MDSS_AHB_CLK 66
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#define GCC_MDSS_AXI_CLK 67
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#define GCC_MDSS_BYTE0_CLK 68
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#define GCC_MDSS_ESC0_CLK 69
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#define GCC_MDSS_HDMI_APP_CLK 70
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#define GCC_MDSS_HDMI_PCLK_CLK 71
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#define GCC_MDSS_MDP_CLK 72
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#define GCC_MDSS_PCLK0_CLK 73
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#define GCC_MDSS_VSYNC_CLK 74
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#define GCC_OXILI_AHB_CLK 75
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#define GFX3D_CLK_SRC 76
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#define GCC_PCIE_0_AUX_CLK 77
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#define GCC_PCIE_0_CFG_AHB_CLK 78
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#define GCC_PCIE_0_MSTR_AXI_CLK 79
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#define GCC_PCIE_0_PIPE_CLK 80
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#define GCC_PCIE_0_SLV_AXI_CLK 81
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#define GCC_PCNOC_USB2_CLK 82
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#define GCC_PCNOC_USB3_CLK 83
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#define GCC_PDM2_CLK 84
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#define GCC_PDM_AHB_CLK 85
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#define VSYNC_CLK_SRC 86
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#define GCC_PRNG_AHB_CLK 87
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#define GCC_PWM0_XO512_CLK 88
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#define GCC_PWM1_XO512_CLK 89
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#define GCC_PWM2_XO512_CLK 90
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#define GCC_SDCC1_AHB_CLK 91
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#define GCC_SDCC1_APPS_CLK 92
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#define GCC_SDCC1_ICE_CORE_CLK 93
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#define GCC_SDCC2_AHB_CLK 94
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#define GCC_SDCC2_APPS_CLK 95
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#define GCC_SYS_NOC_USB3_CLK 96
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#define GCC_USB20_MOCK_UTMI_CLK 97
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#define GCC_USB2A_PHY_SLEEP_CLK 98
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#define GCC_USB30_MASTER_CLK 99
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#define GCC_USB30_MOCK_UTMI_CLK 100
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#define GCC_USB30_SLEEP_CLK 101
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#define GCC_USB3_PHY_AUX_CLK 102
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#define GCC_USB3_PHY_PIPE_CLK 103
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#define GCC_USB_HS_PHY_CFG_AHB_CLK 104
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#define GCC_USB_HS_SYSTEM_CLK 105
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#define GCC_OXILI_GFX3D_CLK 106
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#define GP1_CLK_SRC 107
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#define GP2_CLK_SRC 108
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#define GP3_CLK_SRC 109
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#define HDMI_APP_CLK_SRC 110
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#define HDMI_PCLK_CLK_SRC 111
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#define MDP_CLK_SRC 112
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#define PCIE_0_AUX_CLK_SRC 113
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#define PCIE_0_PIPE_CLK_SRC 114
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#define PCLK0_CLK_SRC 115
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#define PDM2_CLK_SRC 116
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#define SDCC1_APPS_CLK_SRC 117
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#define SDCC1_ICE_CORE_CLK_SRC 118
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#define SDCC2_APPS_CLK_SRC 119
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#define USB20_MOCK_UTMI_CLK_SRC 120
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#define USB30_MASTER_CLK_SRC 121
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#define USB30_MOCK_UTMI_CLK_SRC 122
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#define USB3_PHY_AUX_CLK_SRC 123
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#define USB_HS_SYSTEM_CLK_SRC 124
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#define WCNSS_M_CLK 125
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#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 126
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#define MDSS_MDP_VOTE_CLK 127
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#define MDSS_ROTATOR_VOTE_CLK 128
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#define GCC_BIMC_GPU_CLK 129
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#define GCC_GTCU_AHB_CLK 130
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#define GCC_GFX_TCU_CLK 131
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#define GCC_GFX_TBU_CLK 132
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#define GCC_SMMU_CFG_CLK 133
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#define GCC_APSS_TCU_CLK 134
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#define GCC_CRYPTO_AHB_CLK 135
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#define GCC_CRYPTO_AXI_CLK 136
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#define GCC_CRYPTO_CLK 137
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#define GCC_MDP_TBU_CLK 138
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#define GCC_QDSS_DAP_CLK 139
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#define GCC_BIAS_PLL_MISC_RESET_CLK 142
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#define GCC_BIAS_PLL_AHB_CLK 143
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#define GCC_BIAS_PLL_AON_CLK 144
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#define GCC_GENI_IR_BCR 0
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#define GCC_USB_HS_BCR 1
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#define GCC_USB2_HS_PHY_ONLY_BCR 2
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#define GCC_QUSB2_PHY_BCR 3
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#define GCC_USB_HS_PHY_CFG_AHB_BCR 4
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#define GCC_USB2A_PHY_BCR 5
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#define GCC_USB3_PHY_BCR 6
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#define GCC_USB_30_BCR 7
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#define GCC_USB3PHY_PHY_BCR 8
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#define GCC_PCIE_0_BCR 9
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#define GCC_PCIE_0_PHY_BCR 10
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#define GCC_PCIE_0_LINK_DOWN_BCR 11
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#define GCC_PCIEPHY_0_PHY_BCR 12
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#define GCC_EMAC_BCR 13
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#define GCC_BIAS_PLL_BCR 14
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#endif
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