23 lines
584 B
Plaintext
23 lines
584 B
Plaintext
* QCOM LLCC PMU Bindings
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This represents the miss counters located in the LLCC hardware counters.
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Only one event is supported:
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0x1000 - LLCC misses
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The follow section describes the LLCC PMU DT node binding.
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Required properties:
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- compatible : Shall be "qcom,qcom-llcc-pmu"
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- reg : There shall be one resource, a pair of the form
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< base_address total_size > representing the DDR_LAGG
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region.
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- reg-names : Shall be "lagg-base".
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Example:
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llcc_pmu: llcc-pmu {
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compatible = "qcom,qcom-llcc-pmu";
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reg = < 0x090CC000 0x300 >;
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reg-names = "lagg-base";
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};
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