50 lines
1.9 KiB
Plaintext
50 lines
1.9 KiB
Plaintext
* MSM PM
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PM is the low power management device for MSM (Snapdragon class) chipsets.
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This device sets up different components to do low power modes and registers with
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the kernel to be notified of idle and suspend states and when called, follows
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through the set of instructions in putting the application cores to the lowest
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power mode possible.
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The PC debug counter reserves 16 registers in the IMEM memory space which maintains
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a count on the state of power collapse on each core. This count will be useful to
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debug the power collapse state on each core.
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The required properties for PM are:
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- compatible: "qcom,pm"
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The optional properties are:
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- reg: physical IMEM address reserved for PC counters and the size
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- qcom,use-sync-timer: Indicates whether the target uses the synchronized QTimer.
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- qcom,synced-clocks: Indicates that all cpus running off a single clock source and to
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instantiate the necessary clock source.
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- qcom,pc-resets-timer: Indicates that the timer gets reset during power collapse.
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- qcom,tz-flushes-cache: Indicates that TZ flushes all of the cache during
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power collapse. MSM PM can decide to not perform cache flush operations to
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reduce latency associated with L2 PC.
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- qcom,saw-turns-off-pll: Indicates that the CPU's PLL can be managed from SAW
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hardware. On such targets software management of PLL is not required. If
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this property is specified then qcom,synced-clocks would be ignored.
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- qcom,no-pll-switch-for-retention: Boolean property, to indicate that the cpu
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clock can be sourced even from the HFPLL even when the cpu is in
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retention, and need not be switched to an always on pll. If this flag
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is set then the cpu clock is not ramped down when entering retention or
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ramped up on exiting retention.
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Example 1:
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qcom,pm@fe800664 {
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compatible = "qcom,pm";
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reg = <0xfe800664 0x40>;
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qcom,use-sync-timer;
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};
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Example 2:
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qcom,pm@fe800664 {
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compatible = "qcom,pm";
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reg = <0xfe800664 0x40>;
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qcom,saw-turns-off-pll;
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};
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