91 lines
3.1 KiB
Plaintext
91 lines
3.1 KiB
Plaintext
Qualcomm Technologies Inc. EMAC Gigabit Ethernet controller
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This network controller consists of the MAC and
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RGMII IO Macro for interfacing with PHY.
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Required properties:
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emac_hw node:
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- compatible: Should be "qcom,emac-dwc-eqos"
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- reg: Offset and length of the register regions for the mac and io-macro
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- interrupts: Interrupt number used by this controller
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- io-macro-info: Internal io-macro-info
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- emac_emb_smmu: Internal emac smmu node
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- qcom,phy-reset-delay-msecs is for delays
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The 1st cell is reset pulse in milli seconds.
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The 2nd cell is reset post-delay in milli seconds.
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Optional:
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- qcom,msm-bus,name: String representing the client-name
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- qcom,msm-bus,num-cases: Total number of usecases
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- qcom,msm-bus,num-paths: Total number of master-slave pairs
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- qcom,msm-bus,vectors-KBps: Arrays of unsigned integers representing:
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master-id, slave-id, arbitrated bandwidth
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in KBps, instantaneous bandwidth in KBps
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qcom,bus-vector-names: specifies string IDs for the corresponding bus vectors
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in the same order as qcom,msm-bus,vectors-KBps property.
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- qcom,arm-smmu: Boolean, if present enables EMAC SMMU support in sdxpoorwills.
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Internal io-macro-info:
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- io-macro-bypass-mode: <0 or 1> internal or external delay configuration
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- io-interface: <rgmii/mii/rmii> PHY interface used
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Internal emac_emb_smmu:
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- compatible: Should be "qcom,emac-smmu-embedded".
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- qcom,smmu-s1-bypass: Boolean, if present S1 bypass is enabled.
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- iommus: Includes the <&smmu_phandle stream_id size> pair for each context
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bank.
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- qcom,iova-mapping: <starting_address size> of the smmu context bank.
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Example:
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soc {
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emac_hw: qcom,emac@00020000 {
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compatible = "qcom,emac-dwc-eqos";
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qcom,arm-smmu;
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reg = <0x20000 0x10000>,
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<0x36000 0x100>;
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<0x3D00000 0x300000>;
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reg-names = "emac-base", "rgmii-base";
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interrupts = <0 62 4>, <0 60 4>,
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<0 49 4>, <0 50 4>,
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<0 51 4>, <0 52 4>,
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<0 53 4>, <0 54 4>,
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<0 55 4>, <0 56 4>,
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<0 57 4>;
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interrupt-names = "sbd-intr", "lpi-intr",
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"phy-intr", "tx-ch0-intr",
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"tx-ch1-intr", "tx-ch2-intr",
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"tx-ch3-intr", "tx-ch4-intr",
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"rx-ch0-intr", "rx-ch1-intr",
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"rx-ch2-intr", "rx-ch3-intr";
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qcom,msm-bus,name = "emac";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<98 512 0 0>, <1 781 0 0>, /* No vote */
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<98 512 1250 0>, <1 781 0 40000>, /* 10Mbps vote */
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<98 512 12500 0>, <1 781 0 40000>, /* 100Mbps vote */
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<98 512 125000 0>, <1 781 0 40000>; /* 1000Mbps vote */
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qcom,bus-vector-names = "10", "100", "1000";
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clock-names = "emac_axi_clk", "emac_ptp_clk",
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"emac_rgmii_clk", "emac_slv_ahb_clk";
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qcom,phy-reset = <&tlmm 79 GPIO_ACTIVE_HIGH>;
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qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>;
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qcom,phy-reset-delay-msecs = <10 50>;
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gdsc_emac-supply = <&emac_gdsc>;
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io-macro-info {
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io-macro-bypass-mode = <0>;
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io-interface = "rgmii";
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};
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emac_emb_smmu: emac_emb_smmu {
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compatible = "qcom,emac-smmu-embedded";
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qcom,smmu-s1-bypass;
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iommus = <&apps_smmu 0x3C0 0x0>;
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qcom,iova-mapping = <0x80000000 0x40000000>;
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};
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};
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}
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